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Commit Graph

1138 Commits

Author SHA1 Message Date
Bjorn Helgaas
ec3619abbf Merge branch 'pci/controller/iommu-map'
- Add host bridge .enable_device() and .disable_device() hooks for bridges
  that need to configure things like Requester ID to StreamID mapping when
  enabling devices (Frank Li)

- Add imx6 Requester ID to StreamID mapping configuration when enabling
  devices (Frank Li)

- Extend struct pci_ecam_ops with .enable_device() and .disable_device()
  hooks so drivers that use pci_host_common_probe() instead of their own
  .probe() have a way to set the .enable_device() callbacks (Marc Zyngier)

- Convert pcie-apple StreamID mapping configuration from a bus notifier to
  the .enable_device() and .disable_device() callbacks (Marc Zyngier)

* pci/controller/iommu-map:
  PCI: apple: Convert to {en,dis}able_device() callbacks
  PCI: host-generic: Allow {en,dis}able_device() to be provided via pci_ecam_ops
  PCI: imx6: Add IOMMU and ITS MSI support for i.MX95
  PCI: Add enable_device() and disable_device() callbacks for bridges
2025-01-23 13:04:53 -06:00
Bjorn Helgaas
1108d677da PCI: dwc: Simplify config resource lookup
If platform_get_resource_byname("config") fails, return error immediately
and unindent the normal path.  No functional change intended.

Link: https://lore.kernel.org/r/20250117235119.712043-1-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-20 12:39:38 -06:00
Bjorn Helgaas
b881532991 PCI: imx6: Clean up comments and whitespace
For readability, fix typos and comments that needlessly exceed 80 columns.

Link: https://lore.kernel.org/r/20250118210727.795559-1-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-20 12:38:14 -06:00
Richard Zhu
9d6b1bd6b3 PCI: imx6: Add i.MX8MQ, i.MX8Q and i.MX95 PM support
Add i.MX8MQ, i.MX8Q and i.MX95 PCIe suspend/resume support.

Link: https://lore.kernel.org/r/20241126075702.4099164-10-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-18 15:04:23 -06:00
Frank Li
a528d1a725 PCI: imx6: Use DWC common suspend resume method
Call common DWC suspend/resume function. Use DWC common iATU method to
send out PME_TURN_OFF message.

In old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD in iATU Ctrl2 register
is reserved, so the generic DWC implementation of sending the PME_Turn_Off
message using a dummy MMIO write cannot be used. Use the previous method to
kick off PME_TURN_OFF message for these platforms.

The System Reset Control (SRC) interface is used to toggle 'turnoff_reset'
to send PME_TURN_OFF and since the DWC implementation is used, it is not
needed now.

Replace the imx_pcie_stop_link() and imx_pcie_host_exit() by
dw_pcie_suspend_noirq() in imx_pcie_suspend_noirq().

Since dw_pcie_suspend_noirq() already does these, see below call stack:

  dw_pcie_suspend_noirq()
    dw_pcie_stop_link()
      imx_pcie_stop_link()
    pci->pp.ops->deinit()
      imx_pcie_host_exit()

Replace the imx_pcie_host_init(), dw_pcie_setup_rc() and
imx_pcie_start_link() by dw_pcie_resume_noirq() in imx_pcie_resume_noirq().

Since dw_pcie_resume_noirq() already does these, see below call stack:

  dw_pcie_resume_noirq()
    pci->pp.ops->init()
      imx_pcie_host_init()
    dw_pcie_setup_rc()
    dw_pcie_start_link()
      imx_pcie_start_link(;

Link: https://lore.kernel.org/r/20241126075702.4099164-9-hongxing.zhu@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2025-01-18 15:04:23 -06:00
Bjorn Helgaas
ec57335b81 PCI: dwc: Add dw_pcie_suspend_noirq(), dw_pcie_resume_noirq() stubs for !CONFIG_PCIE_DW_HOST
Previously pcie-designware.h declared dw_pcie_suspend_noirq() and
dw_pcie_resume_noirq() unconditionally, even though they were only
implemented when CONFIG_PCIE_DW_HOST was defined.

Add no-op stubs for them when CONFIG_PCIE_DW_HOST is not defined so
drivers that support both Root Complex and Endpoint modes don't need

Link: https://lore.kernel.org/r/20250117213810.GA656803@bhelgaas
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2025-01-18 15:03:40 -06:00
Richard Zhu
112aba9a79 PCI: dwc: Remove LTSSM state test in dw_pcie_suspend_noirq()
It's safe to send PME_TURN_OFF message regardless of whether the link is up
or down, so don't test the LTSSM state before sending the PME_TURN_OFF
message.

Only print an error message when the LTSSM is not in DETECT or POLL. There
shouldn't be an error when no Endpoint is connected at all.

Link: https://lore.kernel.org/r/20241210081557.163555-3-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-18 13:38:34 -06:00
Richard Zhu
86a016e278 PCI: dwc: Always stop link in the dw_pcie_suspend_noirq
On the i.MX8QM, PCIe link can't be re-established again in
dw_pcie_resume_noirq(), if the LTSSM_EN bit is not cleared
properly in dw_pcie_suspend_noirq().

So, add dw_pcie_stop_link() to dw_pcie_suspend_noirq() to fix
this issue and to align the suspend/resume functions since there
is dw_pcie_start_link() in dw_pcie_resume_noirq() already.

Fixes: 4774faf854 ("PCI: dwc: Implement generic suspend/resume functionality")
Link: https://lore.kernel.org/r/20241210081557.163555-2-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-18 11:35:26 -06:00
Niklas Cassel
ec9fd499b9 PCI: dw-rockchip: Don't wait for link since we can detect Link Up
The Root Complex specific device tree binding for pcie-dw-rockchip has the
'sys' interrupt marked as required.

The driver requests the 'sys' IRQ unconditionally, and errors out if not
provided.

Thus, we can unconditionally set 'use_linkup_irq', so dw_pcie_host_init()
doesn't wait for the link to come up.

This will skip the wait for link up (since the bus will be enumerated once
the link up IRQ is triggered), which reduces the bootup time.

Link: https://lore.kernel.org/r/20250113-rockchip-no-wait-v1-1-25417f37b92f@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2025-01-18 11:35:25 -06:00
Niklas Cassel
0e0b45ab5d PCI: dw-rockchip: Enumerate endpoints based on dll_link_up IRQ
Most boards using the pcie-dw-rockchip PCIe controller lack standard
hotplug support.

Thus, when an endpoint is attached to the SoC, users have to rescan the bus
manually to enumerate the device. This can be avoided by using the
'dll_link_up' interrupt in the combined system interrupt 'sys'.

Once the 'dll_link_up' IRQ is received, the bus underneath the host bridge
is scanned to enumerate PCIe endpoint devices.

This implements the same functionality that was implemented in the DWC
based pcie-qcom driver in 4581403f67 ("PCI: qcom: Enumerate endpoints
based on Link up event in 'global_irq' interrupt").

The Root Complex specific device tree binding for pcie-dw-rockchip already
has the 'sys' interrupt marked as required, so there is no need to update
the device tree binding. This also means that we can request the 'sys' IRQ
unconditionally.

Link: https://lore.kernel.org/r/20241127145041.3531400-2-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: commit log, squash Pei Xiao's redundant dev_err() fix from
https://lore.kernel.org/r/327718207d3cd72847c079ff9d56eb246744c182.1736126067.git.xiaopei01@kylinos.cn,
squash Niklas's #define change from https://lore.kernel.org/r/20250103095812.2408364-2-cassel@kernel.org]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-18 11:35:25 -06:00
Krishna chaitanya chundru
f0639013d3 PCI: qcom: Update ICC and OPP values after Link Up event
4581403f67 ("PCI: qcom: Enumerate endpoints based on Link up event in
'global_irq' interrupt") added the Link Up-based enumeration support, but
did not update the ICC/OPP vote once link is up. Before that, the update
happened during probe and the endpoints may or may not be enumerated at
that time, so the ICC/OPP vote was not guaranteed to be accurate.

With Link Up-based enumeration support, the driver can request the accurate
vote based on the PCIe link.

Call qcom_pcie_icc_opp_update() in qcom_pcie_global_irq_thread() after
enumerating the endpoints.

Fixes: 4581403f67 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt")
Link: https://lore.kernel.org/r/20241123-remove_wait2-v5-3-b5f9e6b794c2@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2025-01-18 11:35:18 -06:00
Krishna chaitanya chundru
36971d6c5a PCI: qcom: Don't wait for link if we can detect Link Up
If we have a 'global' IRQ for Link Up events, we need not wait for the
link to be up during PCI initialization, which reduces startup time.

Check for 'global' IRQ, and if present, set 'use_linkup_irq',
so dw_pcie_host_init() doesn't wait for the link to come up.

Link: https://lore.kernel.org/r/20241123-remove_wait2-v5-2-b5f9e6b794c2@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2025-01-18 11:35:11 -06:00
Krishna chaitanya chundru
8d3bf19f1b PCI: dwc: Don't wait for link up if driver can detect Link Up event
If the driver can detect the Link Up event and enumerate downstream devices
at that time, we need not wait here.

Skip waiting for link to come up if the driver supports 'use_linkup_irq'.

Link: https://lore.kernel.org/r/20241123-remove_wait2-v5-1-b5f9e6b794c2@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: wrap comment, update commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2025-01-18 11:35:02 -06:00
Niklas Cassel
574913f9e1 PCI: dwc: Fix potential truncation in dw_pcie_edma_irq_verify()
Increase the size of the string buffer to avoid potential truncation in
dw_pcie_edma_irq_verify().

This fixes the following build warning when compiling with W=1:

  drivers/pci/controller/dwc/pcie-designware.c: In function ‘dw_pcie_edma_detect’:
  drivers/pci/controller/dwc/pcie-designware.c:989:50: warning: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 3 [-Wformat-truncation=]
    989 |                 snprintf(name, sizeof(name), "dma%d", pci->edma.nr_irqs);
        |                                                  ^~

Link: https://lore.kernel.org/r/20250104002119.2681246-2-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-18 11:34:48 -06:00
Krzysztof Kozlowski
ad9afd7503 PCI: dra7xx: Use syscon_regmap_lookup_by_phandle_args
Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over
syscon_regmap_lookup_by_phandle() combined with getting the syscon
argument.  Except simpler code this annotates within one line that given
phandle has arguments, so grepping for code would be easier.

There is also no real benefit in printing errors on missing syscon
argument, because this is done just too late: runtime check on
static/build-time data.  Dtschema and Devicetree bindings offer the
static/build-time check for this already.

Link: https://lore.kernel.org/r/20250112-syscon-phandle-args-pci-v1-1-fcb6ebcc0afc@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2025-01-16 14:38:53 -06:00
Krzysztof Kozlowski
149fc35734 PCI: layerscape: Use syscon_regmap_lookup_by_phandle_args
Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over
syscon_regmap_lookup_by_phandle() combined with getting the syscon
argument.  Except simpler code this annotates within one line that given
phandle has arguments, so grepping for code would be easier.

Link: https://lore.kernel.org/r/20250112-syscon-phandle-args-pci-v1-2-fcb6ebcc0afc@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Roy Zang <Roy.Zang@nxp.com>
2025-01-16 14:38:36 -06:00
Richard Zhu
6dd24b0a85 PCI: imx6: Remove surplus imx7d_pcie_init_phy() function
This function essentially duplicates imx7d_pcie_enable_ref_clk(). So remove
it.

Link: https://lore.kernel.org/r/20241126075702.4099164-8-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-16 14:29:38 -06:00
Richard Zhu
93d883f890 PCI: imx6: Add missing reference clock disable logic
Ensure the *_enable_ref_clk() function is symmetric by addressing missing
disable parts on some platforms.

Fixes: d0a75c791f ("PCI: imx6: Factor out ref clock disable to match enable")
Link: https://lore.kernel.org/r/20241126075702.4099164-7-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-16 14:29:38 -06:00
Richard Zhu
ef61c7d8d0 PCI: imx6: Deassert apps_reset in imx_pcie_deassert_core_reset()
Since the apps_reset is asserted in imx_pcie_assert_core_reset(), it should
be deasserted in imx_pcie_deassert_core_reset().

Fixes: 9b3fe6796d ("PCI: imx6: Add code to support i.MX7D")
Link: https://lore.kernel.org/r/20241126075702.4099164-6-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-16 14:29:38 -06:00
Richard Zhu
f068ffdd03 PCI: imx6: Skip controller_id generation logic for i.MX7D
The i.MX7D only has one PCIe controller, so controller_id should always be
0. The previous code is incorrect although yielding the correct result.

Fix by removing "IMX7D" from the switch case branch.

Fixes: 2d8ed461db ("PCI: imx6: Add support for i.MX8MQ")
Link: https://lore.kernel.org/r/20241126075702.4099164-5-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-16 14:29:29 -06:00
Richard Zhu
7ab93e6a08 PCI: imx6: Fetch dbi2 and iATU base addesses from DT
Since dw_pcie_get_resources() gets the dbi2 and iATU base addresses from
DT, remove the code from the imx6 driver that does the same.

Upstream DTSes have not enabled Endpoint function. So nothing is broken for
old upstream DTBs.

Link: https://lore.kernel.org/r/20241126075702.4099164-4-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-16 14:22:07 -06:00
Frank Li
de22e20589 PCI: imx6: Configure PHY based on Root Complex or Endpoint mode
Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode,
and fix the Root Complex (RC) mode being hardcoded using a drvdata mode
check.

Fixes: 8026f2d8e8 ("PCI: imx6: Call common PHY API to set mode, speed, and submode")
Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-6-c4bfa5193288@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
2025-01-16 14:21:53 -06:00
Richard Zhu
137250911f PCI: imx6: Add Refclk for i.MX95 PCIe
Add "ref" clock to enable Refclk. To avoid breaking DT backwards
compatibility, the i.MX95 "ref" clock is optional. Use
devm_clk_get_optional() to fetch i.MX95 PCIe optional clocks in driver.

If using external clock, "ref" clock should point to external reference.

If using internal clock, CREF_EN in LAST_TO_REG controls reference output,
implemented in drivers/clk/imx/clk-imx95-blk-ctl.c.

Link: https://lore.kernel.org/r/20241126075702.4099164-3-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2025-01-16 14:20:37 -06:00
Frank Li
687aedb73a PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support
Add support for the i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe
Endpoint (EP). On the i.MX8Q platforms, the PCI bus addresses differ
from the CPU addresses. However, the DesignWare (DWC) driver already
handles this in the common code.

Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-7-c4bfa5193288@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2025-01-16 14:18:14 -06:00
Frank Li
ce4c430172 PCI: imx6: Add IOMMU and ITS MSI support for i.MX95
For the i.MX95, the configuration of a LUT is necessary to convert PCIe
Requester IDs (RIDs) to StreamIDs, which are used by both IOMMU and ITS.
This involves checking msi-map and iommu-map device tree properties to
ensure consistent mapping of Requester IDs to the same StreamIDs.

Subsequently, LUT-related registers are configured. If a msi-map isn't
detected, the platform relies on DWC built-in controller for MSIs that
do not need StreamIDs.

Implement PCI bus callback function to handle enable_device() and
disable_device() operations, setting up the LUT whenever a new PCI
device is enabled.

Known limitations:

  - If iommu-map exists in the device tree but the IOMMU controller is
    disabled, StreamIDs are programmed into the LUT. However, if a RID
    is out of range of the iommu-map, enabling the PCI device would
    result in a failure, although the PCI device can work without the
    IOMMU.

  - If msi-map exists in the device tree but the MSI controller is
    disabled, MSIs will not work. The DWC driver skips initializing the
    built-in MSI controller, falling back to legacy PCI INTx only.

Link: https://lore.kernel.org/r/20250114-imx95_lut-v9-2-39f58dbed03a@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: fix uninitialized "sid" in imx_pcie_enable_device()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
2025-01-15 14:47:24 -06:00
Cristian Ciocaltea
10106d5c1f PCI: exynos: Switch to devm_clk_bulk_get_all_enabled()
The helper devm_clk_bulk_get_all_enable() missed to return the number of
clocks stored in the clk_bulk_data table referenced by the clks
argument and, therefore, will be dropped.

Use the newly introduced devm_clk_bulk_get_all_enabled() variant
instead, which is consistent with devm_clk_bulk_get_all() in terms of
the returned value:

 > 0 if one or more clocks have been stored
 = 0 if there are no clocks
 < 0 if an error occurred

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241217-clk_bulk_ena_fix-v5-2-aafbbb245155@collabora.com
Acked-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-12-23 12:53:52 -08:00
Niklas Cassel
b61fef0813
PCI: artpec6: Implement dw_pcie_ep operation get_features
All non-DWC EPC drivers implement (struct pci_epc *)->ops->get_features().
All DWC EPC drivers implement (struct dw_pcie_ep *)->ops->get_features(),
except for pcie-artpec6.c.

epc_features has been required in pci-epf-test.c since commit 6613bc2301
("PCI: endpoint: Fix NULL pointer dereference for ->get_features()").

A follow-up commit will make further use of epc_features in EPC core code.

Implement epc_features in the only EPC driver where it is currently not
implemented.

Link: https://lore.kernel.org/r/20241213143301.4158431-12-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2024-12-18 21:51:47 +00:00
Niklas Cassel
129f6af747
PCI: dwc: ep: Add 'address' alignment to 'size' check in dw_pcie_prog_ep_inbound_atu()
dw_pcie_prog_ep_inbound_atu() is used to program an inbound iATU in
"BAR Match Mode".

A memory address returned by e.g. kmalloc() is guaranteed to have natural
alignment (aligned to the size of the allocation). It is however not
guaranteed that pci_epc_set_bar() (and thus dw_pcie_prog_ep_inbound_atu())
is supplied an address that has natural alignment. (An EPF driver can send
in an arbitrary physical address to pci_epc_set_bar().)

The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields
in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that:
"Field size depends on log2(BAR_MASK+1) in BAR match mode."

I.e. only the upper bits are writable, and the number of writable bits is
dependent on the configured BAR_MASK.

Add a check to ensure that the physical address programmed in the iATU is
aligned to the size of the BAR (BAR_MASK+1), as without this, we can get
hard to debug errors, as we could write to bits that are read-only (without
getting a write error), which could cause the iATU to end up redirecting to
a physical address that is different from the address that we intended.

Link: https://lore.kernel.org/r/20241213143301.4158431-11-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-12-18 21:51:30 +00:00
Niklas Cassel
3708acbd5f
PCI: dwc: ep: Prevent changing BAR size/flags in pci_epc_set_bar()
In commit 4284c88fff ("PCI: designware-ep: Allow pci_epc_set_bar() update
inbound map address") set_bar() was modified to support dynamically
changing the backing physical address of a BAR that was already configured.

This means that set_bar() can be called twice, without ever calling
clear_bar() (as calling clear_bar() would clear the BAR's PCI address
assigned by the host).

This can only be done if the new BAR size/flags does not differ from the
existing BAR configuration. Add these missing checks.

If we allow set_bar() to set e.g. a new BAR size that differs from the
existing BAR size, the new address translation range will be smaller than
the BAR size already determined by the host, which would mean that a read
past the new BAR size would pass the iATU untranslated, which could allow
the host to read memory not belonging to the new struct pci_epf_bar.

While at it, add comments which clarifies the support for dynamically
changing the physical address of a BAR. (Which was also missing.)

Fixes: 4284c88fff ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address")
Link: https://lore.kernel.org/r/20241213143301.4158431-10-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
2024-12-18 21:51:19 +00:00
Niklas Cassel
33a6938e0c
PCI: dwc: ep: Write BAR_MASK before iATU registers in pci_epc_set_bar()
The "DesignWare Cores PCI Express Controller Register Descriptions,
Version 4.60a", section "1.21.70 IATU_LWR_TARGET_ADDR_OFF_INBOUND_i",
fields LWR_TARGET_RW and LWR_TARGET_HW both state that:
"Field size depends on log2(BAR_MASK+1) in BAR match mode."

I.e. only the upper bits are writable, and the number of writable bits is
dependent on the configured BAR_MASK.

If we do not write the BAR_MASK before writing the iATU registers, we are
relying the reset value of the BAR_MASK being larger than the requested
BAR size (which is supplied in the struct pci_epf_bar which is passed to
pci_epc_set_bar()). The reset value of the BAR_MASK is SoC dependent.

Thus, if the struct pci_epf_bar requests a BAR size that is larger than the
reset value of the BAR_MASK, the iATU will try to write to read-only bits,
which will cause the iATU to end up redirecting to a physical address that
is different from the address that was intended.

Thus, we should always write the iATU registers after writing the BAR_MASK.

Fixes: f8aed6ec62 ("PCI: dwc: designware: Add EP mode support")
Link: https://lore.kernel.org/r/20241213143301.4158431-9-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
2024-12-18 21:50:47 +00:00
Bjorn Helgaas
c60603ca1d Merge branch 'pci/controller/tegra194'
- Move endpoint controller cleanups that depend on refclk from the host to
  the notifier that tells us the host has deasserted PERST# (Manivannan
  Sadhasivam)

* pci/controller/tegra194:
  PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()
2024-11-25 13:41:00 -06:00
Bjorn Helgaas
f54ff407e6 Merge branch 'pci/controller/qcom'
- Enable MSI interrupts if 'global' IRQ is supported, since a previous
  commit unintentionally masked them (Manivannan Sadhasivam)

- Move endpoint controller cleanups that depend on refclk from the host to
  the notifier that tells us the host has deasserted PERST# (Manivannan
  Sadhasivam)

- Add DT binding and driver support for IPQ9574, with Synopsys IP v5.80a
  and Qcom IP 1.27.0 (devi priya)

- Move the OPP "operating-points-v2" table from the qcom,pcie-sm8450.yaml
  DT binding to qcom,pcie-common.yaml, where it can be used by other Qcom
  platforms (Qiang Yu)

- Add 'global' SPI interrupt for events like link-up, link-down to
  qcom,pcie-x1e80100 DT binding so we can start enumeration when the link
  comes up (Qiang Yu)

- Disable ASPM L0s for qcom,pcie-x1e80100 since the PHY is not tuned to
  support this (Qiang Yu)

- Add ops_1_21_0 for SC8280X family SoC, which doesn't use the 'iommu-map'
  DT property and doesn't need BDF-to-SID translation (Qiang Yu)

* pci/controller/qcom:
  PCI: qcom: Disable ASPM L0s for X1E80100
  PCI: qcom: Remove BDF2SID mapping config for SC8280X family SoC
  dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
  dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml
  PCI: qcom: Add support for IPQ9574
  dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller
  PCI: qcom-ep: Move controller cleanups to qcom_pcie_perst_deassert()
  PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported
2024-11-25 13:40:59 -06:00
Bjorn Helgaas
c1787c3e41 Merge branch 'pci/controller/keystone'
- Set the 'ti,keystone-pcie' mode so v3.65a devices work in Root Complex
  mode (Kishon Vijay Abraham I)

- Try to avoid unrecoverable SError for attempts to issue config
  transactions when the link is down; this is racy but the best we can do
  (Kishon Vijay Abraham I)

* pci/controller/keystone:
  PCI: keystone: Add link up check to ks_pcie_other_map_bus()
  PCI: keystone: Set mode as Root Complex for "ti,keystone-pcie" compatible
2024-11-25 13:40:58 -06:00
Bjorn Helgaas
7b86e0a589 Merge branch 'pci/controller/imx6'
- Fix suspend/resume support on i.MX6QDL, which has a hardware erratum that
  prevents use of L2 (Stefan Eichenberger)

* pci/controller/imx6:
  PCI: imx6: Fix suspend/resume support on i.MX6QDL
2024-11-25 13:40:57 -06:00
Bjorn Helgaas
2b4049d192 Merge branch 'pci/controller/dwc'
- Clear outbound address on unmap so dw_pcie_find_index() won't match an
  ATU index that was already unmapped (Damien Le Moal)

- Use of_property_present() instead of of_property_read_bool() when testing
  for presence of non-boolean DT properties (Rob Herring)

- Advertise 1MB size if endpoint supports Resizable BARs, which was
  inadvertently lost in v6.11 (Niklas Cassel)

* pci/controller/dwc:
  PCI: dwc: ep: Fix advertised resizable BAR size regression
  PCI: dwc: Use of_property_present() for non-boolean properties
  PCI: dwc: endpoint: Clear outbound address on unmap
2024-11-25 13:40:57 -06:00
Bjorn Helgaas
bd43348872 Merge branch 'pci/endpoint'
- Add pci_epc_function_is_valid() to avoid repeating common validation
  checks (Damien Le Moal)

- Skip attempts to allocate from endpoint controller memory window if the
  requested size is larger than the window (Damien Le Moal)

- Add and document pci_epc_mem_map() and pci_epc_mem_unmap() to handle
  controller-specific size and alignment constraints, and add test cases to
  the endpoint test driver (Damien Le Moal)

- Implement dwc pci_epc_ops.align_addr() so pci_epc_mem_map() can observe
  DWC-specific alignment requirements (Damien Le Moal)

- Synchronously cancel command handler work in endpoint test before
  cleaning up DMA and BARs (Damien Le Moal)

- Respect endpoint page size in dw_pcie_ep_align_addr() (Niklas Cassel)

- Use dw_pcie_ep_align_addr() in dw_pcie_ep_raise_msi_irq() and
  dw_pcie_ep_raise_msix_irq() instead of open coding the equivalent (Niklas
  Cassel)

- Remove superfluous 'return' from pci_epf_test_clean_dma_chan() (Wang
  Jiang)

- Avoid NULL dereference if Modem Host Interface Endpoint lacks 'mmio' DT
  property (Zhongqiu Han)

- Release PCI domain ID of Endpoint controller parent (not controller
  itself) and before unregistering the controller, to avoid use-after-free
  (Zijun Hu)

- Clear secondary (not primary) EPC in pci_epc_remove_epf() when removing
  the secondary controller associated with an NTB (Zijun Hu)

- Fix pci_epc_map map_size kerneldoc (Rick Wertenbroek)

* pci/endpoint:
  PCI: endpoint: Fix pci_epc_map map_size kerneldoc string
  PCI: endpoint: Clear secondary (not primary) EPC in pci_epc_remove_epf()
  PCI: endpoint: Fix PCI domain ID release in pci_epc_destroy()
  PCI: endpoint: epf-mhi: Avoid NULL dereference if DT lacks 'mmio'
  PCI: endpoint: Remove surplus return statement from pci_epf_test_clean_dma_chan()
  PCI: dwc: ep: Use align addr function for dw_pcie_ep_raise_{msi,msix}_irq()
  PCI: endpoint: test: Synchronously cancel command handler work
  PCI: dwc: endpoint: Implement the pci_epc_ops::align_addr() operation
  PCI: endpoint: test: Use pci_epc_mem_map/unmap()
  PCI: endpoint: Update documentation
  PCI: endpoint: Introduce pci_epc_mem_map()/unmap()
  PCI: endpoint: Improve pci_epc_mem_alloc_addr()
  PCI: endpoint: Introduce pci_epc_function_is_valid()
2024-11-25 13:40:56 -06:00
Niklas Cassel
118397c9ba
PCI: dwc: ep: Fix advertised resizable BAR size regression
The advertised resizable BAR size was fixed in commit 72e34b8593 ("PCI:
dwc: endpoint: Fix advertised resizable BAR size").

Commit 867ab111b2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown()
API to handle Link Down event") was included shortly after this, and
moved the code to another function. When the code was moved, this fix
was mistakenly lost.

According to the spec, it is illegal to not have a bit set in
PCI_REBAR_CAP, and 1 MB is the smallest size allowed.

So, set bit 4 in PCI_REBAR_CAP, so that we actually advertise support
for a 1 MB BAR size.

Fixes: 867ab111b2 ("PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event")
Link: https://lore.kernel.org/r/20241116005950.2480427-2-cassel@kernel.org
Link: https://lore.kernel.org/r/20240606-pci-deinit-v1-3-4395534520dc@linaro.org
Link: https://lore.kernel.org/r/20240307111520.3303774-1-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: stable@vger.kernel.org
2024-11-16 18:21:28 +00:00
Rob Herring (Arm)
154fc1f642
PCI: dwc: Use of_property_present() for non-boolean properties
The use of of_property_read_bool() for non-boolean properties is
deprecated in favor of of_property_present() when testing for property
presence.

Link: https://lore.kernel.org/r/20241104190714.275977-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-11-16 18:21:06 +00:00
Niklas Cassel
3fafc38b77
PCI: dwc: ep: Use align addr function for dw_pcie_ep_raise_{msi,msix}_irq()
Use the dw_pcie_ep_align_addr() function to calculate the alignment in
dw_pcie_ep_raise_{msi,msix}_irq() instead of open coding the same.

Link: https://lore.kernel.org/r/20241017132052.4014605-6-cassel@kernel.org
Link: https://lore.kernel.org/r/20241104205144.409236-2-cassel@kernel.org
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
[kwilczynski: squashed patch that fixes memory map sizes]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-11-16 18:20:01 +00:00
Kishon Vijay Abraham I
9e9ec8d869
PCI: keystone: Add link up check to ks_pcie_other_map_bus()
K2G forwards the error triggered by a link-down state (e.g., no connected
endpoint device) on the system bus for PCI configuration transactions;
these errors are reported as an SError at system level, which is fatal and
hangs the system.

So, apply fix similar to how it was done in the DesignWare Core driver
commit 15b2390634 ("PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()").

Fixes: 10a797c6e5 ("PCI: dwc: keystone: Use pci_ops for config space accessors")
Link: https://lore.kernel.org/r/20240524105714.191642-3-s-vadapalli@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log, added tag for stable releases]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: stable@vger.kernel.org
2024-11-07 15:37:24 +00:00
Kishon Vijay Abraham I
5a938ed948
PCI: keystone: Set mode as Root Complex for "ti,keystone-pcie" compatible
commit 23284ad677 ("PCI: keystone: Add support for PCIe EP in AM654x
Platforms") introduced configuring "enum dw_pcie_device_mode" as part of
device data ("struct ks_pcie_of_data"). However it failed to set the
mode for "ti,keystone-pcie" compatible.

Since the mode defaults to "DW_PCIE_UNKNOWN_TYPE", the following error
message is displayed for the v3.65a controller:

  "INVALID device type 0"

Despite the driver probing successfully, the controller may not be
functional in the Root Complex mode of operation.

So, set the mode as Root Complex for "ti,keystone-pcie" compatible to
fix this.

Fixes: 23284ad677 ("PCI: keystone: Add support for PCIe EP in AM654x Platforms")
Link: https://lore.kernel.org/r/20240524105714.191642-2-s-vadapalli@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log, added tag for stable releases]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: stable@vger.kernel.org
2024-11-07 15:35:17 +00:00
Stefan Eichenberger
0a726f542d
PCI: imx6: Fix suspend/resume support on i.MX6QDL
The suspend/resume functionality is currently broken on the i.MX6QDL
platform, as documented in the NXP errata (ERR005723):

  https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf

This patch addresses the issue by sharing most of the suspend/resume
sequences used by other i.MX devices, while avoiding modifications to
critical registers that disrupt the PCIe functionality. It targets the
same problem as the following downstream commit:

  4e92355e1f

Unlike the downstream commit, this patch also resets the connected PCIe
device if possible. Without this reset, certain drivers, such as ath10k
or iwlwifi, will crash on resume. The device reset is also done by the
driver on other i.MX platforms, making this patch consistent with
existing practices.

Upon resuming, the kernel will hang and display an error. Here's an
example of the error encountered with the ath10k driver:

  ath10k_pci 0000:01:00.0: Unable to change power state from D3hot to D0, device inaccessible
  Unhandled fault: imprecise external abort (0x1406) at 0x0106f944

Without this patch, suspend/resume will fail on i.MX6QDL devices if a
PCIe device is connected.

Link: https://lore.kernel.org/r/20241030103250.83640-1-eichest@gmail.com
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
[kwilczynski: commit log, added tag for stable releases]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Cc: stable@vger.kernel.org
2024-11-06 21:54:17 +00:00
Damien Le Moal
e73ea1c2d4
PCI: dwc: endpoint: Implement the pci_epc_ops::align_addr() operation
The function dw_pcie_prog_outbound_atu() used to program outbound ATU
entries for mapping RC PCI addresses to local CPU addresses does not
allow PCI addresses that are not aligned to the value of region_align
of struct dw_pcie. This value is determined from the iATU hardware
registers during probing of the iATU (done by dw_pcie_iatu_detect()).
This value is thus valid for all DWC PCIe controllers, and valid
regardless of the hardware configuration used when synthesizing the
DWC PCIe controller.

Implement the ->align_addr() endpoint controller operation to allow
this mapping alignment to be transparently handled by endpoint function
drivers through the function pci_epc_mem_map().

Link: https://lore.kernel.org/linux-pci/20241012113246.95634-7-dlemoal@kernel.org
Link: https://lore.kernel.org/linux-pci/20241015090712.112674-1-dlemoal@kernel.org
Link: https://lore.kernel.org/linux-pci/20241017132052.4014605-5-cassel@kernel.org
Co-developed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
[mani: squashed the patch that changed phy_addr_t to u64]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: squashed patch that updated the pci_size variable]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-11-04 21:29:44 +00:00
Qiang Yu
fba6045161
PCI: qcom: Disable ASPM L0s for X1E80100
Currently, the cfg_1_9_0 which is being used for X1E80100 doesn't disable
ASPM L0s. However, hardware team recommends to disable L0s as the PHY init
sequence is not tuned support L0s. Hence reuse cfg_sc8280xp for X1E80100.

Note that the config_sid() callback is not present in cfg_sc8280xp, don't
concern about this because config_sid() callback is originally a no-op
for X1E80100.

Fixes: 6d0c39324c ("PCI: qcom: Add X1E80100 PCIe support")
Link: https://lore.kernel.org/r/20241101030902.579789-5-quic_qianyu@quicinc.com
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <stable@vger.kernel.org> # 6.9
2024-11-04 14:57:30 +00:00
Qiang Yu
1362af92bc
PCI: qcom: Remove BDF2SID mapping config for SC8280X family SoC
The SC8280XP PCIe devicetree nodes do not specify an 'iommu-map' so
the config_sid() callback is effectively a no-op.

Hence introduce a new ops struct, namely ops_1_21_0 which is same as
ops_1_9_0 except that it doesn't have config_sid() callback to clean
it up.

Link: https://lore.kernel.org/r/20241101030902.579789-4-quic_qianyu@quicinc.com
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-11-04 14:55:57 +00:00
devi priya
a63b74f2e3
PCI: qcom: Add support for IPQ9574
Add the new IPQ9574 platform which is based on the Qcom IP rev. 1.27.0
and Synopsys IP rev. 5.80a.

The platform itself has four PCIe Gen3 controllers: two single-lane and
two dual-lane, all are based on Synopsys IP rev. 5.70a. As such, reuse
all the members of 'ops_2_9_0'.

Link: https://lore.kernel.org/r/20240801054803.3015572-5-quic_srichara@quicinc.com
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-11-03 20:11:44 +00:00
Manivannan Sadhasivam
40e2125381
PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()
Currently, the endpoint cleanup function dw_pcie_ep_cleanup() and EPF
deinit notify function pci_epc_deinit_notify() are called during the
execution of pex_ep_event_pex_rst_assert() i.e., when the host has asserted
PERST#. But quickly after this step, refclk will also be disabled by the
host.

All of the tegra194 endpoint SoCs supported as of now depend on the refclk
from the host for keeping the controller operational. Due to this
limitation, any access to the hardware registers in the absence of refclk
will result in a whole endpoint crash. Unfortunately, most of the
controller cleanups require accessing the hardware registers (like eDMA
cleanup performed in dw_pcie_ep_cleanup(), etc...). So these cleanup
functions can cause the crash in the endpoint SoC once host asserts PERST#.

One way to address this issue is by generating the refclk in the endpoint
itself and not depending on the host. But that is not always possible as
some of the endpoint designs do require the endpoint to consume refclk from
the host.

Thus, fix this crash by moving the controller cleanups to the start of
the pex_ep_event_pex_rst_deassert() function. This function is called
whenever the host has deasserted PERST# and it is guaranteed that the
refclk would be active at this point. So at the start of this function
(after enabling resources) the controller cleanup can be performed. Once
finished, rest of the code execution for PERST# deassert can continue as
usual.

Fixes: 473b2cf9c4 ("PCI: endpoint: Introduce 'epc_deinit' event and notify the EPF drivers")
Fixes: 570d7715ee ("PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST#")
Link: https://lore.kernel.org/r/20240817-pci-qcom-ep-cleanup-v1-2-d6b958226559@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Vidya Sagar <vidyas@nvidia.com>
Cc: linux-tegra@vger.kernel.org
2024-11-03 09:08:33 +00:00
Manivannan Sadhasivam
7d7cf89b11
PCI: qcom-ep: Move controller cleanups to qcom_pcie_perst_deassert()
Currently, the endpoint cleanup function dw_pcie_ep_cleanup() and EPF
deinit notify function pci_epc_deinit_notify() are called during the
execution of qcom_pcie_perst_assert() i.e., when the host has asserted
PERST#. But quickly after this step, refclk will also be disabled by the
host.

All of the Qcom endpoint SoCs supported as of now depend on the refclk from
the host for keeping the controller operational. Due to this limitation,
any access to the hardware registers in the absence of refclk will result
in a whole endpoint crash. Unfortunately, most of the controller cleanups
require accessing the hardware registers (like eDMA cleanup performed in
dw_pcie_ep_cleanup(), powering down MHI EPF etc...). So these cleanup
functions are currently causing the crash in the endpoint SoC once host
asserts PERST#.

One way to address this issue is by generating the refclk in the endpoint
itself and not depending on the host. But that is not always possible as
some of the endpoint designs do require the endpoint to consume refclk from
the host (as I was told by the Qcom engineers).

Thus, fix this crash by moving the controller cleanups to the start of
the qcom_pcie_perst_deassert() function. qcom_pcie_perst_deassert() is
called whenever the host has deasserted PERST# and it is guaranteed that
the refclk would be active at this point. So at the start of this function
(after enabling resources), the controller cleanup can be performed. Once
finished, rest of the code execution for PERST# deassert can continue as
usual.

Fixes: 473b2cf9c4 ("PCI: endpoint: Introduce 'epc_deinit' event and notify the EPF drivers")
Fixes: 570d7715ee ("PCI: dwc: ep: Introduce dw_pcie_ep_cleanup() API for drivers supporting PERST#")
Link: https://lore.kernel.org/r/20240817-pci-qcom-ep-cleanup-v1-1-d6b958226559@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-11-03 09:03:30 +00:00
Manivannan Sadhasivam
ba4a2e2317
PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported
Currently, if 'Global IRQ' is supported by the platform, only the Link up
interrupt is enabled in the PARF_INT_ALL_MASK register. This masks MSIs
on some platforms. The MSI bits in PARF_INT_ALL_MASK register are enabled
by default in the hardware, but commit 4581403f67 ("PCI: qcom: Enumerate
endpoints based on Link up event in 'global_irq' interrupt") disabled them
and enabled only the Link up interrupt. While MSI continued to work on the
SM8450 platform that was used to test the offending commit, on other
platforms like SM8250, X1E80100, MSIs are getting masked. And they require
enabling the MSI interrupt bits in the register to unmask (enable) the
MSIs.

Even though the MSI interrupt enable bits in PARF_INT_ALL_MASK are
described as 'diagnostic' interrupts in the internal documentation,
disabling them masks MSI on these platforms. Due to this, MSIs were not
reported to be received these platforms while supporting 'Global IRQ'.

So, enable the MSI interrupts along with the Link up interrupt in the
PARF_INT_ALL_MASK register if 'Global IRQ' is supported. This ensures that
the MSIs continue to work and also the driver is able to catch the Link
up interrupt for enumerating endpoint devices.

Fixes: 4581403f67 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt")
Closes: https://lore.kernel.org/linux-pci/9a692c98-eb0a-4d86-b642-ea655981ff53@kernel.org/
Link: https://lore.kernel.org/r/20241007051255.4378-1-manivannan.sadhasivam@linaro.org
Reported-by: Konrad Dybcio <konradybcio@kernel.org>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> # SL7
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Qiang Yu <quic_qianyu@quicinc.com>
2024-11-02 15:33:00 +00:00
Damien Le Moal
12dd12821f
PCI: dwc: endpoint: Clear outbound address on unmap
Clear the address mapped (outbound_addr array) in dw_pcie_ep_unmap_addr(),
to ensure that dw_pcie_find_index() does not match an ATU index that was
already unmapped.

This is in addition to clearing the ATU index bit in ob_window_map.

Link: https://lore.kernel.org/linux-pci/20241004141000.5080-1-dlemoal@kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-10-27 19:43:44 +00:00
Sergio Paracuellos
3c87b3c85a PCI: controller: Switch back to struct platform_driver::remove()
After commit 0edb555a65 ("platform: Make platform_driver::remove() return
void") .remove() is (again) the right callback to implement for platform
drivers.

Convert all PCI controller drivers to use .remove(), with the eventual goal
to drop struct platform_driver::remove_new(). As .remove() and .remove_new()
have the same prototypes, conversion is done by just changing the structure
member name in the driver initializer.

Link: https://lore.kernel.org/r/20240923065706.728769-1-sergio.paracuellos@gmail.com
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
[bhelgaas: add pcie-xilinx-nwl.c and tidy whitespace per Uwe Kleine-König:
https://lore.kernel.org/r/tdxrmmqyzcufupnwkdbg7lwgadizm7v3lxjirykijbml7x54ze@upbdzycdsilm]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-10-03 16:44:49 -05:00
Linus Torvalds
3a37872316 pci-v6.12-changes
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Merge tag 'pci-v6.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Wait for device readiness after reset by polling Vendor ID and
     looking for Configuration RRS instead of polling the Command
     register and looking for non-error completions, to avoid hardware
     retries done for RRS on non-Vendor ID reads (Bjorn Helgaas)

   - Rename CRS Completion Status to RRS ('Request Retry Status') to
     match PCIe r6.0 spec usage (Bjorn Helgaas)

   - Clear LBMS bit after a manual link retrain so we don't try to
     retrain a link when there's no downstream device anymore (Maciej W.
     Rozycki)

   - Revert to the original link speed after retraining fails instead of
     leaving it restricted to 2.5GT/s, so a future device has a chance
     to use higher speeds (Maciej W. Rozycki)

   - Wait for each level of downstream bus, not just the first, to
     become accessible before restoring devices on that bus (Ilpo
     Järvinen)

   - Add ARCH_PCI_DEV_GROUPS so s390 can add its own attribute_groups
     without having to stomp on the core's pdev->dev.groups (Lukas
     Wunner)

  Driver binding:

   - Export pcim_request_region(), a managed counterpart of
     pci_request_region(), for use by drivers (Philipp Stanner)

   - Export pcim_iomap_region() and deprecate pcim_iomap_regions()
     (Philipp Stanner)

   - Request the PCI BAR used by xboxvideo (Philipp Stanner)

   - Request and map drm/ast BARs with pcim_iomap_region() (Philipp
     Stanner)

  MSI:

   - Add MSI_FLAG_NO_AFFINITY flag for devices that mux MSIs onto a
     single IRQ line and cannot set the affinity of each MSI to a
     specific CPU core (Marek Vasut)

   - Use MSI_FLAG_NO_AFFINITY and remove unnecessary .irq_set_affinity()
     implementations in aardvark, altera, brcmstb, dwc, mediatek-gen3,
     mediatek, mobiveil, plda, rcar, tegra, vmd, xilinx-nwl,
     xilinx-xdma, and xilinx drivers to avoid 'IRQ: set affinity failed'
     warnings (Marek Vasut)

  Power management:

   - Add pwrctl support for ATH11K inside the WCN6855 package (Konrad
     Dybcio)

  PCI device hotplug:

   - Remove unnecessary hpc_ops struct from shpchp (ngn)

   - Check for PCI_POSSIBLE_ERROR(), not 0xffffffff, in cpqphp
     (weiyufeng)

  Virtualization:

   - Mark Creative Labs EMU20k2 INTx masking as broken (Alex Williamson)

   - Add an ACS quirk for Qualcomm SA8775P, which doesn't advertise ACS
     but does provide ACS-like features (Subramanian Ananthanarayanan)

  IOMMU:

   - Add function 0 DMA alias quirk for Glenfly Arise audio function,
     which uses the function 0 Requester ID (WangYuli)

  NPEM:

   - Add Native PCIe Enclosure Management (NPEM) support for sysfs
     control of NVMe RAID storage indicators (ok/fail/locate/
     rebuild/etc) (Mariusz Tkaczyk)

   - Add support for the ACPI _DSM PCIe SSD status LED management, which
     is functionally similar to NPEM but mediated by platform firmware
     (Mariusz Tkaczyk)

  Device trees:

   - Drop minItems and maxItems from ranges in PCI generic host binding
     since host bridges may have several MMIO and I/O port apertures
     (Frank Li)

   - Add kirin, rcar-gen2, uniphier DT binding top-level constraints for
     clocks (Krzysztof Kozlowski)

  Altera PCIe controller driver:

   - Convert altera DT bindings from text to YAML (Matthew Gerlach)

   - Replace TLP_REQ_ID() with macro PCI_DEVID(), which does the same
     thing and is what other drivers use (Jinjie Ruan)

  Broadcom STB PCIe controller driver:

   - Add DT binding maxItems for reset controllers (Jim Quinlan)

   - Use the 'bridge' reset method if described in the DT (Jim Quinlan)

   - Use the 'swinit' reset method if described in the DT (Jim Quinlan)

   - Add 'has_phy' so the existence of a 'rescal' reset controller
     doesn't imply software control of it (Jim Quinlan)

   - Add support for many inbound DMA windows (Jim Quinlan)

   - Rename SoC 'type' to 'soc_base' express the fact that SoCs come in
     families of multiple similar devices (Jim Quinlan)

   - Add Broadcom 7712 DT description and driver support (Jim Quinlan)

   - Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings for
     maintainability (Bjorn Helgaas)

  Freescale i.MX6 PCIe controller driver:

   - Add imx6q-pcie 'dbi2' and 'atu' reg-names for i.MX8M Endpoints
     (Richard Zhu)

   - Fix a code restructuring error that caused i.MX8MM and i.MX8MP
     Endpoints to fail to establish link (Richard Zhu)

   - Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing
     outbound alignment requirement (Richard Zhu)

   - Call phy_power_off() in the .probe() error path (Frank Li)

   - Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also
     supported (Frank Li)

   - Manage Refclk by using SoC-specific callbacks instead of switch
     statements (Frank Li)

   - Manage core reset by using SoC-specific callbacks instead of switch
     statements (Frank Li)

   - Expand comments for erratum ERR010728 workaround (Frank Li)

   - Use generic PHY APIs to configure mode, speed, and submode, which
     is harmless for devices that implement their own internal PHY
     management and don't set the generic imx_pcie->phy (Frank Li)

   - Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver
     Root Complex support (Richard Zhu)

  Freescale Layerscape PCIe controller driver:

   - Replace layerscape-pcie DT binding compatible fsl,lx2160a-pcie with
     fsl,lx2160ar2-pcie (Frank Li)

   - Add layerscape-pcie DT binding deprecated 'num-viewport' property
     to address a DT checker warning (Frank Li)

   - Change layerscape-pcie DT binding 'fsl,pcie-scfg' to phandle-array
     (Frank Li)

  Loongson PCIe controller driver:

   - Increase max PCI hosts to 8 for Loongson-3C6000 and newer chipsets
     (Huacai Chen)

  Marvell Aardvark PCIe controller driver:

   - Fix issue with emulating Configuration RRS for two-byte reads of
     Vendor ID; previously it only worked for four-byte reads (Bjorn
     Helgaas)

  MediaTek PCIe Gen3 controller driver:

   - Add per-SoC struct mtk_gen3_pcie_pdata to support multiple SoC
     types (Lorenzo Bianconi)

   - Use reset_bulk APIs to manage PHY reset lines (Lorenzo Bianconi)

   - Add DT and driver support for Airoha EN7581 PCIe controller
     (Lorenzo Bianconi)

  Qualcomm PCIe controller driver:

   - Update qcom,pcie-sc7280 DT binding with eight interrupts (Rayyan
     Ansari)

   - Add back DT 'vddpe-3v3-supply', which was incorrectly removed
     earlier (Johan Hovold)

   - Drop endpoint redundant masking of global IRQ events (Manivannan
     Sadhasivam)

   - Clarify unknown global IRQ message and only log it once to avoid a
     flood (Manivannan Sadhasivam)

   - Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
     Sadhasivam)

   - Assign PCI domain number for endpoint controllers (Manivannan
     Sadhasivam)

   - Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for
     endpoint controller (Manivannan Sadhasivam)

   - Add global SPI interrupt for PCIe link events to DT binding
     (Manivannan Sadhasivam)

   - Add global RC interrupt handler to handle 'Link up' events and
     automatically enumerate hot-added devices (Manivannan Sadhasivam)

   - Avoid mirroring of DBI and iATU register space so it doesn't
     overlap BAR MMIO space (Prudhvi Yarlagadda)

   - Enable controller resources like PHY only after PERST# is
     deasserted to partially avoid the problem that the endpoint SoC
     crashes when accessing things when Refclk is absent (Manivannan
     Sadhasivam)

   - Add 16.0 GT/s equalization and RX lane margining settings (Shashank
     Babu Chinta Venkata)

   - Pass domain number to pci_bus_release_domain_nr() explicitly to
     avoid a NULL pointer dereference (Manivannan Sadhasivam)

  Renesas R-Car PCIe controller driver:

   - Make the read-only const array 'check_addr' static (Colin Ian King)

   - Add R-Car V4M (R8A779H0) PCIe host and endpoint to DT binding
     (Yoshihiro Shimoda)

  TI DRA7xx PCIe controller driver:

   - Request IRQF_ONESHOT for 'dra7xx-pcie-main' IRQ since the primary
     handler is NULL (Siddharth Vadapalli)

   - Handle IRQ request errors during root port and endpoint probe
     (Siddharth Vadapalli)

  TI J721E PCIe driver:

   - Add DT 'ti,syscon-acspcie-proxy-ctrl' and driver support to enable
     the ACSPCIE module to drive Refclk for the Endpoint (Siddharth
     Vadapalli)

   - Extract the cadence link setup from cdns_pcie_host_setup() so link
     setup can be done separately during resume (Thomas Richard)

   - Add T_PERST_CLK_US definition for the mandatory delay between
     Refclk becoming stable and PERST# being deasserted (Thomas Richard)

   - Add j721e suspend and resume support (Théo Lebrun)

  TI Keystone PCIe controller driver:

   - Fix NULL pointer checking when applying MRRS limitation quirk for
     AM65x SR 1.0 Errata #i2037 (Dan Carpenter)

  Xilinx NWL PCIe controller driver:

   - Fix off-by-one error in INTx IRQ handler that caused INTx
     interrupts to be lost or delivered as the wrong interrupt (Sean
     Anderson)

   - Rate-limit misc interrupt messages (Sean Anderson)

   - Turn off the clock on probe failure and device removal (Sean
     Anderson)

   - Add DT binding and driver support for enabling/disabling PHYs (Sean
     Anderson)

   - Add PCIe phy bindings for the ZCU102 (Sean Anderson)

  Xilinx XDMA PCIe controller driver:

   - Add support for Xilinx QDMA Soft IP PCIe Root Port Bridge to DT
     binding and xilinx-dma-pl driver (Thippeswamy Havalige)

  Miscellaneous:

   - Fix buffer overflow in kirin_pcie_parse_port() (Alexandra Diupina)

   - Fix minor kerneldoc issues and typos (Bjorn Helgaas)

   - Use PCI_DEVID() macro in aer_inject() instead of open-coding it
     (Jinjie Ruan)

   - Check pcie_find_root_port() return in x86 fixups to avoid NULL
     pointer dereferences (Samasth Norway Ananda)

   - Make pci_bus_type constant (Kunwu Chan)

   - Remove unused declarations of __pci_pme_wakeup() and
     pci_vpd_release() (Yue Haibing)

   - Remove any leftover .*.cmd files with make clean (zhang jiao)

   - Remove unused BILLION macro (zhang jiao)"

* tag 'pci-v6.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (132 commits)
  PCI: Fix typos
  dt-bindings: PCI: qcom: Allow 'vddpe-3v3-supply' again
  tools: PCI: Remove unused BILLION macro
  tools: PCI: Remove .*.cmd files with make clean
  PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
  PCI: dra7xx: Fix error handling when IRQ request fails in probe
  PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
  PCI: qcom: Add RX lane margining settings for 16.0 GT/s
  PCI: qcom: Add equalization settings for 16.0 GT/s
  PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
  PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
  PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
  PCI: Mark Creative Labs EMU20k2 INTx masking as broken
  dt-bindings: PCI: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint
  dt-bindings: PCI: altera: msi: Convert to YAML
  PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
  PCI: Rename CRS Completion Status to RRS
  PCI: aardvark: Correct Configuration RRS checking
  PCI: Wait for device readiness with Configuration RRS
  PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings
  ...
2024-09-23 12:47:06 -07:00
Bjorn Helgaas
187b811570 Merge branch 'pci/controller/rcar-gen4'
- Make the read-only const array 'check_addr' static (Colin Ian King)

- Add R-Car V4M (R8A779H0) PCIe host and endpoint to DT binding (Yoshihiro
  Shimoda)

* pci/controller/rcar-gen4:
  dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4M compatible
  dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4M compatible
  PCI: rcar-gen4: Make read-only const array check_addr static
2024-09-19 14:25:33 -05:00
Bjorn Helgaas
45e981b86d Merge branch 'pci/controller/qcom'
- Drop endpoint redundant masking of global IRQ events (Manivannan
  Sadhasivam)

- Clarify unknown global IRQ message and only log it once to avoid a flood
  (Manivannan Sadhasivam)

- Add Manivannan Sadhasivam as maintainer of qcom endpoint driver
  (Manivannan Sadhasivam)

- Add 'linux,pci-domain' property to endpoint DT binding (Manivannan
  Sadhasivam)

- Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam)

- Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint
  controller (Manivannan Sadhasivam)

- Add global SPI interrupt for PCIe link events to DT binding (Manivannan
  Sadhasivam)

- Add global RC interrupt handler to handle 'Link up' events and
  automatically enumerate hot-added devices (Manivannan Sadhasivam)

- Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR
  MMIO space (Prudhvi Yarlagadda)

- Enable controller resources like PHY only after PERST# is deasserted to
  partially avoid the problem that the endpoint SoC crashes when accessing
  things when Refclk is absent (Manivannan Sadhasivam)

- Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan
  Sadhasivam)

- Cache maximum link speed value in dw_pcie.max_link_speed for use by
  vendor drivers (Manivannan Sadhasivam)

- Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu
  Chinta Venkata)

- Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a
  NULL pointer dereference (Manivannan Sadhasivam)

* pci/controller/qcom:
  PCI: Pass domain number to pci_bus_release_domain_nr() explicitly
  PCI: qcom: Add RX lane margining settings for 16.0 GT/s
  PCI: qcom: Add equalization settings for 16.0 GT/s
  PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
  PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
  PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
  PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
  PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
  dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt
  PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
  PCI: endpoint: Assign PCI domain number for endpoint controllers
  dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property
  dt-bindings: PCI: pci-ep: Update Maintainers
  PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
  PCI: qcom-ep: Drop the redundant masking of global IRQ events
2024-09-19 14:25:32 -05:00
Bjorn Helgaas
af64919440 Merge branch 'pci/controller/kirin'
- Fix potential buffer overflow in kirin_pcie_parse_port() (Alexandra
  Diupina)

* pci/controller/kirin:
  PCI: kirin: Fix buffer overflow in kirin_pcie_parse_port()
2024-09-19 14:25:31 -05:00
Bjorn Helgaas
e5f8d1c75b Merge branch 'pci/controller/keystone'
- Fix NULL pointer checking when applying MRRS limitation quirk for AM65x
  SR 1.0 Errata #i2037 (Dan Carpenter)

* pci/controller/keystone:
  PCI: keystone: Fix if-statement expression in ks_pcie_quirk()
2024-09-19 14:25:31 -05:00
Bjorn Helgaas
f8ca62bff2 Merge branch 'pci/controller/imx6'
- Fix a code restructuring error that caused i.MX8MM and i.MX8MP Endpoints
  to fail to establish link (Richard Zhu)

- Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing
  outbound alignment requirement (Richard Zhu)

- Call phy_power_off() in the .probe() error path (Frank Li)

- Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also
  supported (Frank Li)

- Manage Refclk by using SoC-specific callbacks instead of switch
  statements (Frank Li)

- Manage core reset by using SoC-specific callbacks instead of switch
  statements (Frank Li)

- Expand comments for erratum ERR010728 workaround (Frank Li)

- Use generic PHY APIs to configure mode, speed, and submode, which is
  harmless for devices that implement their own internal PHY management and
  don't set the generic imx_pcie->phy (Frank Li)

- Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver Root
  Complex support (Richard Zhu)

* pci/controller/imx6:
  PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
  PCI: imx6: Call common PHY API to set mode, speed, and submode
  dt-bindings: PCI: imx6q-pcie: Add i.MX8Q PCIe compatible string
  PCI: imx6: Consolidate redundant if-checks
  PCI: imx6: Improve comment for workaround ERR010728
  PCI: imx6: Simplify switch-case logic by involve core_reset callback
  PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
  PCI: imx6: Rename imx6_* with imx_*
  PCI: imx6: Fix missing call to phy_power_off() in error handling
  PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
  PCI: imx6: Fix establish link failure in EP mode for i.MX8MM and i.MX8MP
2024-09-19 14:25:30 -05:00
Bjorn Helgaas
5ec58799e8 Merge branch 'pci/controller/dra7xx'
- Request IRQF_ONESHOT for 'dra7xx-pcie-main' IRQ since the primary handler
  is NULL (Siddharth Vadapalli)

- Handle IRQ request errors during root port and endpoint probe (Siddharth
  Vadapalli)

* pci/controller/dra7xx:
  PCI: dra7xx: Fix error handling when IRQ request fails in probe
  PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
2024-09-19 14:25:30 -05:00
Bjorn Helgaas
f045bc60d5 Merge branch 'pci/controller/affinity'
- Add MSI_FLAG_NO_AFFINITY flag for devices that mux MSIs onto a single IRQ
  line and cannot set the affinity of each MSI to a specific CPU core
  (Marek Vasut)

- Use MSI_FLAG_NO_AFFINITY and remove unnecessary .irq_set_affinity()
  implementations in aardvark, altera, brcmstb, dwc, mediatek-gen3,
  mediatek, mobiveil, plda, rcar, tegra, vmd, xilinx-nwl, xilinx-xdma, and
  xilinx drivers to avoid "IRQ: set affinity failed" warnings (Marek Vasut)

* pci/controller/affinity:
  PCI: xilinx: Silence 'set affinity failed' warning
  PCI: xilinx-xdma: Silence 'set affinity failed' warning
  PCI: xilinx-nwl: Silence 'set affinity failed' warning
  PCI: vmd: Silence 'set affinity failed' warning
  PCI: tegra: Silence 'set affinity failed' warning
  PCI: rcar-host: Silence 'set affinity failed' warning
  PCI: plda: Silence 'set affinity failed' warning
  PCI: mobiveil: Silence 'set affinity failed' warning
  PCI: mediatek: Silence 'set affinity failed' warning
  PCI: mediatek-gen3: Silence 'set affinity failed' warning
  PCI: dwc: Silence 'set affinity failed' warning
  PCI: brcmstb: Silence 'set affinity failed' warning
  PCI: altera-msi: Silence 'set affinity failed' warning
  PCI: aardvark: Silence 'set affinity failed' warning
  genirq/msi: Silence 'set affinity failed' warning
2024-09-19 14:25:28 -05:00
Siddharth Vadapalli
4d60f6d4b8
PCI: dra7xx: Fix error handling when IRQ request fails in probe
Commit d4c7d1a089 ("PCI: dwc: dra7xx: Push request_irq()
call to the bottom of probe") moved the IRQ request for
"dra7xx-pcie-main" towards the end of dra7xx_pcie_probe().

However, the error handling does not take into account the
initialization performed by either dra7xx_add_pcie_port() or
dra7xx_add_pcie_ep(), depending on the mode of operation.

Fix the error handling to address this.

Fixes: d4c7d1a089 ("PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe")
Link: https://lore.kernel.org/linux-pci/20240827122422.985547-3-s-vadapalli@ti.com
Tested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
2024-09-13 21:36:11 +00:00
Siddharth Vadapalli
03f84b3bab
PCI: dra7xx: Fix threaded IRQ request for "dra7xx-pcie-main" IRQ
Commit da87d35a6e ("PCI: dra7xx: Use threaded IRQ handler for
"dra7xx-pcie-main" IRQ") switched from devm_request_irq() to
devm_request_threaded_irq() for the "dra7xx-pcie-main" interrupt.

Since the primary handler was set to NULL, the "IRQF_ONESHOT" flag
should have also been set. Fix this.

Fixes: da87d35a6e ("PCI: dra7xx: Use threaded IRQ handler for "dra7xx-pcie-main" IRQ")
Suggested-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/linux-pci/20240827122422.985547-2-s-vadapalli@ti.com
Reported-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org
2024-09-13 21:34:38 +00:00
Shashank Babu Chinta Venkata
d14bc28af3
PCI: qcom: Add RX lane margining settings for 16.0 GT/s
Add RX lane margining settings for 16.0 GT/s (GEN 4) data rate.

These settings improve link stability while operating at high date
rates and helps to improve signal quality.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-4-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-13 14:44:59 +00:00
Shashank Babu Chinta Venkata
d45736b598
PCI: qcom: Add equalization settings for 16.0 GT/s
During high data transmission rates such as 16.0 GT/s, there is an
increased risk of signal loss due to poor channel quality and
interference. This can impact receiver's ability to capture signals
accurately.

Hence, as signal compensation is achieved through appropriate lane
equalization, apply lane equalization settings at both transmitter
and receiver which results in an increase in the PCIe signal strength.

While at it, modify the pcie-tegra194 driver to make use of the
common GEN3_EQ_CONTROL_OFF definitions in pcie-designware.h.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-3-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
[mani: dropped the code refactoring and minor changes]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-13 14:44:57 +00:00
Manivannan Sadhasivam
19a69cbd9d
PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed
Currently, the dw_pcie::max_link_speed has a valid value only if the
controller driver restricts the maximum link speed in the driver or if
the platform does so in the devicetree using the 'max-link-speed'
property.

But having the maximum supported link speed of the platform would be
helpful for the vendor drivers to configure any link specific settings.

So in the case of non-valid value in dw_pcie::max_link_speed, just cache
the hardware default value from Link Capability register.

While at it, remove the 'max_link_speed' argument to the
dw_pcie_link_set_max_speed() function since the value can be
retrieved within the function.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-2-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
2024-09-13 14:44:55 +00:00
Manivannan Sadhasivam
2cebf68a24
PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed'
The 'link_gen' field is now holding the maximum supported link speed set
either by the controller driver or by DT through 'max-link-speed'
property.

However, the name 'link_gen' sounds like the negotiated link speed of
the PCIe link.

So rename it to 'max_link_speed' to make it clear that it holds the
maximum supported link speed of the controller.

Link: https://lore.kernel.org/linux-pci/20240911-pci-qcom-gen4-stability-v7-1-743f5c1fd027@linaro.org
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
2024-09-13 14:44:43 +00:00
Manivannan Sadhasivam
d3745e3ae6
PCI: qcom-ep: Enable controller resources like PHY only after refclk is available
qcom_pcie_enable_resources() is called by qcom_pcie_ep_probe() and it
enables the controller resources like clocks, regulator, PHY. On one of the
new unreleased Qcom SoC, PHY enablement depends on the active refclk. And
on all of the supported Qcom endpoint SoCs, refclk comes from the host
(RC). So calling qcom_pcie_enable_resources() without refclk causes the
NoC (Network On Chip) error in the endpoint SoC and in turn results in a
whole SoC crash and rebooting into EDL (Emergency Download) mode which is
an unrecoverable state.

But qcom_pcie_enable_resources() is already called by
qcom_pcie_perst_deassert() when PERST# is deasserted, and refclk is
available at that time.

Hence, remove the unnecessary call to qcom_pcie_enable_resources() from
qcom_pcie_ep_probe() to prevent the above mentioned crash.

It should be noted that this commit prevents the crash only under normal
working condition (booting endpoint before host), but the crash may also
occur if PERST# assert happens at the wrong time. For avoiding the crash
completely, it is recommended to use SRIS mode which allows the endpoint
SoC to generate its own refclk. The driver is not supporting SRIS mode
currently, but will be added in the future.

Fixes: 869bc52534 ("PCI: dwc: ep: Fix DBI access failure for drivers requiring refclk from host")
Link: https://lore.kernel.org/linux-pci/20240830082319.51387-1-manivannan.sadhasivam@linaro.org
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
2024-09-13 14:21:25 +00:00
Richard Zhu
c2699778e6 PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support
Implement i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe Root Complex
(RC) support. While the controller resembles that of i.MX8MP, the PHY
differs significantly. Also, there's a distinction between PCI bus
addresses and CPU addresses.

Introduce IMX_PCIE_FLAG_CPU_ADDR_FIXUP in drvdata::flags to indicate driver
need the cpu_addr_fixup() callback to facilitate CPU address to PCI bus
address conversion according to "ranges" property.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-11-b68ee5ef2b4d@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: check resource_list_first_type() for NULL]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-11 09:04:18 -05:00
Bjorn Helgaas
87f10faf16 PCI: Rename CRS Completion Status to RRS
PCIe r6.0 changed the abbreviation for "Configuration Request Retry Status"
Completion Status from "CRS" to "RRS" and uses the terminology of
"Configuration RRS Software Visibility" instead of "CRS Software
Visibility".

Align the Linux usage with the r6.0 spec language.  No functional change
intended.

It's confusing to make this change, but I think "RRS" *is* a better
abbreviation because it was easy to interpret "CRS" as "Completion Retry
Status", which really didn't make any sense.

Link: https://lore.kernel.org/r/20240827234848.4429-4-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-09-10 19:52:30 -05:00
Frank Li
8026f2d8e8
PCI: imx6: Call common PHY API to set mode, speed, and submode
Invoke the common PHY API to configure mode, speed, and submode. While
these functions are optional in the PHY interface, they are necessary for
certain PHY drivers. Lack of support for these functions in a PHY driver
does not cause harm.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-10-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-09 14:08:22 +00:00
Frank Li
eea9ecebe2
PCI: imx6: Consolidate redundant if-checks
Consolidated redundant if-checks pertaining to imx_pcie->phy. Instead of
two separate checks, merged them into one to improve code readability.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-8-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-09 14:08:22 +00:00
Frank Li
52ac41b5cd
PCI: imx6: Improve comment for workaround ERR010728
Improve comment about workaround ERR010728 by using official errata
document content, see:

  https://www.nxp.com/webapp/Download?colCode=IMX7DS_2N09P

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-7-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-09 14:08:22 +00:00
Frank Li
5223084d13
PCI: imx6: Simplify switch-case logic by involve core_reset callback
Instead of using the switch case statement to assert/dassert the core
reset handled by this driver itself, let's introduce a new callback
core_reset() and define it for platforms that require it.

This simplifies the code.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-5-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-09 14:08:22 +00:00
Frank Li
256867b746
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
Instead of using the switch case statement to enable/disable the
reference clock handled by this driver itself, let's introduce a new
callback enable_ref_clk() and define it for platforms that require it.

This simplifies the code.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-5-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-09 14:08:22 +00:00
Frank Li
d657ea28d5
PCI: imx6: Rename imx6_* with imx_*
Since this driver has evolved to support other i.MX SoCs such as
i.MX7/8/9, thus rename the 'imx6' prefix to 'imx' to avoid confusion.

The driver name is left unchanged to avoid breaking userspace.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-3-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log, refactor the IMX_* macros]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-09-09 14:08:21 +00:00
Frank Li
5b04d44d5c
PCI: imx6: Fix missing call to phy_power_off() in error handling
Fix missing call to phy_power_off() in the error path of
imx6_pcie_host_init(). Remove unnecessary check for imx6_pcie->phy
as the PHY API already handles NULL pointers.

Fixes: cbcf8722b5 ("phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()")
Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-3-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <stable@vger.kernel.org> # 6.1+
2024-09-09 14:08:19 +00:00
Richard Zhu
5cb3aa92c7
PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
Correct occasional MSI triggering failures in i.MX8MP PCIe EP by applying
the correct hardware outbound alignment requirement.

The i.MX platform has a restriction about outbound address translation. The
pci-epc-mem uses page_size to manage it. Set the correct page_size for i.MX
platform to meet the hardware requirement, which is the same as inbound
address alignment.

Thus, align it with epc_features::align.

Fixes: 1bd0d43dcf ("PCI: imx6: Clean up addr_space retrieval code")
Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-2-b68ee5ef2b4d@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Cc: <stable@vger.kernel.org> # 6.9+
2024-09-09 14:08:15 +00:00
Richard Zhu
5214ff221a
PCI: imx6: Fix establish link failure in EP mode for i.MX8MM and i.MX8MP
Add IMX6_PCIE_FLAG_HAS_APP_RESET flag to IMX8MM_EP and IMX8MP_EP drvdata.

This flag was overlooked during code restructuring. It is crucial to
release the app-reset from the System Reset Controller before initiating
LTSSM to rectify the issue.

Fixes: 0c9651c21f ("PCI: imx6: Simplify reset handling by using *_FLAG_HAS_*_RESET")
Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-1-b68ee5ef2b4d@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: <stable@vger.kernel.org> # 6.9+
2024-09-09 14:08:12 +00:00
Alexandra Diupina
c500a86693
PCI: kirin: Fix buffer overflow in kirin_pcie_parse_port()
Within kirin_pcie_parse_port(), the pcie->num_slots is compared to
pcie->gpio_id_reset size (MAX_PCI_SLOTS) which is correct and would lead
to an overflow.

Thus, fix condition to pcie->num_slots + 1 >= MAX_PCI_SLOTS and move
pcie->num_slots increment below the if-statement to avoid out-of-bounds
array access.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: b22dbbb245 ("PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge")
Link: https://lore.kernel.org/linux-pci/20240903115823.30647-1-adiupina@astralinux.ru
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2024-09-06 06:36:29 +00:00
Colin Ian King
5603a3491b
PCI: rcar-gen4: Make read-only const array check_addr static
Don't populate the const read-only array check_addr on the stack at
run time, instead make it static.

Link: https://lore.kernel.org/linux-pci/20240822205941.643187-1-colin.i.king@gmail.com
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
[kwilczynski: refactor array definition]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-01 17:31:04 +00:00
Prudhvi Yarlagadda
10ba0854c5
PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region
PARF hardware block which is a wrapper on top of DWC PCIe controller
mirrors the DBI and ATU register space. It uses PARF_SLV_ADDR_SPACE_SIZE
register to get the size of the memory block to be mirrored and uses
PARF_DBI_BASE_ADDR, PARF_ATU_BASE_ADDR registers to determine the base
address of DBI and ATU space inside the memory block that is being
mirrored.

When a memory region which is located above the SLV_ADDR_SPACE_SIZE
boundary is used for BAR region then there could be an overlap of DBI and
ATU address space that is getting mirrored and the BAR region. This
results in DBI and ATU address space contents getting updated when a PCIe
function driver tries updating the BAR/MMIO memory region. Reference
memory map of the PCIe memory region with DBI and ATU address space
overlapping BAR region is as below.

                        |---------------|
                        |               |
                        |               |
        ------- --------|---------------|
           |       |    |---------------|
           |       |    |       DBI     |
           |       |    |---------------|---->DBI_BASE_ADDR
           |       |    |               |
           |       |    |               |
           |    PCIe    |               |---->2*SLV_ADDR_SPACE_SIZE
           |    BAR/MMIO|---------------|
           |    Region  |       ATU     |
           |       |    |---------------|---->ATU_BASE_ADDR
           |       |    |               |
        PCIe       |    |---------------|
        Memory     |    |       DBI     |
        Region     |    |---------------|---->DBI_BASE_ADDR
           |       |    |               |
           |    --------|               |
           |            |               |---->SLV_ADDR_SPACE_SIZE
           |            |---------------|
           |            |       ATU     |
           |            |---------------|---->ATU_BASE_ADDR
           |            |               |
           |            |---------------|
           |            |       DBI     |
           |            |---------------|---->DBI_BASE_ADDR
           |            |               |
           |            |               |
        ----------------|---------------|
                        |               |
                        |               |
                        |               |
                        |---------------|

Currently memory region beyond the SLV_ADDR_SPACE_SIZE boundary is not
used for BAR region which is why the above mentioned issue is not
encountered. This issue is discovered as part of internal testing when we
tried moving the BAR region beyond the SLV_ADDR_SPACE_SIZE boundary. Hence
we are trying to fix this.

As PARF hardware block mirrors DBI and ATU register space after every
PARF_SLV_ADDR_SPACE_SIZE (default 0x1000000) boundary multiple, program
maximum possible size to this register by writing 0x80000000 to it(it
considers only powers of 2 as values) to avoid mirroring DBI and ATU to
BAR/MMIO region. Write the physical base address of DBI and ATU register
blocks to PARF_DBI_BASE_ADDR (default 0x0) and PARF_ATU_BASE_ADDR (default
0x1000) respectively to make sure DBI and ATU blocks are at expected
memory locations.

The register offsets PARF_DBI_BASE_ADDR_V2, PARF_SLV_ADDR_SPACE_SIZE_V2
and PARF_ATU_BASE_ADDR are applicable for platforms that use Qcom IP
rev 1.9.0, 2.7.0 and 2.9.0. PARF_DBI_BASE_ADDR_V2 and
PARF_SLV_ADDR_SPACE_SIZE_V2 are applicable for Qcom IP rev 2.3.3.
PARF_DBI_BASE_ADDR and PARF_SLV_ADDR_SPACE_SIZE are applicable for Qcom
IP rev 1.0.0, 2.3.2 and 2.4.0. Update init()/post_init() functions of the
respective Qcom IP versions to program applicable PARF_DBI_BASE_ADDR,
PARF_SLV_ADDR_SPACE_SIZE and PARF_ATU_BASE_ADDR register offsets. Update
the SLV_ADDR_SPACE_SZ macro to 0x80000000 to set highest bit in
PARF_SLV_ADDR_SPACE_SIZE register.

Cache DBI and iATU physical addresses in 'struct dw_pcie' so that
pcie_qcom.c driver can program these addresses in the PARF_DBI_BASE_ADDR
and PARF_ATU_BASE_ADDR registers.

Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/linux-pci/20240814220338.1969668-1-quic_pyarlaga@quicinc.com
Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Mayank Rana <quic_mrana@quicinc.com>
2024-09-01 08:12:27 +00:00
Manivannan Sadhasivam
4581403f67
PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt
Historically, Qcom PCIe RC controllers lacked standard hotplug support. So
when an endpoint is attached to the SoC, users have to rescan the bus
manually to enumerate the device. But this can be avoided by using the Link
up event exposed by the Qcom specific 'global_irq' interrupt.

Qcom PCIe RC controllers are capable of generating the 'global' SPI
interrupt to the host CPUs. The device driver can use this interrupt to
identify events such as PCIe link specific events, safety events etc...

One such event is the PCIe Link up event generated when an endpoint is
detected on the bus and the Link is 'up'. This event can be used to
enumerate the PCIe endpoint devices without user intervention.

So add support for capturing the PCIe Link up event using the 'global'
interrupt in the driver. Once the Link up event is received, the bus
underneath the host bridge is scanned to enumerate PCIe endpoint devices.

All of the Qcom SoCs have only one Root Port per controller instance. So
only a single 'Link up' event is generated for the PCIe controller.

Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-11-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
2024-09-01 08:12:26 +00:00
Manivannan Sadhasivam
bba1251edf
PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
Currently, the IRQ device name for both of these IRQs doesn't have Qcom
specific prefix and PCIe domain number. This causes 2 issues:

1. Pollutes the global IRQ namespace since 'global' is a common name.
2. When more than one EP controller instance is present in the SoC, naming
conflict will occur.

Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ
names to uniquely identify the IRQs and also to fix the above mentioned
issues.

Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-6-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
2024-09-01 08:12:26 +00:00
Manivannan Sadhasivam
95bebcbd65
PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event
Current error message just prints the contents of PARF_INT_ALL_STATUS
register as if like the IRQ event number. It could mislead the users.
Reword it to make it clear that the error message is actually showing the
interrupt status register to help debug spurious IRQ events.

While at it, let's also switch over to dev_WARN_ONCE() so that any IRQ
storm won't flood the kernel log buffer.

Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-2-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
2024-09-01 08:12:26 +00:00
Manivannan Sadhasivam
3858e8a5ea
PCI: qcom-ep: Drop the redundant masking of global IRQ events
Once the events are disabled in PARF_INT_ALL_MASK register, only the
enabled events will generate global IRQ. So there is no need to do the
masking again in the IRQ handler, drop it.

If there are any spurious IRQs getting generated, they will be reported
using the existing dev_err() in the handler.

Link: https://lore.kernel.org/linux-pci/20240828-pci-qcom-hotplug-v4-1-263a385fbbcb@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
2024-09-01 08:12:13 +00:00
Manivannan Sadhasivam
db1ec60fba PCI: qcom: Use OPP only if the platform supports it
With commit 5b6272e0ef ("PCI: qcom: Add OPP support to scale
performance"), OPP was used to control the interconnect and power domains
if the platform supported OPP. Also to maintain the backward compatibility
with platforms not supporting OPP but just ICC, the above mentioned commit
assumed that if ICC was not available on the platform, it would resort to
OPP.

Unfortunately, some old platforms don't support either ICC or OPP. On those
platforms, resorting to OPP in the absence of ICC throws below errors from
OPP core during suspend and resume:

  qcom-pcie 1c08000.pcie: dev_pm_opp_set_opp: device opp doesn't exist
  qcom-pcie 1c08000.pcie: _find_key: OPP table not found (-19)

Also, it doesn't make sense to invoke the OPP APIs when OPP is not
supported by the platform at all.

Add a "use_pm_opp" flag to identify whether OPP is supported and use it to
control invoking the OPP APIs.

Fixes: 5b6272e0ef ("PCI: qcom: Add OPP support to scale performance")
Link: https://lore.kernel.org/linux-pci/20240722131128.32470-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mayank Rana <quic_mrana@quicinc.com>
2024-08-21 16:31:41 -05:00
Manivannan Sadhasivam
5d6a6c7454 PCI: qcom-ep: Disable MHI RAM data parity error interrupt for SA8775P SoC
SA8775P SoC has support for the hardware parity check feature on the MHI
RAM (entity that holds MHI registers, etc.) But due to a hardware bug in
the parity check logic, the data parity error interrupt is getting
generated all the time when using MHI. So the hardware team has suggested
disabling the parity check error to work around the hardware bug.

Mask the parity error interrupt in PARF_INT_ALL_5_MASK register.

Fixes: 58d0d3e032 ("PCI: qcom-ep: Add support for SA8775P SOC")
Link: https://lore.kernel.org/linux-pci/20240808063057.7394-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-08-21 16:30:42 -05:00
Dan Carpenter
6188a1c762
PCI: keystone: Fix if-statement expression in ks_pcie_quirk()
This code accidentally uses && where || was intended.  It potentially
results in a NULL dereference.

Thus, fix the if-statement expression to use the correct condition.

Fixes: 86f271f22b ("PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)")
Link: https://lore.kernel.org/linux-pci/1b762a93-e1b2-4af3-8c04-c8843905c279@stanley.mountain
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-08-13 20:07:58 +00:00
Marek Vasut
363d53acbf PCI: dwc: Silence 'set affinity failed' warning
Use MSI_FLAG_NO_AFFINITY, which keeps .irq_set_affinity() unset and allows
migrate_one_irq() to exit right away, without warnings like this:

  IRQ...: set affinity failed(-22)

Remove the .irq_set_affinity() implementation that is no longer needed.

Link: https://lore.kernel.org/r/20240723132958.41320-6-marek.vasut+renesas@mailbox.org
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
2024-07-29 12:46:35 -05:00
Bjorn Helgaas
45659274e6 Merge branch 'pci/misc'
- Remove unused struct 'acpi_handle_node' (Dr. David Alan Gilbert)

- Use array notation for portdrv .id_table consistently (Masahiro Yamada)

- Switch to new Intel CPU model defines (Tony Luck)

- Add missing MODULE_DESCRIPTION() macros (Jeff Johnson)

* pci/misc:
  PCI: controller: Add missing MODULE_DESCRIPTION() macros
  PCI: Add missing MODULE_DESCRIPTION() macros
  PCI/PM: Switch to new Intel CPU model defines
  PCI: Use array for .id_table consistently
  ACPI: PCI: Remove unused struct 'acpi_handle_node'
2024-07-19 10:10:33 -05:00
Bjorn Helgaas
99329ded09 Merge branch 'pci/controller/tegra194'
- Ensure Tegra194 and Tegra234 inbound ATU entries are 64KB-aligned to
  match the hardware restriction (Jon Hunter)

- Remove unused struct 'tegra_pcie_soc' (Dr. David Alan Gilbert)

* pci/controller/tegra194:
  PCI: tegra: Remove unused struct 'tegra_pcie_soc'
  PCI: tegra194: Set EP alignment restriction for inbound ATU
2024-07-19 10:10:32 -05:00
Bjorn Helgaas
8240a9b4a5 Merge branch 'pci/controller/rockchip'
- Use dev_err_probe() in dw-rockchip probe error path so the failures
  aren't silent (Uwe Kleine-König)

- Sleep PCIE_T_PVPERL_MS (100ms) before deasserting PERST# (Damien Le Moal)

- Sleep PCIE_T_RRS_READY_MS (100ms) after conventional reset, before a
  config access (Damien Le Moal)

- Request the PERST# GPIO with GPIOD_OUT_LOW so it matches the POR value,
  which avoids a spurious PERST# assertion and fixes a Qcom modem firmware
  crash and issues with WLAN controllers, e.g., RTL8822CE (Manivannan
  Sadhasivam for rockchip, Niklas Cassel for dw-rockchip)

- Refactor dw-rockchip and add support for Endpoint mode for rk3568 and
  rk3588 (Niklas Cassel)

* pci/controller/rockchip:
  PCI: dw-rockchip: Use pci_epc_init_notify() directly
  PCI: dw-rockchip: Add endpoint mode support
  PCI: dw-rockchip: Refactor the driver to prepare for EP mode
  PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
  PCI: dw-rockchip: Fix weird indentation
  PCI: dw-rockchip: Fix initial PERST# GPIO value
  PCI: dw-rockchip: Add error messages in .probe() error paths
  PCI: rockchip: Use GPIOD_OUT_LOW flag while requesting ep_gpio
  PCI: rockchip-host: Wait 100ms after reset before starting configuration
  PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
2024-07-19 10:10:32 -05:00
Bjorn Helgaas
59dd7046b4 Merge branch 'pci/controller/rcar-gen4'
- Add Synopsys DWC macros for lane skew configuration (Yoshihiro Shimoda)

- Add struct rcar_gen4_pcie_drvdata to provide for future SoCs with
  different initialization requirements (Yoshihiro Shimoda)

- Add .ltssm_control() method for SoC dependencies (Yoshihiro Shimoda)

- Add r8a779g0 (R-Car V4H) support (Yoshihiro Shimoda)

* pci/controller/rcar-gen4:
  PCI: rcar-gen4: Add support for R-Car V4H
  PCI: rcar-gen4: Add .ltssm_control() for other SoC support
  PCI: rcar-gen4: Add struct rcar_gen4_pcie_drvdata
  PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
2024-07-19 10:10:31 -05:00
Bjorn Helgaas
df5dd33728 Merge branch 'pci/controller/qcom'
- Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid
  writing out all the clock names (Manivannan Sadhasivam)

- Add DT binding and driver support for the SA8775P SoC (Mrinmay Sarkar)

- Refactor dw_pcie_edma_find_chip() to enable adding support for Hyper DMA
  (HDMA) (Manivannan Sadhasivam)

- Enable drivers to supply the eDMA channel count since some can't auto
  detect this (Manivannan Sadhasivam)

- Add HDMA support for the SA8775P SoC (Mrinmay Sarkar)

- Override the SA8775P NO_SNOOP default to avoid possible memory corruption
  (Mrinmay Sarkar)

- Make sure resources are disabled during PERST# assertion, even if the
  link is already disabled (Manivannan Sadhasivam)

- Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays active
  even if other drivers don't vote for it (Krishna chaitanya chundru)

- Add Operating Performance Points (OPP) to scale performance state based
  on aggregate link bandwidth to improve SoC power efficiency (Krishna
  chaitanya chundru)

- Return failure instead of success if dev_pm_opp_find_freq_floor() fails
  (Dan Carpenter)

- Avoid an error pointer dereference if dev_pm_opp_find_freq_exact() fails
  (Dan Carpenter)

- Prevent use of uninitialized data in qcom_pcie_suspend_noirq() (Dan
  Carpenter)

* pci/controller/qcom:
  PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq()
  PCI: qcom: Prevent potential error pointer dereference
  PCI: qcom: Fix missing error code in qcom_pcie_probe()
  PCI: qcom: Add OPP support to scale performance
  PCI: Bring the PCIe speed to MBps logic to new pcie_dev_speed_mbps()
  PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path
  PCI: qcom-ep: Disable resources unconditionally during PERST# assert
  PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP
  PCI: qcom: Override NO_SNOOP attribute for SA8775P RC
  PCI: epf-mhi: Enable HDMA for SA8775P SoC
  PCI: qcom-ep: Add HDMA support for SA8775P SoC
  PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers
  PCI: dwc: Skip finding eDMA channels count for HDMA platforms
  PCI: dwc: Refactor dw_pcie_edma_find_chip() API
  PCI: qcom-ep: Add support for SA8775P SOC
  dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC
  PCI: qcom: Use devm_clk_bulk_get_all() API
2024-07-19 10:10:31 -05:00
Bjorn Helgaas
db2cc94fae Merge branch 'pci/controller/keystone'
- Enable BAR 0 only for v3.65a to avoid Completion Timeouts that
  cause a 45 second boot delay on the v4.90a-based AM654x SoC (Siddharth
  Vadapalli)

- Avoid a NULL pointer dereference if DT failed to provide a host bridge
  memory window (Aleksandr Mishin)

* pci/controller/keystone:
  PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
  PCI: keystone: Fix NULL pointer dereference in case of DT error in ks_pcie_setup_rc_app_regs()
  PCI: keystone: Don't enable BAR 0 for AM654x
  PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()
2024-07-19 10:10:28 -05:00
Bjorn Helgaas
da3552d225 Merge branch 'pci/controller/exynos'
- Use devm_clk_bulk_get_all_enable() to simplify clock setup (Shradha Todi)

* pci/controller/exynos:
  PCI: exynos: Adapt to use bulk clock APIs
2024-07-19 10:10:27 -05:00
Bjorn Helgaas
1d97f4b215 Merge branch 'pci/controller/dra7xx'
- Correct the dra7xx_pcie_cpu_addr_fixup() parameter name, which takes a
  CPU address but called it "pci_addr" (Niklas Cassel)

* pci/controller/dra7xx:
  PCI: dra7xx: Fix dra7xx_pcie_cpu_addr_fixup() parameter name
2024-07-19 10:10:27 -05:00
Bjorn Helgaas
43f25adf9f Merge branch 'pci/controller/artpec6'
- Correct the artpec6_pcie_cpu_addr_fixup() parameter name, which takes a
  CPU address but called it "pci_addr" (Niklas Cassel)

* pci/controller/artpec6:
  PCI: artpec6: Fix artpec6_pcie_cpu_addr_fixup() parameter name
2024-07-19 10:10:26 -05:00
Bjorn Helgaas
e38de94edd Merge branch 'pci/controller/al'
- Check IORESOURCE_BUS existence to avoid NULL pointer dereference
  (Aleksandr Mishin)

* pci/controller/al:
  PCI: al: Check IORESOURCE_BUS existence during probe
2024-07-19 10:10:26 -05:00
Bjorn Helgaas
3785393285 Merge branch 'pci/controller/dwc'
- Use msleep() in DWC core instead of usleep_range() for ~100 ms sleep
  (Konrad Dybcio)

- Fix iATU slot management to avoid using the wrong slot after PERST#
  assert/deassert, which could potentially cause DMA to go the wrong place
  (Frank Li)

- Consolidate dw_pcie_prog_outbound_atu() arguments into a struct to ease
  adding new functionality like initiating Message TLPs (Yoshihiro Shimoda)

- Add support for endpoints to initiate PCIe messages (Yoshihiro Shimoda)

- Add #defines for PCIe INTx messages (Yoshihiro Shimoda)

- Add support for endpoints to initiate PCIe PME_Turn_Off messages for
  system suspend (Frank Li)

- Add dw_pcie_ep_linkdown() to reinitialize registers that are lost when
  the link goes down (Manivannan Sadhasivam)

- Use dw_pcie_ep_linkdown() to reinitialize qcom non-sticky registers that
  are lost when the link goes down (Manivannan Sadhasivam)

- Enforce DWC limitation that 64-bit BARs must start with the even numbered
  BAR (Niklas Cassel)

* pci/controller/dwc:
  PCI: dwc: ep: Enforce DWC specific 64-bit BAR limitation
  PCI: layerscape-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event
  PCI: qcom-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event
  PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper
  PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event
  PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend
  PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro
  PCI: Add PCIE_MSG_CODE_ASSERT_INTx message macros
  PCI: dwc: Add outbound MSG TLPs support
  PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structure
  PCI: dwc: Fix index 0 incorrectly being interpreted as a free ATU slot
  PCI: dwc: Use msleep() in dw_pcie_wait_for_link()
2024-07-19 10:10:25 -05:00
Bjorn Helgaas
35f0c94a12 Merge branch 'pci/controller/gpio'
- Include <linux/irqchip/chained_irq.h> in dra7xx to avoid implicitly
  including it elsewhere (Andy Shevchenko)

- Remove unused <linux/of_gpio.h> from aardvark and dwc drivers (dra7xx,
  meson, qcom, tegra194) (Andy Shevchenko)

- Convert kirin to use scoped for_each_available_child_of_node() to ease
  future error exits (Javier Carrasco)

- Convert imx6 and kirin to use the agnostic GPIO API to simplify GPIO
  setup and remove usage of the deprecated of_gpio.h API (Andy Shevchenko)

* pci/controller/gpio:
  PCI: kirin: Convert to use agnostic GPIO API
  PCI: kirin: Convert kirin_pcie_parse_port() to scoped iterator
  PCI: imx6: Convert to use agnostic GPIO API
  PCI: dwc: Remove unused of_gpio.h inclusion
  PCI: aardvark: Remove unused of_gpio.h inclusion
  PCI: dra7xx: Add missing chained IRQ header inclusion
2024-07-19 10:10:25 -05:00
Dan Carpenter
044b45be04
PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq()
Smatch complains that "ret" could be uninitialized if "pcie->icc_mem" is
NULL and "pm_suspend_target_state == PM_SUSPEND_MEM".

Silence this warning by initializing ret to zero.

Fixes: 78b5f6f8855e ("PCI: qcom: Add OPP support to scale performance")
Link: https://lore.kernel.org/linux-pci/20240708180539.1447307-4-dan.carpenter@linaro.org
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-10 05:39:15 +00:00
Dan Carpenter
9553636b57
PCI: qcom: Prevent potential error pointer dereference
Only call dev_pm_opp_put() if dev_pm_opp_find_freq_exact() succeeds;
otherwise it leads to an error pointer dereference.

Fixes: 78b5f6f8855e ("PCI: qcom: Add OPP support to scale performance")
Link: https://lore.kernel.org/linux-pci/20240708180539.1447307-3-dan.carpenter@linaro.org
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-10 05:39:11 +00:00
Dan Carpenter
101e5c5c4e
PCI: qcom: Fix missing error code in qcom_pcie_probe()
Return a negative error code if dev_pm_opp_find_freq_floor() fails;
don't return success.

Fixes: 78b5f6f8855e ("PCI: qcom: Add OPP support to scale performance")
Link: https://lore.kernel.org/linux-pci/20240708180539.1447307-2-dan.carpenter@linaro.org
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Anders Roxell <anders.roxell@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-10 05:38:51 +00:00
Niklas Cassel
84e30b878a PCI: dw-rockchip: Use pci_epc_init_notify() directly
A previous commit ("PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper")
removed the dw_pcie_ep_init_notify() wrapper and changed the DWC glue
drivers to instead use pci_epc_init_notify() directly.

The endpoint support for the dw-rockchip had not been merged at that point
in time, so the previous commit wrapper") did not update dw-rockchip.

Do the same change for dw-rockchip, so that the driver will not try
to use a function that has now been removed.

Link: https://lore.kernel.org/linux-pci/20240622132024.2927799-2-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-07-09 18:29:45 -05:00
Niklas Cassel
e242f26f63 PCI: dw-rockchip: Add endpoint mode support
The PCIe controller in rk3568 and rk3588 can operate in endpoint mode.

This endpoint mode support heavily leverages the existing code in
pcie-designware-ep.c.

Add support for endpoint mode to the existing pcie-dw-rockchip glue
driver.

[kwilczynski: squash with patch adding the PCI_ENDPOINT dependency]
Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-10-0a042d6b0049@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:29:36 -05:00
Niklas Cassel
49a0925d17 PCI: dw-rockchip: Refactor the driver to prepare for EP mode
Refactor the driver to prepare for EP mode.

Add of-match data to the existing compatible, and explicitly define it as
DW_PCIE_RC_TYPE. This way, we will be able to add EP mode in a follow-up
commit in a much less intrusive way, which makes the follow-up commit much
easier to review.

No functional change intended.

Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-9-0a042d6b0049@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:29:05 -05:00
Niklas Cassel
d8b864c95d PCI: dw-rockchip: Add rockchip_pcie_get_ltssm() helper
Add a rockchip_pcie_ltssm() helper function that reads the LTSSM status.

This helper will be used in additional places in follow-up commits.

Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-8-0a042d6b0049@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:28:57 -05:00
Niklas Cassel
2baa5fc389 PCI: dw-rockchip: Fix weird indentation
Fix the indentation of rockchip_pcie_{readl,writel}_apb() parameters to
match the opening parenthesis.

Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-7-0a042d6b0049@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:28:51 -05:00
Niklas Cassel
28b8d7793b PCI: dw-rockchip: Fix initial PERST# GPIO value
PERST# is active low according to the PCIe specification.

However, the existing pcie-dw-rockchip.c driver does:

  gpiod_set_value(..., 0); msleep(100); gpiod_set_value(..., 1);

when asserting + deasserting PERST#.

This is of course wrong, but because all the device trees for this
compatible string have also incorrectly marked this GPIO as ACTIVE_HIGH:

  $ git grep -B 10 reset-gpios arch/arm64/boot/dts/rockchip/rk3568*
  $ git grep -B 10 reset-gpios arch/arm64/boot/dts/rockchip/rk3588*

The actual toggling of PERST# is correct, and we cannot change it anyway,
since that would break device tree compatibility.

However, this driver does request the GPIO to be initialized as
GPIOD_OUT_HIGH, which does cause a silly sequence where PERST# gets
toggled back and forth for no good reason.

Fix this by requesting the GPIO to be initialized as GPIOD_OUT_LOW (which
for this driver means PERST# asserted).

This will avoid an unnecessary signal change where PERST# gets deasserted
(by devm_gpiod_get_optional()) and then gets asserted (by
rockchip_pcie_start_link()) just a few instructions later.

Before patch, debug prints on EP side, when booting RC:

  [  845.606810] pci: PERST# asserted by host!
  [  852.483985] pci: PERST# de-asserted by host!
  [  852.503041] pci: PERST# asserted by host!
  [  852.610318] pci: PERST# de-asserted by host!

After patch, debug prints on EP side, when booting RC:

  [  125.107921] pci: PERST# asserted by host!
  [  132.111429] pci: PERST# de-asserted by host!

This extra, very short, PERST# assertion + deassertion has been reported to
cause issues with certain WLAN controllers, e.g. RTL8822CE.

Fixes: 0e898eb8df ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver")
Link: https://lore.kernel.org/linux-pci/20240417164227.398901-1-cassel@kernel.org
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: stable@vger.kernel.org	# v5.15+
2024-07-09 18:28:40 -05:00
Uwe Kleine-König
206c4f778b PCI: dw-rockchip: Add error messages in .probe() error paths
Drivers that silently fail to probe provide a bad user experience and
make it unnecessarily hard to debug such a failure.

Fix it by using dev_err_probe() instead of a plain return.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240227141256.413055-2-ukleinek@debian.org
Signed-off-by: Uwe Kleine-König <ukleinek@debian.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jesper Nilsson <jesper.nilsson@axis.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:28:37 -05:00
Niklas Cassel
9b10e877fc PCI: dwc: ep: Enforce DWC specific 64-bit BAR limitation
From the DWC EP databook 5.96a, section "3.5.7.1.4 General Rules for BAR
Setup (Fixed Mask or Programmable Mask Schemes Only)":

"Any pair (for example BARs 0 and 1) can be configured as one 64-bit BAR,
two 32-bit BARs, or one 32-bit BAR."

"BAR pairs cannot overlap to form a 64-bit BAR. For example, you cannot
combine BARs 1 and 2 to form a 64-bit BAR."

While this limitation does exist in some other PCI endpoint controllers,
e.g. cdns_pcie_ep_set_bar(), the limitation does not appear to be defined
in the PCIe specification itself, thus add an explicit check for this in
dw_pcie_ep_set_bar() (rather than pci_epc_set_bar()).

Link: https://lore.kernel.org/linux-pci/20240528134839.8817-2-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:21:39 -05:00
Manivannan Sadhasivam
b8747e10fd PCI: layerscape-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event
Now that dw_pcie_ep_linkdown() is available, use it. This also handles the
reinitialization of DWC non-sticky registers in addition to sending the
notification to EPF drivers.

Closes: https://lore.kernel.org/linux-pci/20240528195539.GA458945@bhelgaas
Link: https://lore.kernel.org/linux-pci/20240606-pci-deinit-v1-5-4395534520dc@linaro.org
Reported-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-07-09 18:21:11 -05:00
Manivannan Sadhasivam
574621166c PCI: qcom-ep: Use the generic dw_pcie_ep_linkdown() API to handle Link Down event
Now that the generic dw_pcie_ep_linkdown() API is available, use it. This
also handles the reinitialization of DWC non-sticky registers in addition
to sending the notification to EPF drivers.

Link: https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-9-22832d0d456f@linaro.org
Tested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-07-09 18:20:49 -05:00
Manivannan Sadhasivam
245b9ebf7b PCI: dwc: ep: Remove dw_pcie_ep_init_notify() wrapper
Currently dw_pcie_ep_init_notify() wrapper just calls pci_epc_init_notify()
directly, so this wrapper provides no benefit to the glue drivers.

Remove it and call pci_epc_init_notify() directly from glue drivers.

Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/linux-pci/20240606-pci-deinit-v1-1-4395534520dc@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-07-09 18:20:21 -05:00
Manivannan Sadhasivam
867ab111b2 PCI: dwc: ep: Add a generic dw_pcie_ep_linkdown() API to handle Link Down event
Per PCIe r6.0, sec 5.2, a Link Down event can happen under any of the
following circumstances:

  1. Fundamental/Hot reset
  2. Link disable transmission by upstream component
  3. Moving from L2/L3 to L0

In those cases, Link Down causes some non-sticky DWC registers to lose the
state (like REBAR, etc.), so drivers need to reinitialize them to function
properly once the link comes back again.

This is not a problem for drivers supporting PERST# IRQ, since they can
reinitialize the registers in the PERST# IRQ callback. But for the drivers
not supporting PERST#, there is no way they can reinitialize the registers
other than relying on Link Down IRQ received when the link goes down. So
add a DWC generic API dw_pcie_ep_linkdown() that reinitializes the
non-sticky registers and also notifies the EPF drivers about link going
down.

This API can also be used by the drivers supporting PERST# to handle the
scenario (2) mentioned above.

NOTE: For the sake of code organization, move the dw_pcie_ep_linkup()
definition just above dw_pcie_ep_linkdown().

Link: https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-8-22832d0d456f@linaro.org
Tested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: update spec citation]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-07-09 18:20:18 -05:00
Frank Li
e1a4ec1a95 PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend
Instead of relying on the vendor specific implementations to send the
PME_Turn_Off message, introduce a generic way of sending the message using
the MSG TLP.

This is achieved by reserving a region for MSG TLP of size
'pci->region_align', at the end of the first IORESOURCE_MEM window of the
host bridge. And then sending the PME_Turn_Off message during system
suspend with the help of iATU.

The reason for reserving the MSG TLP region at the end of the
IORESOURCE_MEM is to avoid generating holes in between, because when the
region is allocated using allocate_resource(), memory will be allocated
from the start of the window. Later, if memory gets allocated for an
endpoint of size bigger than 'region_align', there will be a hole between
MSG TLP region and endpoint memory.

This generic implementation is optional for the glue drivers and can be
overridden by a custom 'pme_turn_off' callback.

Link: https://lore.kernel.org/linux-pci/20240418-pme_msg-v8-5-a54265c39742@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:20:15 -05:00
Yoshihiro Shimoda
cd02e4b684 PCI: dwc: Add outbound MSG TLPs support
Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
INTx IRQs by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. This implementation supports the data-less messages only for now.

Link: https://lore.kernel.org/linux-pci/20240418-pme_msg-v8-3-a54265c39742@nxp.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
2024-07-09 18:20:08 -05:00
Yoshihiro Shimoda
aa85ef61d8 PCI: dwc: Consolidate args of dw_pcie_prog_outbound_atu() into a structure
This is a preparation before adding the Msg-type outbound iATU
mapping. The respective update will require two more arguments added
to __dw_pcie_prog_outbound_atu(). That will make the already
complicated function prototype even more hard to comprehend accepting
_eight_ arguments.

To prevent that and keep the code more-or-less readable, move all the
outbound iATU-related arguments to a new config structure: struct
dw_pcie_ob_atu_cfg, and pass a pointer to dw_pcie_prog_outbound_atu(). The
structure should be locally defined and populated with the outbound iATU
settings implied by the caller context.

As a result of this change there is no longer need in having the two
distinctive methods for the Host and Endpoint outbound iATU setups since
the code can directly call the dw_pcie_prog_outbound_atu() method with the
config structure populated, so drop dw_pcie_prog_ep_outbound_atu().

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240418-pme_msg-v8-2-a54265c39742@nxp.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
2024-07-09 18:20:05 -05:00
Frank Li
c2a57ee0f2 PCI: dwc: Fix index 0 incorrectly being interpreted as a free ATU slot
When PERST# assert and deassert happens on the PERST# supported platforms,
both iATU0 and iATU6 will map inbound window to BAR0. DMA will access the
area that was previously allocated (iATU0) for BAR0, instead of the new
area (iATU6) for BAR0.

Right now, this isn't an issue because both iATU0 and iATU6 should
translate inbound accesses to BAR0 to the same allocated memory area.
However, having two separate inbound mappings for the same BAR is a
disaster waiting to happen.

The mappings between PCI BAR and iATU inbound window are maintained in the
dw_pcie_ep::bar_to_atu[] array. While allocating a new inbound iATU map for
a BAR, dw_pcie_ep_inbound_atu() API checks for the availability of the
existing mapping in the array and if it is not found (i.e., value in the
array indexed by the BAR is found to be 0), it allocates a new map value
using find_first_zero_bit().

The issue is the existing logic failed to consider the fact that the map
value '0' is a valid value for BAR0, so find_first_zero_bit() will return
'0' as the map value for BAR0 (note that it returns the first zero bit
position).

Due to this, when PERST# assert + deassert happens on the PERST# supported
platforms, the inbound window allocation restarts from BAR0 and the
existing logic to find the BAR mapping will return '6' for BAR0 instead of
'0' due to the fact that it considers '0' as an invalid map value.

Fix this issue by always incrementing the map value before assigning to
bar_to_atu[] array and then decrementing it while fetching. This will make
sure that the map value '0' always represents the invalid mapping."

Fixes: 4284c88fff ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address")
Closes: https://lore.kernel.org/linux-pci/ZXsRp+Lzg3x%2Fnhk3@x1-carbon/
Link: https://lore.kernel.org/linux-pci/20240412160841.925927-1-Frank.Li@nxp.com
Reported-by: Niklas Cassel <Niklas.Cassel@wdc.com>
Tested-by: Niklas Cassel <niklas.cassel@wdc.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Niklas Cassel <niklas.cassel@wdc.com>
2024-07-09 18:20:02 -05:00
Konrad Dybcio
b262518262 PCI: dwc: Use msleep() in dw_pcie_wait_for_link()
According to [1], msleep should be used for large sleeps, such as the
100-ish ms one in this function. Comply with the guide and use it.

[1] https://docs.kernel.org/timers/timers-howto.html

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240215-topic-pci_sleep-v2-1-79334884546b@linaro.org
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 18:19:58 -05:00
Andy Shevchenko
d03b2dd785 PCI: kirin: Convert to use agnostic GPIO API
The of_gpio.h legacy API is going to be removed. In preparation for that,
convert the driver to the agnostic API.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240506142142.4042810-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
2024-07-09 17:46:19 -05:00
Javier Carrasco
7e8e4fc532 PCI: kirin: Convert kirin_pcie_parse_port() to scoped iterator
Convert loops in kirin_pcie_parse_port() to use the _scoped() version of
for_each_available_child_of_node() so the refcounts of children are
implicitly decremented when the loop is exited.

No functional change intended here, but it will make future error exits
from these loops easier.

Link: https://lore.kernel.org/linux-pci/20240609-pcie-kirin-memleak-v1-1-62b45b879576@gmail.com
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: move to GPIO series to avoid bisection hole, commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-07-09 17:40:34 -05:00
Krishna chaitanya chundru
5b6272e0ef PCI: qcom: Add OPP support to scale performance
QCOM Resource Power Manager-hardened (RPMh) is a hardware block which
maintains hardware state of a regulator by performing max aggregation of
the requests made by all of the clients.

PCIe controller can operate on different RPMh performance state of power
domain based on the speed of the link. And this performance state varies
from target to target, like some controllers support GEN3 in NOM (Nominal)
voltage corner, while some other supports GEN3 in low SVS (static voltage
scaling).

The SoC can be more power efficient if we scale the performance state
based on the aggregate PCIe link bandwidth.

Add Operating Performance Points (OPP) support to vote for RPMh state based
on the aggregate link bandwidth.

OPP can handle ICC bw voting also, so move ICC bw voting through OPP
framework if OPP entries are present.

As we are moving ICC voting as part of OPP, don't initialize ICC if OPP
is supported.

Before PCIe link is initialized vote for highest OPP in the OPP table,
so that we are voting for maximum voltage corner for the link to come up
in maximum supported speed.

Link: https://lore.kernel.org/linux-pci/20240619-opp_support-v15-4-aa769a2173a3@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: wrap comments to fit in 80 columns]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 16:56:43 -05:00
Krishna chaitanya chundru
980136d1c2 PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path
To access the host controller registers of the host controller and the
endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should
be voted otherwise it may lead to NoC (Network on chip) timeout.
We are surviving because of other driver voting for this path.

As there is less access on this path compared to PCIe to mem path
add minimum vote i.e 1KBps bandwidth always which is sufficient enough
to keep the path active and is recommended by HW team.

During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while
disabling the boot CPU). So do not disable the CPU-PCIe interconnect path
during S2RAM as that may lead to NoC error.

Link: https://lore.kernel.org/linux-pci/20240619-opp_support-v15-1-aa769a2173a3@quicinc.com
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 16:56:32 -05:00
Manivannan Sadhasivam
912315715d PCI: qcom-ep: Disable resources unconditionally during PERST# assert
All EP specific resources are enabled during PERST# deassert. As a counter
operation, all resources should be disabled during PERST# assert. There is
no point in skipping that if the link was not enabled.

This will also result in enablement of the resources twice if PERST# got
deasserted again. So remove the check from qcom_pcie_perst_assert() and
disable all the resources unconditionally.

Fixes: f55fee56a6 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
Link: https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-1-22832d0d456f@linaro.org
Tested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-07-09 16:56:30 -05:00
Mrinmay Sarkar
c71b5eb3b8 PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP
Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
the requester is indicating that no cache coherency issues exist for
the addressed memory on the host i.e., memory is not cached. But in
reality, requester cannot assume this unless there is a complete
control/visibility over the addressed memory on the host.

And worst case, if the memory is cached on the host, it may lead to
memory corruption issues. It should be noted that the caching of memory
on the host is not solely dependent on the NO_SNOOP attribute in TLP.

So to avoid the corruption, this patch overrides the NO_SNOOP attribute
by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
needed for other upstream supported platforms since they do not set
NO_SNOOP attribute by default.

Link: https://lore.kernel.org/linux-pci/1710166298-27144-3-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 16:56:25 -05:00
Mrinmay Sarkar
1d648bf79d PCI: qcom: Override NO_SNOOP attribute for SA8775P RC
Due to some hardware changes, SA8775P has set the NO_SNOOP attribute
in its TLP for all the PCIe controllers. NO_SNOOP attribute when set,
the requester is indicating that no cache coherency issue exist for
the addressed memory on the endpoint i.e., memory is not cached. But
in reality, requester cannot assume this unless there is a complete
control/visibility over the addressed memory on the endpoint.

And worst case, if the memory is cached on the endpoint, it may lead to
memory corruption issues. It should be noted that the caching of memory
on the endpoint is not solely dependent on the NO_SNOOP attribute in TLP.

So to avoid the corruption, this patch overrides the NO_SNOOP attribute
by setting the PCIE_PARF_NO_SNOOP_OVERIDE register. This patch is not
needed for other upstream supported platforms since they do not set
NO_SNOOP attribute by default.

8775 has IP version 1.34.0 so introduce a new cfg(cfg_1_34_0) for this
platform. Assign override_no_snoop flag into struct qcom_pcie_cfg and
set it true in cfg_1_34_0 and enable cache snooping if this particular
flag is true.

Link: https://lore.kernel.org/linux-pci/1710166298-27144-2-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: wrap comments to fit in 80 columns]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-09 16:52:19 -05:00
Jeff Johnson
142a41da39
PCI: controller: Add missing MODULE_DESCRIPTION() macros
When ARCH=x86, make allmodconfig && make W=1 C=1 reports:

  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/dwc/pci-exynos.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pci-host-generic.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-altera.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-altera-msi.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-mediatek.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-mediatek-gen3.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/vmd.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-apple.o
  WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/pci/controller/pcie-mt7621.o

Add the missing MODULE_DESCRIPTION() macro.

[kwilczynski: update MODULE_DESCRIPTION() text, commit log]
Link: https://lore.kernel.org/linux-pci/20240626-md-drivers-pci-controller-v2-1-94c811db7a51@quicinc.com
Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Nirmal Patel <nirmal.patel@linux.intel.com>
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> # MT7621
2024-07-08 08:36:14 +00:00
Manivannan Sadhasivam
473b2cf9c4
PCI: endpoint: Introduce 'epc_deinit' event and notify the EPF drivers
As like the 'epc_init' event, that is used to signal the EPF drivers about
the EPC initialization, let's introduce 'epc_deinit' event that is used to
signal EPC deinitialization.

The EPC deinitialization applies only when any sort of fundamental reset
is supported by the endpoint controller as per the PCIe spec.

Reference: PCIe r6.0, sec 4.2.5.9.1 and 6.6.1.

Currently, some EPC drivers like pcie-qcom-ep and pcie-tegra194 support
PERST# as the fundamental reset. So the 'deinit' event will be notified to
the EPF drivers when PERST# assert happens in the above mentioned EPC
drivers.

The EPF drivers, on receiving the event through the epc_deinit() callback
should reset the EPF state machine and also cleanup any configuration that
got affected by the fundamental reset like BAR, DMA etc...

This change also warrants skipping the cleanups in unbind() if already done
in epc_deinit().

Link: https://lore.kernel.org/r/20240606-pci-deinit-v1-2-4395534520dc@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
2024-07-04 14:40:53 +00:00
Yoshihiro Shimoda
faf5a975ee
PCI: rcar-gen4: Add support for R-Car V4H
Add support for r8a779g0 (R-Car V4H).

This driver previously supported r8a779f0 (R-Car S4-8). PCIe features
of both r8a779f0 and r8a779g0 are almost all the same. For example:

 - PCI Express Base Specification Revision 4.0
 - Root complex mode and endpoint mode are supported

However, r8a779g0 requires specific firmware to be provided, to
initialize the PHY. Otherwise, the PCIe controller will not work.

[kwilczynski: drop the proprietary firmware conversion comment]
Link: https://lore.kernel.org/linux-pci/20240611125057.1232873-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-07-01 22:33:03 +00:00
Yoshihiro Shimoda
2c49151b3f
PCI: rcar-gen4: Add .ltssm_control() for other SoC support
Sequence for controlling the LTSSM state machine is going to change
for SoCs like r8a779f0. Move the LTSSM code to a new callback
ltssm_control() and populate it for each SoCs.

This also warrants the addition of new compatibles for r8a779g0 and
r8a779h0. But since they are already part of the DT binding, it won't
make any difference.

Link: https://lore.kernel.org/linux-pci/20240611125057.1232873-4-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-06-29 19:20:41 +00:00
Yoshihiro Shimoda
ac1d89f8dc
PCI: rcar-gen4: Add struct rcar_gen4_pcie_drvdata
In order to support future SoCs such as r8a779g0 (R-Car V4H) and
r8a779h0 (R-Car V4M) that require different initialization settings,
introduce SoC specific driver data with the initial member being the
device mode.

No functional change.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240611125057.1232873-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-06-29 19:20:35 +00:00
Yoshihiro Shimoda
544a18c936
PCI: dwc: Add PCIE_PORT_{FORCE,LANE_SKEW} macros
R-Car Gen4 PCIe controller needs to use the Synopsys-specific PCIe
configuration registers. So, add the macros.

Link: https://lore.kernel.org/linux-pci/20240611125057.1232873-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-06-29 19:20:16 +00:00
Kishon Vijay Abraham I
86f271f22b
PCI: keystone: Add workaround for Errata #i2037 (AM65x SR 1.0)
Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
(SPRZ452D_July 2018_Revised December 2019 [1]) mentions when an
inbound PCIe TLP spans more than two internal AXI 128-byte bursts,
the bus may corrupt the packet payload and the corrupt data may
cause associated applications or the processor to hang.

The workaround for Errata #i2037 is to limit the maximum read
request size and maximum payload size to 128 bytes. Add workaround
for Errata #i2037 here.

The errata and workaround is applicable only to AM65x SR 1.0 and
later versions of the silicon will have this fixed.

[1] -> https://www.ti.com/lit/er/sprz452i/sprz452i.pdf

Link: https://lore.kernel.org/linux-pci/16e1fcae-1ea7-46be-b157-096e05661b15@siemens.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-06-28 21:23:59 +00:00
Dr. David Alan Gilbert
6a61183362 PCI: tegra: Remove unused struct 'tegra_pcie_soc'
'tegra_pcie_soc' has been unused since 56e15a238d ("PCI: tegra: Add
Tegra194 PCIe support").  Remove it.

Link: https://lore.kernel.org/r/20240527160118.37069-1-linux@treblig.org
Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-06-06 14:57:36 -05:00
Jon Hunter
d19a86d584 PCI: tegra194: Set EP alignment restriction for inbound ATU
Tegra194 and Tegra234 PCIe EP controllers have 64K alignment restriction
for the inbound ATU. Set the endpoint inbound ATU alignment to 64kB in the
Tegra194 PCIe driver.

Fixes: c57247f940 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Link: https://lore.kernel.org/linux-pci/20240508092207.337063-1-jonathanh@nvidia.com
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-05-28 11:16:02 -05:00
Aleksandr Mishin
a231707a91 PCI: keystone: Fix NULL pointer dereference in case of DT error in ks_pcie_setup_rc_app_regs()
If IORESOURCE_MEM is not provided in Device Tree due to
any error, resource_list_first_type() will return NULL and
pci_parse_request_of_pci_ranges() will just emit a warning.

This will cause a NULL pointer dereference. Fix this bug by adding NULL
return check.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: 0f71c60ffd ("PCI: dwc: Remove storing of PCI resources")
Link: https://lore.kernel.org/linux-pci/20240505061517.11527-1-amishin@t-argos.ru
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Aleksandr Mishin <amishin@t-argos.ru>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-05-28 11:15:15 -05:00
Siddharth Vadapalli
9ffa0e70b2 PCI: keystone: Don't enable BAR 0 for AM654x
After 6ab15b5e70 ("PCI: dwc: keystone: Convert .scan_bus() callback to
use add_bus"), ks_pcie_v3_65_add_bus() enabled BAR 0 for both v3.65a and
v4.90a devices.  On the AM654x SoC, which uses v4.90a, enabling BAR 0
causes Completion Timeouts when setting up MSI-X.  These timeouts delay
boot of the AM654x by about 45 seconds.

Move the BAR 0 initialization to ks_pcie_msi_host_init(), which is only
used for v3.65a devices, and remove ks_pcie_v3_65_add_bus().

[bhelgaas: commit log]
Fixes: 6ab15b5e70 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus")
Link: https://lore.kernel.org/linux-pci/20240328085041.2916899-3-s-vadapalli@ti.com
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Suggested-by: Niklas Cassel <cassel@kernel.org>
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-05-28 11:15:15 -05:00
Siddharth Vadapalli
5125fdc329 PCI: keystone: Relocate ks_pcie_set/clear_dbi_mode()
Relocate ks_pcie_set_dbi_mode() and ks_pcie_clear_dbi_mode() to avoid
forward declaration in a subsequent patch. No functional change intended.

Link: https://lore.kernel.org/linux-pci/20240328085041.2916899-2-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-05-28 11:15:15 -05:00
Andy Shevchenko
2e81122d68 PCI: imx6: Convert to use agnostic GPIO API
The of_gpio.h legacy API is going to be removed. In preparation for that,
convert the driver to the agnostic API.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240506142142.4042810-5-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-05-28 11:15:08 -05:00
Andy Shevchenko
050a5e4b86 PCI: dwc: Remove unused of_gpio.h inclusion
The of_gpio.h API is deprecated and subject to removal. The driver doesn't
use it, so simply remove the unused header.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240506142142.4042810-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-05-28 11:15:08 -05:00
Andy Shevchenko
7726ed06f5 PCI: dra7xx: Add missing chained IRQ header inclusion
Driver is using chained_irq_*() APIs, add the respective inclusion.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240506142142.4042810-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-05-28 11:15:08 -05:00
Shradha Todi
6b11143f93 PCI: exynos: Adapt to use bulk clock APIs
There is no need to hardcode the clock info in the driver as driver can
rely on the devicetree to supply the clocks required for the functioning
of the peripheral.

Thus, remove the static clock info and obtain the platform supplied
clocks. All the clocks supplied are obtained and enabled using the
devm_clk_bulk_get_all_enable() API.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240220084046.23786-3-shradha.t@samsung.com
Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2024-05-28 11:15:01 -05:00
Niklas Cassel
045fda2535 PCI: dra7xx: Fix dra7xx_pcie_cpu_addr_fixup() parameter name
The function pointer declaration for the cpu_addr_fixup() callback uses
"cpu_addr" as parameter name.

Likewise, the argument that is supplied to the function pointer when the
function is actually called is "cpu_addr".

Rename the dra7xx_pcie_cpu_addr_fixup() function parameter name to match
reality.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240430071054.248008-3-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-05-28 11:14:42 -05:00
Niklas Cassel
7903ffa440 PCI: artpec6: Fix artpec6_pcie_cpu_addr_fixup() parameter name
The function pointer declaration for the cpu_addr_fixup() callback uses
"cpu_addr" as parameter name.

Likewise, the argument that is supplied to the function pointer when the
function is actually called is "cpu_addr".

Rename the artpec6_pcie_cpu_addr_fixup() parameter name to match
reality.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240430071054.248008-4-cassel@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
2024-05-28 11:14:35 -05:00
Aleksandr Mishin
a9927c2cac PCI: al: Check IORESOURCE_BUS existence during probe
If IORESOURCE_BUS is not provided in Device Tree it will be fabricated in
of_pci_parse_bus_range(), so NULL pointer dereference should not happen
here.

But that's hard to verify, so check for NULL anyway.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Link: https://lore.kernel.org/linux-pci/20240503125705.46055-1-amishin@t-argos.ru
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Aleksandr Mishin <amishin@t-argos.ru>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-05-28 11:14:24 -05:00
Manivannan Sadhasivam
f58838d7fe PCI: endpoint: Rename BME to Bus Master Enable
BME which stands for 'Bus Master Enable' is not defined in the PCIe base
spec even though it is commonly referred in many places (vendor docs).  To
align with the spec, rename it to its expansion 'Bus Master Enable'.

Suggested-by: Damien Le Moal <dlemoal@kernel.org>
Link: https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-3-22832d0d456f@linaro.org
Link: https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-4-22832d0d456f@linaro.org
Tested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
[bhelgaas: squash removal of irrelevant 'Link is enabled']
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
2024-05-28 11:13:48 -05:00
Mrinmay Sarkar
c94391ba52 PCI: qcom-ep: Add HDMA support for SA8775P SoC
SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP,
so add support for it by passing the mapping format and the number of
read/write channels count.

The PCIe EP controller used on this SoC is of version 1.34.0, so a separate
config struct is introduced for the sake of enabling HDMA conditionally.

It should be noted that for the eDMA support (predecessor of HDMA), there
are no mapping format and channels count specified. That is because eDMA
supports auto detection of both parameters, whereas HDMA doesn't.

[mani: reworded commit message, added kdoc, and minor cleanups]
Link: https://lore.kernel.org/linux-pci/20240318-dw-hdma-v5-4-f04c5cdde760@linaro.org
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2024-05-28 09:51:17 -05:00
Manivannan Sadhasivam
0551abf219 PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers
Instead of maintaining a separate capability for glue drivers that cannot
support auto detection of the eDMA mapping format, pass the mapping format
directly from them.

This will simplify the code and also allow adding HDMA support that also
doesn't support auto detection of mapping format.

Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/linux-pci/20240318-dw-hdma-v5-3-f04c5cdde760@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2024-05-28 09:51:17 -05:00
Manivannan Sadhasivam
0d278fbdb4 PCI: dwc: Skip finding eDMA channels count for HDMA platforms
In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way
the drivers can auto detect the number of read/write channels as like its
predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA
have to pass the channels count during probe.

To accommodate that, skip the existing auto detection of channels count
procedure for HDMA based platforms. If the channels count passed by the
glue drivers were wrong in any form, then the existing sanity check will
catch it.

Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/linux-pci/20240318-dw-hdma-v5-2-f04c5cdde760@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2024-05-28 09:51:17 -05:00