2 Commits

Author	SHA1	Message	Date
Srikanth, Jampala	7a027b57f9	crypto: cavium/nitrox - Enable interrups for PF in SR-IOV mode. ... Enable the available interrupt vectors for PF in SR-IOV Mode. Only single vector entry 192 is valid of PF. This is used to notify any hardware errors and mailbox messages from VF(s). Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>	2018-11-29 16:27:04 +08:00
Srikanth Jampala	5155e118dd	crypto: cavium/nitrox - use pci_alloc_irq_vectors() while enabling MSI-X. ... replace pci_enable_msix_exact() with pci_alloc_irq_vectors(). get the required vector count from pci_msix_vec_count(). use struct nitrox_q_vector as the argument to tasklets. Signed-off-by: Srikanth Jampala <Jampala.Srikanth@cavium.com> Reviewed-by: Gadam Sreerama <sgadam@cavium.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>	2018-10-05 10:22:48 +08:00