5 Commits

Author	SHA1	Message	Date
Kai Ye	07a4356baf	crypto: hisilicon/sec - use the correct print format ... According to Documentation/core-api/printk-formats.rst, Use the correct print format. Printing an unsigned int value should use %u instead of %d. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>	2021-04-16 21:16:33 +10:00
Hao Fang	5377265f54	crypto: hisilicon - use the correct HiSilicon copyright ... s/Hisilicon/HiSilicon/g, according to https://www.hisilicon.com/en/terms-of-use. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>	2021-04-02 18:28:12 +11:00
Lee Jones	45394566b0	crypto: hisilicon/sec - Supply missing description for 'sec_queue_empty()'s 'queue' param ... Fixes the following W=1 kernel build warning(s): drivers/crypto/hisilicon/sec/sec_drv.c:843: warning: Function parameter or member 'queue' not described in 'sec_queue_empty' Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: Zaibo Xu <xuzaibo@huawei.com> Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Cc: linux-crypto@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>	2021-03-26 20:02:35 +11:00
Luis Chamberlain	750afb08ca	cross-tree: phase out dma_zalloc_coherent() ... We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>	2019-01-08 07:58:37 -05:00
Jonathan Cameron	915e4e8413	crypto: hisilicon - SEC security accelerator driver ... This accelerator is found inside hisilicon hip06 and hip07 SoCs. Each instance provides a number of queues which feed a different number of backend acceleration units. The queues are operating in an out of order mode in the interests of throughput. The silicon does not do tracking of dependencies between multiple 'messages' or update of the IVs as appropriate for training. Hence where relevant we need to do this in software. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>	2018-08-03 18:06:02 +08:00