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perf amd ibs: Incorporate Zen5 DTLB and PageSize information
IBS Op PMU on Zen5 reports DTLB and page size information differently
compared to prior generation.
IBS_OP_DATA3 Zen3/4 Zen5
----------------------------------------------------------------
19 IbsDcL2TlbHit1G Reserved
----------------------------------------------------------------
6 IbsDcL2tlbHit2M Reserved
----------------------------------------------------------------
5 IbsDcL1TlbHit1G PageSize:
4 IbsDcL1TlbHit2M 0 - 4K
1 - 2M
2 - 1G
3 - Reserved
Valid only if
IbsDcPhyAddrValid = 1
----------------------------------------------------------------
3 IbsDcL2TlbMiss IbsDcL2TlbMiss
Valid only if
IbsDcPhyAddrValid = 1
----------------------------------------------------------------
2 IbsDcL1tlbMiss IbsDcL1tlbMiss
Valid only if
IbsDcPhyAddrValid = 1
----------------------------------------------------------------
Kernel expose this change as "dtlb_pgsize" capability in PMU sysfs.
Change IBS register raw-dump logic according to new bit definitions.
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Joe Mario <jmario@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Santosh Shukla <santosh.shukla@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20250429035938.1301-3-ravi.bangoria@amd.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ravi Bangoria
Arnaldo Carvalho de Melo
parent
eeefc13c71
commit
fc481adc97
@ -20,6 +20,7 @@
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static u32 cpu_family, cpu_model, ibs_fetch_type, ibs_op_type;
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static bool zen4_ibs_extensions;
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static bool ldlat_cap;
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static bool dtlb_pgsize_cap;
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static void pr_ibs_fetch_ctl(union ibs_fetch_ctl reg)
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{
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@ -161,9 +162,20 @@ static void pr_ibs_op_data2(union ibs_op_data2 reg)
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static void pr_ibs_op_data3(union ibs_op_data3 reg)
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{
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char l2_miss_str[sizeof(" L2Miss _")] = "";
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char op_mem_width_str[sizeof(" OpMemWidth _____ bytes")] = "";
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static const char * const dc_page_sizes[] = {
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" 4K",
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" 2M",
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" 1G",
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" ??",
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};
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char op_dc_miss_open_mem_reqs_str[sizeof(" OpDcMissOpenMemReqs __")] = "";
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char dc_l1_l2tlb_miss_str[sizeof(" DcL1TlbMiss _ DcL2TlbMiss _")] = "";
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char dc_l1tlb_hit_str[sizeof(" DcL1TlbHit2M _ DcL1TlbHit1G _")] = "";
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char op_mem_width_str[sizeof(" OpMemWidth _____ bytes")] = "";
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char dc_l2tlb_hit_2m_str[sizeof(" DcL2TlbHit2M _")] = "";
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char dc_l2tlb_hit_1g_str[sizeof(" DcL2TlbHit1G _")] = "";
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char dc_page_size_str[sizeof(" DcPageSize ____")] = "";
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char l2_miss_str[sizeof(" L2Miss _")] = "";
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/*
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* Erratum #1293
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@ -179,16 +191,40 @@ static void pr_ibs_op_data3(union ibs_op_data3 reg)
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snprintf(op_mem_width_str, sizeof(op_mem_width_str),
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" OpMemWidth %2d bytes", 1 << (reg.op_mem_width - 1));
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printf("ibs_op_data3:\t%016llx LdOp %d StOp %d DcL1TlbMiss %d DcL2TlbMiss %d "
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"DcL1TlbHit2M %d DcL1TlbHit1G %d DcL2TlbHit2M %d DcMiss %d DcMisAcc %d "
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"DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d DcLinAddrValid %d "
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"DcPhyAddrValid %d DcL2TlbHit1G %d%s SwPf %d%s%s DcMissLat %5d TlbRefillLat %5d\n",
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reg.val, reg.ld_op, reg.st_op, reg.dc_l1tlb_miss, reg.dc_l2tlb_miss,
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reg.dc_l1tlb_hit_2m, reg.dc_l1tlb_hit_1g, reg.dc_l2tlb_hit_2m, reg.dc_miss,
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reg.dc_mis_acc, reg.dc_wc_mem_acc, reg.dc_uc_mem_acc, reg.dc_locked_op,
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reg.dc_miss_no_mab_alloc, reg.dc_lin_addr_valid, reg.dc_phy_addr_valid,
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reg.dc_l2_tlb_hit_1g, l2_miss_str, reg.sw_pf, op_mem_width_str,
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op_dc_miss_open_mem_reqs_str, reg.dc_miss_lat, reg.tlb_refill_lat);
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if (dtlb_pgsize_cap) {
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if (reg.dc_phy_addr_valid) {
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int idx = (reg.dc_l1tlb_hit_1g << 1) | reg.dc_l1tlb_hit_2m;
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snprintf(dc_l1_l2tlb_miss_str, sizeof(dc_l1_l2tlb_miss_str),
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" DcL1TlbMiss %d DcL2TlbMiss %d",
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reg.dc_l1tlb_miss, reg.dc_l2tlb_miss);
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snprintf(dc_page_size_str, sizeof(dc_page_size_str),
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" DcPageSize %4s", dc_page_sizes[idx]);
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}
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} else {
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snprintf(dc_l1_l2tlb_miss_str, sizeof(dc_l1_l2tlb_miss_str),
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" DcL1TlbMiss %d DcL2TlbMiss %d",
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reg.dc_l1tlb_miss, reg.dc_l2tlb_miss);
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snprintf(dc_l1tlb_hit_str, sizeof(dc_l1tlb_hit_str),
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" DcL1TlbHit2M %d DcL1TlbHit1G %d",
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reg.dc_l1tlb_hit_2m, reg.dc_l1tlb_hit_1g);
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snprintf(dc_l2tlb_hit_2m_str, sizeof(dc_l2tlb_hit_2m_str),
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" DcL2TlbHit2M %d", reg.dc_l2tlb_hit_2m);
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snprintf(dc_l2tlb_hit_1g_str, sizeof(dc_l2tlb_hit_1g_str),
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" DcL2TlbHit1G %d", reg.dc_l2_tlb_hit_1g);
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}
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printf("ibs_op_data3:\t%016llx LdOp %d StOp %d%s%s%s DcMiss %d DcMisAcc %d "
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"DcWcMemAcc %d DcUcMemAcc %d DcLockedOp %d DcMissNoMabAlloc %d "
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"DcLinAddrValid %d DcPhyAddrValid %d%s%s SwPf %d%s%s "
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"DcMissLat %5d TlbRefillLat %5d\n",
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reg.val, reg.ld_op, reg.st_op, dc_l1_l2tlb_miss_str,
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dtlb_pgsize_cap ? dc_page_size_str : dc_l1tlb_hit_str,
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dc_l2tlb_hit_2m_str, reg.dc_miss, reg.dc_mis_acc, reg.dc_wc_mem_acc,
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reg.dc_uc_mem_acc, reg.dc_locked_op, reg.dc_miss_no_mab_alloc,
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reg.dc_lin_addr_valid, reg.dc_phy_addr_valid, dc_l2tlb_hit_1g_str,
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l2_miss_str, reg.sw_pf, op_mem_width_str, op_dc_miss_open_mem_reqs_str,
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reg.dc_miss_lat, reg.tlb_refill_lat);
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}
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/*
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@ -341,6 +377,9 @@ bool evlist__has_amd_ibs(struct evlist *evlist)
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if (perf_env__find_pmu_cap(env, "ibs_op", "ldlat"))
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ldlat_cap = 1;
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if (perf_env__find_pmu_cap(env, "ibs_op", "dtlb_pgsize"))
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dtlb_pgsize_cap = 1;
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if (ibs_fetch_type || ibs_op_type) {
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if (!cpu_family)
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parse_cpuid(env);
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