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drm/amdgpu: GPU vm support 5-level page table

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If GPU supports 5-level page table, but CPU disable 5-level page table
by using boot option no5lvl or CPU feature not available, the virtual
address will be 48bit, not needed to enable 5-level page table on GPU
vm.

If adev->vm_manager.num_level, number of pde levels, set to 4, then
gfxhub and mmhub register VM_CONTEXTx_CNTL/PAGE_TABLE_DEPTH will set
to 4 to enable 5-level page table in page table walker.

Set vm_manager.root_level to AMDGPU_VM_PDE3, then update GPU mapping
will allocate and update PDE3/PDE2/PDE1/PDE0/PTB 5-level page tables.

If max_level is not 4, no change for the logic to support features
needed by old ASICs.

v2: squash in CONFIG fix

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Philip Yang
2025-04-25 10:55:07 -04:00
committed by Alex Deucher
parent bc5094e27e
commit f6b1c1f5fd
3 changed files with 23 additions and 1 deletions
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20
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
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@@ -2360,9 +2360,26 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
unsigned max_bits)
{
unsigned int max_size = 1 << (max_bits - 30);
bool sys_5level_pgtable = false;
unsigned int vm_size;
uint64_t tmp;
#ifdef CONFIG_X86_64
/*
* Refer to function configure_5level_paging() for details.
*/
sys_5level_pgtable = (native_read_cr4() & X86_CR4_LA57);
#endif
/*
* If GPU supports 5-level page table, but system uses 4-level page table,
* then use 4-level page table on GPU
*/
if (max_level == 4 && !sys_5level_pgtable) {
min_vm_size = 256 * 1024;
max_level = 3;
}
/* adjust vm size first */
if (amdgpu_vm_size != -1) {
vm_size = amdgpu_vm_size;
@@ -2405,6 +2422,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
switch (adev->vm_manager.num_level) {
case 4:
adev->vm_manager.root_level = AMDGPU_VM_PDB3;
break;
case 3:
adev->vm_manager.root_level = AMDGPU_VM_PDB2;
break;