mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Samsung pinctrl drivers changes for v6.15
1. Add pin controller drivers for newly usptreamed Samsung Exynos2200 and Exynos7870. 2. Correct filter configuration offset of some of Google GS101 SoC pin banks, which later is supposed to be used during system suspend/resume. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmfW4GQQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD13QSEACYr14mY3bEzRDyxchkOiwi50uNgieKCI2/ JQIEs/TtGqDAlvwN+OODkyIKzwyc0PDkbKGBP/kUOblHr/4i9H06dT653d8mgzkZ Kkoe9SLeniW717YCS9N5vrZOYmQNIqYA0rEHFO5G45fAWQCNomFjrbtakkdG4Zx3 jEEGoxFygR4Pu4vymEYhdzX8W3KgcqNQEwxf6gN+HOM18DNq/0zW6lcP6Pe66eaR 3VcoyvaU7B8UAJOLecOwKOfcCc1g32+hBkWuLHsSwcky8yK/Nt6sW7xbeUflcEwU XYJeqv9B4OzPHNiTVovAgBw/ZRcv1x4jeajqI0+pU22JZj80orI+lzQEBpjRpUmh u6g/e8K9Y/66Xnyt/T5fvTWlkOkSWZh0tL3aqcS6JJ/7RNFB9FBaClydlyEAprhs UZ1ACsX9xZz+XeKIL864zQlUa/lKJWcS+bzviuqB83Kqtwqv6tW2ijReco87MIaf jeP6IGlFFotLofCfphbLn8ppuiG+r+1aZKfZryMurL27KM4LL/cffWTYxyvgOjZs IoxIfZaXtJrJk7B7U5mmajMziT7Mzly7fQIuTDmlSWNnxi7xklCkvLFzW//r4341 2jFjIsX3avNzsckq3laJtLX36w5oOlv1V8RIdWOOE4YlsBZhIXEZj2HIznPhdnCd 2MccU8vOrg== =H+LK -----END PGP SIGNATURE----- Merge tag 'samsung-pinctrl-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.15 1. Add pin controller drivers for newly usptreamed Samsung Exynos2200 and Exynos7870. 2. Correct filter configuration offset of some of Google GS101 SoC pin banks, which later is supposed to be used during system suspend/resume. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
commit
eb8578843f
@ -40,6 +40,7 @@ properties:
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|||||||
- items:
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- items:
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- enum:
|
- enum:
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||||||
- samsung,exynos5433-wakeup-eint
|
- samsung,exynos5433-wakeup-eint
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||||||
|
- samsung,exynos7870-wakeup-eint
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||||||
- samsung,exynos7885-wakeup-eint
|
- samsung,exynos7885-wakeup-eint
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||||||
- samsung,exynos850-wakeup-eint
|
- samsung,exynos850-wakeup-eint
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- samsung,exynos8895-wakeup-eint
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- samsung,exynos8895-wakeup-eint
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@ -47,6 +48,7 @@ properties:
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- items:
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- items:
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- enum:
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- enum:
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- google,gs101-wakeup-eint
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- google,gs101-wakeup-eint
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- samsung,exynos2200-wakeup-eint
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- samsung,exynos9810-wakeup-eint
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- samsung,exynos9810-wakeup-eint
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- samsung,exynos990-wakeup-eint
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- samsung,exynos990-wakeup-eint
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- samsung,exynosautov9-wakeup-eint
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- samsung,exynosautov9-wakeup-eint
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@ -104,6 +106,7 @@ allOf:
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- contains:
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- contains:
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enum:
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enum:
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- samsung,exynos5433-wakeup-eint
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- samsung,exynos5433-wakeup-eint
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- samsung,exynos7870-wakeup-eint
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- samsung,exynos7885-wakeup-eint
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- samsung,exynos7885-wakeup-eint
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- samsung,exynos8895-wakeup-eint
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- samsung,exynos8895-wakeup-eint
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then:
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then:
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@ -42,6 +42,7 @@ properties:
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- samsung,s3c2450-pinctrl
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- samsung,s3c2450-pinctrl
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- samsung,s3c64xx-pinctrl
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- samsung,s3c64xx-pinctrl
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- samsung,s5pv210-pinctrl
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- samsung,s5pv210-pinctrl
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- samsung,exynos2200-pinctrl
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- samsung,exynos3250-pinctrl
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- samsung,exynos3250-pinctrl
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- samsung,exynos4210-pinctrl
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- samsung,exynos4210-pinctrl
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- samsung,exynos4x12-pinctrl
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- samsung,exynos4x12-pinctrl
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@ -51,6 +52,7 @@ properties:
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- samsung,exynos5420-pinctrl
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- samsung,exynos5420-pinctrl
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- samsung,exynos5433-pinctrl
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- samsung,exynos5433-pinctrl
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- samsung,exynos7-pinctrl
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- samsung,exynos7-pinctrl
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- samsung,exynos7870-pinctrl
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- samsung,exynos7885-pinctrl
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- samsung,exynos7885-pinctrl
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- samsung,exynos850-pinctrl
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- samsung,exynos850-pinctrl
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- samsung,exynos8895-pinctrl
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- samsung,exynos8895-pinctrl
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@ -40,6 +40,15 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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};
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/*
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* Bank type for alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 2, DRV: 3
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*/
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static const struct samsung_pin_bank_type exynos7870_bank_type_alive = {
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.fld_width = { 4, 1, 2, 3, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/*
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/*
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* Bank type for non-alive type. Bit fields:
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* Bank type for non-alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
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* CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
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@ -70,6 +79,174 @@ static const struct samsung_pin_bank_type exynos8895_bank_type_off = {
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/* Pad retention control code for accessing PMU regmap */
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/* Pad retention control code for accessing PMU regmap */
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static atomic_t exynos_shared_retention_refcnt;
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static atomic_t exynos_shared_retention_refcnt;
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/* pin banks of exynos2200 pin-controller - ALIVE */
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static const struct samsung_pin_bank_data exynos2200_pin_banks0[] __initconst = {
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EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(8, 0x20, "gpa1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(8, 0x60, "gpa3", 0x0c),
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EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpa4", 0x10),
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EXYNOS_PIN_BANK_EINTN(4, 0xa0, "gpq0"),
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EXYNOS_PIN_BANK_EINTN(2, 0xc0, "gpq1"),
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EXYNOS_PIN_BANK_EINTN(2, 0xe0, "gpq2"),
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};
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/* pin banks of exynos2200 pin-controller - CMGP */
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static const struct samsung_pin_bank_data exynos2200_pin_banks1[] __initconst = {
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EXYNOS850_PIN_BANK_EINTW(2, 0x0, "gpm0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(2, 0x20, "gpm1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(2, 0x40, "gpm2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpm3", 0x0c),
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EXYNOS850_PIN_BANK_EINTW(2, 0x80, "gpm4", 0x10),
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EXYNOS850_PIN_BANK_EINTW(2, 0xa0, "gpm5", 0x14),
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EXYNOS850_PIN_BANK_EINTW(2, 0xc0, "gpm6", 0x18),
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EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpm7", 0x1c),
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EXYNOS850_PIN_BANK_EINTW(2, 0x100, "gpm8", 0x20),
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EXYNOS850_PIN_BANK_EINTW(2, 0x120, "gpm9", 0x24),
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EXYNOS850_PIN_BANK_EINTW(2, 0x140, "gpm10", 0x28),
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EXYNOS850_PIN_BANK_EINTW(2, 0x160, "gpm11", 0x2c),
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EXYNOS850_PIN_BANK_EINTW(2, 0x180, "gpm12", 0x30),
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EXYNOS850_PIN_BANK_EINTW(2, 0x1a0, "gpm13", 0x34),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1c0, "gpm14", 0x38),
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EXYNOS850_PIN_BANK_EINTW(1, 0x1e0, "gpm15", 0x3c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40),
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EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44),
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EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm20", 0x48),
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EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm21", 0x4c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm22", 0x50),
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EXYNOS850_PIN_BANK_EINTW(1, 0x2a0, "gpm23", 0x54),
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EXYNOS850_PIN_BANK_EINTW(1, 0x2c0, "gpm24", 0x58),
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};
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/* pin banks of exynos2200 pin-controller - HSI1 */
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static const struct samsung_pin_bank_data exynos2200_pin_banks2[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpf0", 0x00),
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};
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/* pin banks of exynos2200 pin-controller - UFS */
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static const struct samsung_pin_bank_data exynos2200_pin_banks3[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpf1", 0x00),
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};
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/* pin banks of exynos2200 pin-controller - HSI1UFS */
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static const struct samsung_pin_bank_data exynos2200_pin_banks4[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gpf2", 0x00),
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};
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/* pin banks of exynos2200 pin-controller - PERIC0 */
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static const struct samsung_pin_bank_data exynos2200_pin_banks5[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpb0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpb1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpb2", 0x08),
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EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpb3", 0x0c),
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EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
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EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpc0", 0x14),
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EXYNOS850_PIN_BANK_EINTG(2, 0xc0, "gpc1", 0x18),
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EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc2", 0x1c),
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EXYNOS850_PIN_BANK_EINTG(7, 0x100, "gpg1", 0x20),
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EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpg2", 0x24),
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};
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/* pin banks of exynos2200 pin-controller - PERIC1 */
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static const struct samsung_pin_bank_data exynos2200_pin_banks6[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp7", 0x00),
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EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp8", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp9", 0x08),
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EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp10", 0x0c),
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};
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/* pin banks of exynos2200 pin-controller - PERIC2 */
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static const struct samsung_pin_bank_data exynos2200_pin_banks7[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(4, 0x0, "gpp0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
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EXYNOS850_PIN_BANK_EINTG(4, 0x60, "gpp3", 0x0c),
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EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp5", 0x10),
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EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp6", 0x14),
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EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp11", 0x18),
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EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpc3", 0x1c),
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EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpc4", 0x20),
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EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpc5", 0x24),
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EXYNOS850_PIN_BANK_EINTG(2, 0x140, "gpc6", 0x28),
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EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpc7", 0x2c),
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EXYNOS850_PIN_BANK_EINTG(2, 0x180, "gpc8", 0x30),
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EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpc9", 0x34),
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EXYNOS850_PIN_BANK_EINTG(5, 0x1c0, "gpg0", 0x38),
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};
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/* pin banks of exynos2200 pin-controller - VTS */
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static const struct samsung_pin_bank_data exynos2200_pin_banks8[] __initconst = {
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EXYNOS850_PIN_BANK_EINTG(7, 0x0, "gpv0", 0x00),
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};
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static const struct samsung_pin_ctrl exynos2200_pin_ctrl[] = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynos2200_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos2200_pin_banks0),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 1 CMGP data */
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.pin_banks = exynos2200_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos2200_pin_banks1),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 2 HSI1 data */
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.pin_banks = exynos2200_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos2200_pin_banks2),
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}, {
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/* pin-controller instance 3 UFS data */
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.pin_banks = exynos2200_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos2200_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 4 HSI1UFS data */
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.pin_banks = exynos2200_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos2200_pin_banks4),
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|
.eint_gpio_init = exynos_eint_gpio_init,
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|
.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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}, {
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/* pin-controller instance 5 PERIC0 data */
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.pin_banks = exynos2200_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos2200_pin_banks5),
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|
.eint_gpio_init = exynos_eint_gpio_init,
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.suspend = exynos_pinctrl_suspend,
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.resume = exynos_pinctrl_resume,
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|
}, {
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|
/* pin-controller instance 6 PERIC1 data */
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|
.pin_banks = exynos2200_pin_banks6,
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|
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks6),
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||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
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|
.suspend = exynos_pinctrl_suspend,
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|
.resume = exynos_pinctrl_resume,
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|
}, {
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|
/* pin-controller instance 7 PERIC2 data */
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|
.pin_banks = exynos2200_pin_banks7,
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|
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks7),
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||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
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|
.suspend = exynos_pinctrl_suspend,
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|
.resume = exynos_pinctrl_resume,
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|
}, {
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|
/* pin-controller instance 8 VTS data */
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|
.pin_banks = exynos2200_pin_banks8,
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|
.nr_banks = ARRAY_SIZE(exynos2200_pin_banks8),
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|
},
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|
};
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|
|
||||||
|
const struct samsung_pinctrl_of_match_data exynos2200_of_data __initconst = {
|
||||||
|
.ctrl = exynos2200_pin_ctrl,
|
||||||
|
.num_ctrl = ARRAY_SIZE(exynos2200_pin_ctrl),
|
||||||
|
};
|
||||||
|
|
||||||
/* pin banks of exynos5433 pin-controller - ALIVE */
|
/* pin banks of exynos5433 pin-controller - ALIVE */
|
||||||
static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
|
static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
|
||||||
/* Must start with EINTG banks, ordered by EINT group number. */
|
/* Must start with EINTG banks, ordered by EINT group number. */
|
||||||
@ -450,6 +627,136 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
|
|||||||
.num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
|
.num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 0 (ALIVE) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks0[] __initconst = {
|
||||||
|
EXYNOS7870_PIN_BANK_EINTN(6, 0x000, "etc0"),
|
||||||
|
EXYNOS7870_PIN_BANK_EINTN(3, 0x020, "etc1"),
|
||||||
|
EXYNOS7870_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00),
|
||||||
|
EXYNOS7870_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04),
|
||||||
|
EXYNOS7870_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08),
|
||||||
|
EXYNOS7870_PIN_BANK_EINTN(2, 0x0c0, "gpq0"),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 1 (DISPAUD) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks1[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpz0", 0x00),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(6, 0x020, "gpz1", 0x04),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpz2", 0x08),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 2 (ESE) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks2[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(5, 0x000, "gpc7", 0x00),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 3 (FSYS) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks3[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpr0", 0x00),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x040, "gpr2", 0x08),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpr3", 0x0c),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(6, 0x080, "gpr4", 0x10),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 4 (MIF) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks4[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x000, "gpm0", 0x00),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 5 (NFC) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks5[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpc2", 0x00),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 6 (TOP) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks6[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x000, "gpb0", 0x00),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(3, 0x020, "gpc0", 0x04),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x040, "gpc1", 0x08),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x060, "gpc4", 0x0c),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x080, "gpc5", 0x10),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x0a0, "gpc6", 0x14),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x0c0, "gpc8", 0x18),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x0e0, "gpc9", 0x1c),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(7, 0x100, "gpd1", 0x20),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(6, 0x120, "gpd2", 0x24),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(8, 0x140, "gpd3", 0x28),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(7, 0x160, "gpd4", 0x2c),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(3, 0x1a0, "gpe0", 0x34),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x1e0, "gpf1", 0x3c),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(2, 0x200, "gpf2", 0x40),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(4, 0x220, "gpf3", 0x44),
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(5, 0x240, "gpf4", 0x48),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* pin banks of exynos7870 pin-controller 7 (TOUCH) */
|
||||||
|
static const struct samsung_pin_bank_data exynos7870_pin_banks7[] __initconst = {
|
||||||
|
EXYNOS8895_PIN_BANK_EINTG(3, 0x000, "gpc3", 0x00),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct samsung_pin_ctrl exynos7870_pin_ctrl[] __initconst = {
|
||||||
|
{
|
||||||
|
/* pin-controller instance 0 Alive data */
|
||||||
|
.pin_banks = exynos7870_pin_banks0,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks0),
|
||||||
|
.eint_wkup_init = exynos_eint_wkup_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 1 DISPAUD data */
|
||||||
|
.pin_banks = exynos7870_pin_banks1,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks1),
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 2 ESE data */
|
||||||
|
.pin_banks = exynos7870_pin_banks2,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks2),
|
||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 3 FSYS data */
|
||||||
|
.pin_banks = exynos7870_pin_banks3,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks3),
|
||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 4 MIF data */
|
||||||
|
.pin_banks = exynos7870_pin_banks4,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks4),
|
||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 5 NFC data */
|
||||||
|
.pin_banks = exynos7870_pin_banks5,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks5),
|
||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 6 TOP data */
|
||||||
|
.pin_banks = exynos7870_pin_banks6,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks6),
|
||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
}, {
|
||||||
|
/* pin-controller instance 7 TOUCH data */
|
||||||
|
.pin_banks = exynos7870_pin_banks7,
|
||||||
|
.nr_banks = ARRAY_SIZE(exynos7870_pin_banks7),
|
||||||
|
.eint_gpio_init = exynos_eint_gpio_init,
|
||||||
|
.suspend = exynos_pinctrl_suspend,
|
||||||
|
.resume = exynos_pinctrl_resume,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct samsung_pinctrl_of_match_data exynos7870_of_data __initconst = {
|
||||||
|
.ctrl = exynos7870_pin_ctrl,
|
||||||
|
.num_ctrl = ARRAY_SIZE(exynos7870_pin_ctrl),
|
||||||
|
};
|
||||||
|
|
||||||
/* pin banks of exynos7885 pin-controller 0 (ALIVE) */
|
/* pin banks of exynos7885 pin-controller 0 (ALIVE) */
|
||||||
static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
|
static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
|
||||||
EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),
|
EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),
|
||||||
@ -1370,83 +1677,83 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
|
|||||||
|
|
||||||
/* pin banks of gs101 pin-controller (ALIVE) */
|
/* pin banks of gs101 pin-controller (ALIVE) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_alive[] = {
|
static const struct samsung_pin_bank_data gs101_pin_alive[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
|
GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),
|
GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08),
|
||||||
EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),
|
GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10),
|
||||||
EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),
|
GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18),
|
||||||
EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),
|
GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c),
|
||||||
EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),
|
GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20),
|
||||||
EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),
|
GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28),
|
||||||
EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),
|
GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
|
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
|
static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),
|
GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),
|
GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08),
|
||||||
EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),
|
GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c),
|
||||||
EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),
|
GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (GSACORE) */
|
/* pin banks of gs101 pin-controller (GSACORE) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
|
static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),
|
GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),
|
GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04),
|
||||||
EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),
|
GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (GSACTRL) */
|
/* pin banks of gs101 pin-controller (GSACTRL) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
|
static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),
|
GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (PERIC0) */
|
/* pin banks of gs101 pin-controller (PERIC0) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
|
static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),
|
GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
|
GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
|
GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),
|
GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
|
GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),
|
GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),
|
GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),
|
GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),
|
GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),
|
GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),
|
GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),
|
GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),
|
GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),
|
GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),
|
GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),
|
GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),
|
GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),
|
GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),
|
GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),
|
GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (PERIC1) */
|
/* pin banks of gs101 pin-controller (PERIC1) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
|
static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),
|
GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),
|
GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),
|
GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),
|
GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),
|
GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),
|
GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c),
|
||||||
EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),
|
GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20),
|
||||||
EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),
|
GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (HSI1) */
|
/* pin banks of gs101 pin-controller (HSI1) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
|
static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),
|
GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),
|
GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08),
|
||||||
};
|
};
|
||||||
|
|
||||||
/* pin banks of gs101 pin-controller (HSI2) */
|
/* pin banks of gs101 pin-controller (HSI2) */
|
||||||
static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
|
static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
|
||||||
EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),
|
GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00),
|
||||||
EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),
|
GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08),
|
||||||
EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),
|
GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c),
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
|
static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
|
||||||
|
@ -112,6 +112,25 @@
|
|||||||
.pctl_res_idx = pctl_idx, \
|
.pctl_res_idx = pctl_idx, \
|
||||||
} \
|
} \
|
||||||
|
|
||||||
|
#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \
|
||||||
|
{ \
|
||||||
|
.type = &exynos7870_bank_type_alive, \
|
||||||
|
.pctl_offset = reg, \
|
||||||
|
.nr_pins = pins, \
|
||||||
|
.eint_type = EINT_TYPE_NONE, \
|
||||||
|
.name = id \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \
|
||||||
|
{ \
|
||||||
|
.type = &exynos7870_bank_type_alive, \
|
||||||
|
.pctl_offset = reg, \
|
||||||
|
.nr_pins = pins, \
|
||||||
|
.eint_type = EINT_TYPE_WKUP, \
|
||||||
|
.eint_offset = offs, \
|
||||||
|
.name = id \
|
||||||
|
}
|
||||||
|
|
||||||
#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
|
#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
|
||||||
{ \
|
{ \
|
||||||
.type = &exynos850_bank_type_alive, \
|
.type = &exynos850_bank_type_alive, \
|
||||||
@ -175,6 +194,28 @@
|
|||||||
.name = id \
|
.name = id \
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
|
||||||
|
{ \
|
||||||
|
.type = &exynos850_bank_type_off, \
|
||||||
|
.pctl_offset = reg, \
|
||||||
|
.nr_pins = pins, \
|
||||||
|
.eint_type = EINT_TYPE_GPIO, \
|
||||||
|
.eint_offset = offs, \
|
||||||
|
.eint_fltcon_offset = fltcon_offs, \
|
||||||
|
.name = id \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
|
||||||
|
{ \
|
||||||
|
.type = &exynos850_bank_type_alive, \
|
||||||
|
.pctl_offset = reg, \
|
||||||
|
.nr_pins = pins, \
|
||||||
|
.eint_type = EINT_TYPE_WKUP, \
|
||||||
|
.eint_offset = offs, \
|
||||||
|
.eint_fltcon_offset = fltcon_offs, \
|
||||||
|
.name = id \
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
|
* struct exynos_weint_data: irq specific data for all the wakeup interrupts
|
||||||
* generated by the external wakeup interrupt controller.
|
* generated by the external wakeup interrupt controller.
|
||||||
|
@ -1230,6 +1230,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
|
|||||||
bank->eint_con_offset = bdata->eint_con_offset;
|
bank->eint_con_offset = bdata->eint_con_offset;
|
||||||
bank->eint_mask_offset = bdata->eint_mask_offset;
|
bank->eint_mask_offset = bdata->eint_mask_offset;
|
||||||
bank->eint_pend_offset = bdata->eint_pend_offset;
|
bank->eint_pend_offset = bdata->eint_pend_offset;
|
||||||
|
bank->eint_fltcon_offset = bdata->eint_fltcon_offset;
|
||||||
bank->name = bdata->name;
|
bank->name = bdata->name;
|
||||||
|
|
||||||
raw_spin_lock_init(&bank->slock);
|
raw_spin_lock_init(&bank->slock);
|
||||||
@ -1469,10 +1470,14 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
|
|||||||
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
|
#ifdef CONFIG_PINCTRL_EXYNOS_ARM64
|
||||||
{ .compatible = "google,gs101-pinctrl",
|
{ .compatible = "google,gs101-pinctrl",
|
||||||
.data = &gs101_of_data },
|
.data = &gs101_of_data },
|
||||||
|
{ .compatible = "samsung,exynos2200-pinctrl",
|
||||||
|
.data = &exynos2200_of_data },
|
||||||
{ .compatible = "samsung,exynos5433-pinctrl",
|
{ .compatible = "samsung,exynos5433-pinctrl",
|
||||||
.data = &exynos5433_of_data },
|
.data = &exynos5433_of_data },
|
||||||
{ .compatible = "samsung,exynos7-pinctrl",
|
{ .compatible = "samsung,exynos7-pinctrl",
|
||||||
.data = &exynos7_of_data },
|
.data = &exynos7_of_data },
|
||||||
|
{ .compatible = "samsung,exynos7870-pinctrl",
|
||||||
|
.data = &exynos7870_of_data },
|
||||||
{ .compatible = "samsung,exynos7885-pinctrl",
|
{ .compatible = "samsung,exynos7885-pinctrl",
|
||||||
.data = &exynos7885_of_data },
|
.data = &exynos7885_of_data },
|
||||||
{ .compatible = "samsung,exynos850-pinctrl",
|
{ .compatible = "samsung,exynos850-pinctrl",
|
||||||
|
@ -144,6 +144,7 @@ struct samsung_pin_bank_type {
|
|||||||
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
|
* @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank.
|
||||||
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
|
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
|
||||||
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
|
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
|
||||||
|
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
|
||||||
* @name: name to be prefixed for each pin in this pin bank.
|
* @name: name to be prefixed for each pin in this pin bank.
|
||||||
*/
|
*/
|
||||||
struct samsung_pin_bank_data {
|
struct samsung_pin_bank_data {
|
||||||
@ -158,6 +159,7 @@ struct samsung_pin_bank_data {
|
|||||||
u32 eint_con_offset;
|
u32 eint_con_offset;
|
||||||
u32 eint_mask_offset;
|
u32 eint_mask_offset;
|
||||||
u32 eint_pend_offset;
|
u32 eint_pend_offset;
|
||||||
|
u32 eint_fltcon_offset;
|
||||||
const char *name;
|
const char *name;
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -175,6 +177,7 @@ struct samsung_pin_bank_data {
|
|||||||
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
|
* @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank.
|
||||||
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
|
* @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank.
|
||||||
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
|
* @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank.
|
||||||
|
* @eint_fltcon_offset: GS101 SoC-specific EINT filter config register offset.
|
||||||
* @name: name to be prefixed for each pin in this pin bank.
|
* @name: name to be prefixed for each pin in this pin bank.
|
||||||
* @id: id of the bank, propagated to the pin range.
|
* @id: id of the bank, propagated to the pin range.
|
||||||
* @pin_base: starting pin number of the bank.
|
* @pin_base: starting pin number of the bank.
|
||||||
@ -201,6 +204,7 @@ struct samsung_pin_bank {
|
|||||||
u32 eint_con_offset;
|
u32 eint_con_offset;
|
||||||
u32 eint_mask_offset;
|
u32 eint_mask_offset;
|
||||||
u32 eint_pend_offset;
|
u32 eint_pend_offset;
|
||||||
|
u32 eint_fltcon_offset;
|
||||||
const char *name;
|
const char *name;
|
||||||
u32 id;
|
u32 id;
|
||||||
|
|
||||||
@ -373,6 +377,7 @@ struct samsung_pmx_func {
|
|||||||
};
|
};
|
||||||
|
|
||||||
/* list of all exported SoC specific data */
|
/* list of all exported SoC specific data */
|
||||||
|
extern const struct samsung_pinctrl_of_match_data exynos2200_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
|
||||||
@ -382,6 +387,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
|
|||||||
extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
|
||||||
|
extern const struct samsung_pinctrl_of_match_data exynos7870_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
|
||||||
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
|
extern const struct samsung_pinctrl_of_match_data exynos8895_of_data;
|
||||||
|
Loading…
Reference in New Issue
Block a user