mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-04 20:19:47 +08:00
Merge branch 'for-6.17/amd-sfh' into for-linus
- add support for operating modes (Basavaraj Natikar)
This commit is contained in:
Jiri Kosina
commit
e9ef810dfe
31
.mailmap
31
.mailmap
@ -21,7 +21,8 @@ Adam Radford <aradford@gmail.com>
|
||||
Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
|
||||
Adrian Bunk <bunk@stusta.de>
|
||||
Ajay Kaher <ajay.kaher@broadcom.com> <akaher@vmware.com>
|
||||
Akhil P Oommen <quic_akhilpo@quicinc.com> <akhilpo@codeaurora.org>
|
||||
Akhil P Oommen <akhilpo@oss.qualcomm.com> <akhilpo@codeaurora.org>
|
||||
Akhil P Oommen <akhilpo@oss.qualcomm.com> <quic_akhilpo@quicinc.com>
|
||||
Alan Cox <alan@lxorguk.ukuu.org.uk>
|
||||
Alan Cox <root@hraefn.swansea.linux.org.uk>
|
||||
Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
|
||||
@ -106,7 +107,8 @@ Asahi Lina <lina+kernel@asahilina.net> <lina@asahilina.net>
|
||||
Ashok Raj Nagarajan <quic_arnagara@quicinc.com> <arnagara@codeaurora.org>
|
||||
Ashwin Chaugule <quic_ashwinc@quicinc.com> <ashwinc@codeaurora.org>
|
||||
Asutosh Das <quic_asutoshd@quicinc.com> <asutoshd@codeaurora.org>
|
||||
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
|
||||
Atish Patra <atish.patra@linux.dev> <atishp@atishpatra.org>
|
||||
Atish Patra <atish.patra@linux.dev> <atish.patra@wdc.com>
|
||||
Avaneesh Kumar Dwivedi <quic_akdwived@quicinc.com> <akdwived@codeaurora.org>
|
||||
Axel Dyks <xl@xlsigned.net>
|
||||
Axel Lin <axel.lin@gmail.com>
|
||||
@ -135,6 +137,7 @@ Ben Widawsky <bwidawsk@kernel.org> <benjamin.widawsky@intel.com>
|
||||
Benjamin Poirier <benjamin.poirier@gmail.com> <bpoirier@suse.de>
|
||||
Benjamin Tissoires <bentiss@kernel.org> <benjamin.tissoires@gmail.com>
|
||||
Benjamin Tissoires <bentiss@kernel.org> <benjamin.tissoires@redhat.com>
|
||||
Benno Lossin <lossin@kernel.org> <benno.lossin@proton.me>
|
||||
Bingwu Zhang <xtex@aosc.io> <xtexchooser@duck.com>
|
||||
Bingwu Zhang <xtex@aosc.io> <xtex@xtexx.eu.org>
|
||||
Bjorn Andersson <andersson@kernel.org> <bjorn@kryo.se>
|
||||
@ -194,6 +197,7 @@ Daniel Borkmann <daniel@iogearbox.net> <daniel.borkmann@tik.ee.ethz.ch>
|
||||
Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
|
||||
Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
|
||||
Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>
|
||||
Danilo Krummrich <dakr@kernel.org> <dakr@redhat.com>
|
||||
David Brownell <david-b@pacbell.net>
|
||||
David Collins <quic_collinsd@quicinc.com> <collinsd@codeaurora.org>
|
||||
David Heidelberg <david@ixit.cz> <d.okias@gmail.com>
|
||||
@ -279,6 +283,7 @@ Gustavo Padovan <gustavo@las.ic.unicamp.br>
|
||||
Gustavo Padovan <padovan@profusion.mobi>
|
||||
Hamza Mahfooz <hamzamahfooz@linux.microsoft.com> <hamza.mahfooz@amd.com>
|
||||
Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
|
||||
Hans de Goede <hansg@kernel.org> <hdegoede@redhat.com>
|
||||
Hans Verkuil <hverkuil@xs4all.nl> <hansverk@cisco.com>
|
||||
Hans Verkuil <hverkuil@xs4all.nl> <hverkuil-cisco@xs4all.nl>
|
||||
Harry Yoo <harry.yoo@oracle.com> <42.hyeyoo@gmail.com>
|
||||
@ -419,8 +424,13 @@ Krishna Manikandan <quic_mkrishn@quicinc.com> <mkrishn@codeaurora.org>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <krzysztof.kozlowski@canonical.com>
|
||||
Krzysztof Wilczyński <kwilczynski@kernel.org> <krzysztof.wilczynski@linux.com>
|
||||
Krzysztof Wilczyński <kwilczynski@kernel.org> <kw@linux.com>
|
||||
Kshitiz Godara <quic_kgodara@quicinc.com> <kgodara@codeaurora.org>
|
||||
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Kuniyuki Iwashima <kuniyu@google.com> <kuniyu@amazon.com>
|
||||
Kuniyuki Iwashima <kuniyu@google.com> <kuniyu@amazon.co.jp>
|
||||
Kuniyuki Iwashima <kuniyu@google.com> <kuni1840@gmail.com>
|
||||
Kuogee Hsieh <quic_khsieh@quicinc.com> <khsieh@codeaurora.org>
|
||||
Lee Jones <lee@kernel.org> <joneslee@google.com>
|
||||
Lee Jones <lee@kernel.org> <lee.jones@canonical.com>
|
||||
@ -461,6 +471,7 @@ Maheshwar Ajja <quic_majja@quicinc.com> <majja@codeaurora.org>
|
||||
Malathi Gottam <quic_mgottam@quicinc.com> <mgottam@codeaurora.org>
|
||||
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> <mpubbise@codeaurora.org>
|
||||
Manivannan Sadhasivam <mani@kernel.org> <manivannanece23@gmail.com>
|
||||
Manivannan Sadhasivam <mani@kernel.org> <manivannan.sadhasivam@linaro.org>
|
||||
Manoj Basapathi <quic_manojbm@quicinc.com> <manojbm@codeaurora.org>
|
||||
Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
|
||||
Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
|
||||
@ -596,6 +607,12 @@ Paul Mackerras <paulus@ozlabs.org> <paulus@samba.org>
|
||||
Paul Mackerras <paulus@ozlabs.org> <paulus@au1.ibm.com>
|
||||
Paul Moore <paul@paul-moore.com> <paul.moore@hp.com>
|
||||
Paul Moore <paul@paul-moore.com> <pmoore@redhat.com>
|
||||
Paulo Alcantara <pc@manguebit.org> <pcacjr@zytor.com>
|
||||
Paulo Alcantara <pc@manguebit.org> <paulo@paulo.ac>
|
||||
Paulo Alcantara <pc@manguebit.org> <pc@cjr.nz>
|
||||
Paulo Alcantara <pc@manguebit.org> <palcantara@suse.de>
|
||||
Paulo Alcantara <pc@manguebit.org> <palcantara@suse.com>
|
||||
Paulo Alcantara <pc@manguebit.org> <pc@manguebit.com>
|
||||
Pavankumar Kondeti <quic_pkondeti@quicinc.com> <pkondeti@codeaurora.org>
|
||||
Peter A Jonsson <pj@ludd.ltu.se>
|
||||
Peter Oruba <peter.oruba@amd.com>
|
||||
@ -636,6 +653,8 @@ Richard Genoud <richard.genoud@bootlin.com> <richard.genoud@gmail.com>
|
||||
Richard Leitner <richard.leitner@linux.dev> <dev@g0hl1n.net>
|
||||
Richard Leitner <richard.leitner@linux.dev> <me@g0hl1n.net>
|
||||
Richard Leitner <richard.leitner@linux.dev> <richard.leitner@skidata.com>
|
||||
Rob Clark <robin.clark@oss.qualcomm.com> <robdclark@chromium.org>
|
||||
Rob Clark <robin.clark@oss.qualcomm.com> <robdclark@gmail.com>
|
||||
Robert Foss <rfoss@kernel.org> <robert.foss@linaro.org>
|
||||
Rocky Liao <quic_rjliao@quicinc.com> <rjliao@codeaurora.org>
|
||||
Rodrigo Siqueira <siqueira@igalia.com> <rodrigosiqueiramelo@gmail.com>
|
||||
@ -674,9 +693,10 @@ Serge Hallyn <sergeh@kernel.org> <serge.hallyn@canonical.com>
|
||||
Serge Hallyn <sergeh@kernel.org> <serue@us.ibm.com>
|
||||
Seth Forshee <sforshee@kernel.org> <seth.forshee@canonical.com>
|
||||
Shakeel Butt <shakeel.butt@linux.dev> <shakeelb@google.com>
|
||||
Shannon Nelson <shannon.nelson@amd.com> <snelson@pensando.io>
|
||||
Shannon Nelson <shannon.nelson@amd.com> <shannon.nelson@intel.com>
|
||||
Shannon Nelson <shannon.nelson@amd.com> <shannon.nelson@oracle.com>
|
||||
Shannon Nelson <sln@onemain.com> <shannon.nelson@amd.com>
|
||||
Shannon Nelson <sln@onemain.com> <snelson@pensando.io>
|
||||
Shannon Nelson <sln@onemain.com> <shannon.nelson@intel.com>
|
||||
Shannon Nelson <sln@onemain.com> <shannon.nelson@oracle.com>
|
||||
Sharath Chandra Vurukala <quic_sharathv@quicinc.com> <sharathv@codeaurora.org>
|
||||
Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
|
||||
Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
|
||||
@ -705,6 +725,7 @@ Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org>
|
||||
Sriram R <quic_srirrama@quicinc.com> <srirrama@codeaurora.org>
|
||||
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
|
||||
Stanislav Fomichev <sdf@fomichev.me> <sdf@google.com>
|
||||
Stanislav Fomichev <sdf@fomichev.me> <stfomichev@gmail.com>
|
||||
Stefan Wahren <wahrenst@gmx.net> <stefan.wahren@i2se.com>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
Stephen Hemminger <stephen@networkplumber.org> <shemminger@linux-foundation.org>
|
||||
|
||||
5
CREDITS
5
CREDITS
@ -2981,6 +2981,11 @@ S: 521 Pleasant Valley Road
|
||||
S: Potsdam, New York 13676
|
||||
S: USA
|
||||
|
||||
N: Shannon Nelson
|
||||
E: sln@onemain.com
|
||||
D: Worked on several network drivers including
|
||||
D: ixgbe, i40e, ionic, pds_core, pds_vdpa, pds_fwctl
|
||||
|
||||
N: Dave Neuer
|
||||
E: dave.neuer@pobox.com
|
||||
D: Helped implement support for Compaq's H31xx series iPAQs
|
||||
|
||||
70
Documentation/ABI/testing/debugfs-pcie-ptm
Normal file
70
Documentation/ABI/testing/debugfs-pcie-ptm
Normal file
@ -0,0 +1,70 @@
|
||||
What: /sys/kernel/debug/pcie_ptm_*/local_clock
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RO) PTM local clock in nanoseconds. Applicable for both Root
|
||||
Complex and Endpoint controllers.
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/master_clock
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RO) PTM master clock in nanoseconds. Applicable only for
|
||||
Endpoint controllers.
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/t1
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RO) PTM T1 timestamp in nanoseconds. Applicable only for
|
||||
Endpoint controllers.
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/t2
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RO) PTM T2 timestamp in nanoseconds. Applicable only for
|
||||
Root Complex controllers.
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/t3
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RO) PTM T3 timestamp in nanoseconds. Applicable only for
|
||||
Root Complex controllers.
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/t4
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RO) PTM T4 timestamp in nanoseconds. Applicable only for
|
||||
Endpoint controllers.
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/context_update
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RW) Control the PTM context update mode. Applicable only for
|
||||
Endpoint controllers.
|
||||
|
||||
Following values are supported:
|
||||
|
||||
* auto = PTM context auto update trigger for every 10ms
|
||||
|
||||
* manual = PTM context manual update. Writing 'manual' to this
|
||||
file triggers PTM context update (default)
|
||||
|
||||
What: /sys/kernel/debug/pcie_ptm_*/context_valid
|
||||
Date: May 2025
|
||||
Contact: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
Description:
|
||||
(RW) Control the PTM context validity (local clock timing).
|
||||
Applicable only for Root Complex controllers. PTM context is
|
||||
invalidated by hardware if the Root Complex enters low power
|
||||
mode or changes link frequency.
|
||||
|
||||
Following values are supported:
|
||||
|
||||
* 0 = PTM context invalid (default)
|
||||
|
||||
* 1 = PTM context valid
|
||||
@ -242,7 +242,7 @@ Description:
|
||||
decoding a Host Physical Address range. Note that this number
|
||||
may be elevated without any regionX objects active or even
|
||||
enumerated, as this may be due to decoders established by
|
||||
platform firwmare or a previous kernel (kexec).
|
||||
platform firmware or a previous kernel (kexec).
|
||||
|
||||
|
||||
What: /sys/bus/cxl/devices/decoderX.Y
|
||||
@ -572,7 +572,7 @@ Description:
|
||||
|
||||
|
||||
What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth
|
||||
/sys/bus/cxl/devices/regionZ/accessY/write_banwidth
|
||||
/sys/bus/cxl/devices/regionZ/accessY/write_bandwidth
|
||||
Date: Jan, 2024
|
||||
KernelVersion: v6.9
|
||||
Contact: linux-cxl@vger.kernel.org
|
||||
|
||||
@ -94,6 +94,7 @@ Description:
|
||||
What: /sys/bus/iio/devices/iio:deviceX/sampling_frequency
|
||||
What: /sys/bus/iio/devices/iio:deviceX/in_intensity_sampling_frequency
|
||||
What: /sys/bus/iio/devices/iio:deviceX/buffer/sampling_frequency
|
||||
What: /sys/bus/iio/devices/iio:deviceX/events/sampling_frequency
|
||||
What: /sys/bus/iio/devices/triggerX/sampling_frequency
|
||||
KernelVersion: 2.6.35
|
||||
Contact: linux-iio@vger.kernel.org
|
||||
@ -740,7 +741,9 @@ Description:
|
||||
1kohm_to_gnd: connected to ground via an 1kOhm resistor,
|
||||
2.5kohm_to_gnd: connected to ground via a 2.5kOhm resistor,
|
||||
6kohm_to_gnd: connected to ground via a 6kOhm resistor,
|
||||
7.7kohm_to_gnd: connected to ground via a 7.7kOhm resistor,
|
||||
20kohm_to_gnd: connected to ground via a 20kOhm resistor,
|
||||
32kohm_to_gnd: connected to ground via a 32kOhm resistor,
|
||||
42kohm_to_gnd: connected to ground via a 42kOhm resistor,
|
||||
90kohm_to_gnd: connected to ground via a 90kOhm resistor,
|
||||
100kohm_to_gnd: connected to ground via an 100kOhm resistor,
|
||||
|
||||
@ -117,3 +117,47 @@ Date: July 2018
|
||||
KernelVersion: 4.19.0
|
||||
Contact: linux-pci@vger.kernel.org, rajatja@google.com
|
||||
Description: Total number of ERR_NONFATAL messages reported to rootport.
|
||||
|
||||
PCIe AER ratelimits
|
||||
-------------------
|
||||
|
||||
These attributes show up under all the devices that are AER capable.
|
||||
They represent configurable ratelimits of logs per error type.
|
||||
|
||||
See Documentation/PCI/pcieaer-howto.rst for more info on ratelimits.
|
||||
|
||||
What: /sys/bus/pci/devices/<dev>/aer/correctable_ratelimit_interval_ms
|
||||
Date: May 2025
|
||||
KernelVersion: 6.16.0
|
||||
Contact: linux-pci@vger.kernel.org
|
||||
Description: Writing 0 disables AER correctable error log ratelimiting.
|
||||
Writing a positive value sets the ratelimit interval in ms.
|
||||
Default is DEFAULT_RATELIMIT_INTERVAL (5000 ms).
|
||||
|
||||
What: /sys/bus/pci/devices/<dev>/aer/correctable_ratelimit_burst
|
||||
Date: May 2025
|
||||
KernelVersion: 6.16.0
|
||||
Contact: linux-pci@vger.kernel.org
|
||||
Description: Ratelimit burst for correctable error logs. Writing a value
|
||||
changes the number of errors (burst) allowed per interval
|
||||
before ratelimiting. Reading gets the current ratelimit
|
||||
burst. Default is DEFAULT_RATELIMIT_BURST (10).
|
||||
|
||||
What: /sys/bus/pci/devices/<dev>/aer/nonfatal_ratelimit_interval_ms
|
||||
Date: May 2025
|
||||
KernelVersion: 6.16.0
|
||||
Contact: linux-pci@vger.kernel.org
|
||||
Description: Writing 0 disables AER non-fatal uncorrectable error log
|
||||
ratelimiting. Writing a positive value sets the ratelimit
|
||||
interval in ms. Default is DEFAULT_RATELIMIT_INTERVAL
|
||||
(5000 ms).
|
||||
|
||||
What: /sys/bus/pci/devices/<dev>/aer/nonfatal_ratelimit_burst
|
||||
Date: May 2025
|
||||
KernelVersion: 6.16.0
|
||||
Contact: linux-pci@vger.kernel.org
|
||||
Description: Ratelimit burst for non-fatal uncorrectable error logs.
|
||||
Writing a value changes the number of errors (burst)
|
||||
allowed per interval before ratelimiting. Reading gets the
|
||||
current ratelimit burst. Default is DEFAULT_RATELIMIT_BURST
|
||||
(10).
|
||||
@ -72,6 +72,12 @@ Description:
|
||||
/sys/class/leds/<led> once a given trigger is selected. For
|
||||
their documentation see `sysfs-class-led-trigger-*`.
|
||||
|
||||
Writing "none" removes the trigger for this LED.
|
||||
|
||||
Writing "default" sets the trigger to the LED's default trigger
|
||||
(which would often be configured in the device tree for the
|
||||
hardware).
|
||||
|
||||
What: /sys/class/leds/<led>/inverted
|
||||
Date: January 2011
|
||||
KernelVersion: 2.6.38
|
||||
|
||||
@ -17,7 +17,7 @@ Description: Read only. Returns the firmware version of Intel MAX10
|
||||
What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address
|
||||
Date: January 2021
|
||||
KernelVersion: 5.12
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns the first MAC address in a block
|
||||
of sequential MAC addresses assigned to the board
|
||||
that is managed by the Intel MAX10 BMC. It is stored in
|
||||
@ -28,7 +28,7 @@ Description: Read only. Returns the first MAC address in a block
|
||||
What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count
|
||||
Date: January 2021
|
||||
KernelVersion: 5.12
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns the number of sequential MAC
|
||||
addresses assigned to the board managed by the Intel
|
||||
MAX10 BMC. This value is stored in FLASH and is mirrored
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns the root entry hash for the static
|
||||
region if one is programmed, else it returns the
|
||||
string: "hash not programmed". This file is only
|
||||
@ -11,7 +11,7 @@ Description: Read only. Returns the root entry hash for the static
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns the root entry hash for the partial
|
||||
reconfiguration region if one is programmed, else it
|
||||
returns the string: "hash not programmed". This file
|
||||
@ -21,7 +21,7 @@ Description: Read only. Returns the root entry hash for the partial
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns the root entry hash for the BMC image
|
||||
if one is programmed, else it returns the string:
|
||||
"hash not programmed". This file is only visible if the
|
||||
@ -31,7 +31,7 @@ Description: Read only. Returns the root entry hash for the BMC image
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns a list of indices for canceled code
|
||||
signing keys for the static region. The standard bitmap
|
||||
list format is used (e.g. "1,2-6,9").
|
||||
@ -39,7 +39,7 @@ Description: Read only. Returns a list of indices for canceled code
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns a list of indices for canceled code
|
||||
signing keys for the partial reconfiguration region. The
|
||||
standard bitmap list format is used (e.g. "1,2-6,9").
|
||||
@ -47,7 +47,7 @@ Description: Read only. Returns a list of indices for canceled code
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns a list of indices for canceled code
|
||||
signing keys for the BMC. The standard bitmap list format
|
||||
is used (e.g. "1,2-6,9").
|
||||
@ -55,7 +55,7 @@ Description: Read only. Returns a list of indices for canceled code
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Peter Colberg <peter.colberg@altera.com>
|
||||
Contact: Matthew Gerlach <matthew.gerlach@altera.com>
|
||||
Description: Read only. Returns number of times the secure update
|
||||
staging area has been flashed.
|
||||
Format: "%u".
|
||||
|
||||
@ -60,26 +60,26 @@ Description: RO. Package default power limit (default TDP setting).
|
||||
|
||||
Only supported for particular Intel Xe graphics platforms.
|
||||
|
||||
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_crit
|
||||
Date: February 2024
|
||||
KernelVersion: 6.8
|
||||
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_crit
|
||||
Date: May 2025
|
||||
KernelVersion: 6.15
|
||||
Contact: intel-xe@lists.freedesktop.org
|
||||
Description: RW. Package reactive critical (I1) power limit in microwatts.
|
||||
Description: RW. Card reactive critical (I1) power limit in microwatts.
|
||||
|
||||
Package reactive critical (I1) power limit in microwatts is exposed
|
||||
Card reactive critical (I1) power limit in microwatts is exposed
|
||||
for client products. The power controller will throttle the
|
||||
operating frequency if the power averaged over a window exceeds
|
||||
this limit.
|
||||
|
||||
Only supported for particular Intel Xe graphics platforms.
|
||||
|
||||
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr2_crit
|
||||
Date: February 2024
|
||||
KernelVersion: 6.8
|
||||
What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr1_crit
|
||||
Date: May 2025
|
||||
KernelVersion: 6.15
|
||||
Contact: intel-xe@lists.freedesktop.org
|
||||
Description: RW. Package reactive critical (I1) power limit in milliamperes.
|
||||
Description: RW. Card reactive critical (I1) power limit in milliamperes.
|
||||
|
||||
Package reactive critical (I1) power limit in milliamperes is
|
||||
Card reactive critical (I1) power limit in milliamperes is
|
||||
exposed for server products. The power controller will throttle
|
||||
the operating frequency if the power averaged over a window
|
||||
exceeds this limit.
|
||||
|
||||
10
Documentation/PCI/controller/index.rst
Normal file
10
Documentation/PCI/controller/index.rst
Normal file
@ -0,0 +1,10 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
===========================================
|
||||
PCI Native Host Bridge and Endpoint Drivers
|
||||
===========================================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
rcar-pcie-firmware
|
||||
32
Documentation/PCI/controller/rcar-pcie-firmware.rst
Normal file
32
Documentation/PCI/controller/rcar-pcie-firmware.rst
Normal file
@ -0,0 +1,32 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
=================================================
|
||||
Firmware of PCIe controller for Renesas R-Car V4H
|
||||
=================================================
|
||||
|
||||
Renesas R-Car V4H (r8a779g0) has a PCIe controller, requiring a specific
|
||||
firmware download during startup.
|
||||
|
||||
However, Renesas currently cannot distribute the firmware free of charge.
|
||||
|
||||
The firmware file "104_PCIe_fw_addr_data_ver1.05.txt" (note that the file name
|
||||
might be different between different datasheet revisions) can be found in the
|
||||
datasheet encoded as text, and as such, the file's content must be converted
|
||||
back to binary form. This can be achieved using the following example script:
|
||||
|
||||
.. code-block:: sh
|
||||
|
||||
$ awk '/^\s*0x[0-9A-Fa-f]{4}\s+0x[0-9A-Fa-f]{4}/ { print substr($2,5,2) substr($2,3,2) }' \
|
||||
104_PCIe_fw_addr_data_ver1.05.txt | \
|
||||
xxd -p -r > rcar_gen4_pcie.bin
|
||||
|
||||
Once the text content has been converted into a binary firmware file, verify
|
||||
its checksum as follows:
|
||||
|
||||
.. code-block:: sh
|
||||
|
||||
$ sha1sum rcar_gen4_pcie.bin
|
||||
1d0bd4b189b4eb009f5d564b1f93a79112994945 rcar_gen4_pcie.bin
|
||||
|
||||
The resulting binary file called "rcar_gen4_pcie.bin" should be placed in the
|
||||
"/lib/firmware" directory before the driver runs.
|
||||
@ -8,6 +8,6 @@ PCI NVMe Function
|
||||
|
||||
The PCI NVMe endpoint function implements a PCI NVMe controller using the NVMe
|
||||
subsystem target core code. The driver for this function resides with the NVMe
|
||||
subsystem as drivers/nvme/target/nvmet-pciep.c.
|
||||
subsystem as drivers/nvme/target/pci-epf.c.
|
||||
|
||||
See Documentation/nvme/nvme-pci-endpoint-target.rst for more details.
|
||||
|
||||
@ -17,5 +17,6 @@ PCI Bus Subsystem
|
||||
pci-error-recovery
|
||||
pcieaer-howto
|
||||
endpoint/index
|
||||
controller/index
|
||||
boot-interrupts
|
||||
tph
|
||||
|
||||
@ -85,12 +85,27 @@ In the example, 'Requester ID' means the ID of the device that sent
|
||||
the error message to the Root Port. Please refer to PCIe specs for other
|
||||
fields.
|
||||
|
||||
AER Ratelimits
|
||||
--------------
|
||||
|
||||
Since error messages can be generated for each transaction, we may see
|
||||
large volumes of errors reported. To prevent spammy devices from flooding
|
||||
the console/stalling execution, messages are throttled by device and error
|
||||
type (correctable vs. non-fatal uncorrectable). Fatal errors, including
|
||||
DPC errors, are not ratelimited.
|
||||
|
||||
AER uses the default ratelimit of DEFAULT_RATELIMIT_BURST (10 events) over
|
||||
DEFAULT_RATELIMIT_INTERVAL (5 seconds).
|
||||
|
||||
Ratelimits are exposed in the form of sysfs attributes and configurable.
|
||||
See Documentation/ABI/testing/sysfs-bus-pci-devices-aer.
|
||||
|
||||
AER Statistics / Counters
|
||||
-------------------------
|
||||
|
||||
When PCIe AER errors are captured, the counters / statistics are also exposed
|
||||
in the form of sysfs attributes which are documented at
|
||||
Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
|
||||
Documentation/ABI/testing/sysfs-bus-pci-devices-aer.
|
||||
|
||||
Developer Guide
|
||||
===============
|
||||
|
||||
@ -270,6 +270,8 @@ configured for Unix Extensions (and the client has not disabled
|
||||
illegal Windows/NTFS/SMB characters to a remap range (this mount parameter
|
||||
is the default for SMB3). This remap (``mapposix``) range is also
|
||||
compatible with Mac (and "Services for Mac" on some older Windows).
|
||||
When POSIX Extensions for SMB 3.1.1 are negotiated, remapping is automatically
|
||||
disabled.
|
||||
|
||||
CIFS VFS Mount Options
|
||||
======================
|
||||
|
||||
@ -458,6 +458,9 @@
|
||||
arm64.nomops [ARM64] Unconditionally disable Memory Copy and Memory
|
||||
Set instructions support
|
||||
|
||||
arm64.nompam [ARM64] Unconditionally disable Memory Partitioning And
|
||||
Monitoring support
|
||||
|
||||
arm64.nomte [ARM64] Unconditionally disable Memory Tagging Extension
|
||||
support
|
||||
|
||||
|
||||
@ -296,6 +296,39 @@ information is missing.
|
||||
To recover from this mode, one needs to flash a valid NVM image to the
|
||||
host controller in the same way it is done in the previous chapter.
|
||||
|
||||
Tunneling events
|
||||
----------------
|
||||
The driver sends ``KOBJ_CHANGE`` events to userspace when there is a
|
||||
tunneling change in the ``thunderbolt_domain``. The notification carries
|
||||
following environment variables::
|
||||
|
||||
TUNNEL_EVENT=<EVENT>
|
||||
TUNNEL_DETAILS=0:12 <-> 1:20 (USB3)
|
||||
|
||||
Possible values for ``<EVENT>`` are:
|
||||
|
||||
activated
|
||||
The tunnel was activated (created).
|
||||
|
||||
changed
|
||||
There is a change in this tunnel. For example bandwidth allocation was
|
||||
changed.
|
||||
|
||||
deactivated
|
||||
The tunnel was torn down.
|
||||
|
||||
low bandwidth
|
||||
The tunnel is not getting optimal bandwidth.
|
||||
|
||||
insufficient bandwidth
|
||||
There is not enough bandwidth for the current tunnel requirements.
|
||||
|
||||
The ``TUNNEL_DETAILS`` is only provided if the tunnel is known. For
|
||||
example, in case of Firmware Connection Manager this is missing or does
|
||||
not provide full tunnel information. In case of Software Connection Manager
|
||||
this includes full tunnel details. The format currently matches what the
|
||||
driver uses when logging. This may change over time.
|
||||
|
||||
Networking over Thunderbolt cable
|
||||
---------------------------------
|
||||
Thunderbolt technology allows software communication between two hosts
|
||||
|
||||
@ -234,7 +234,7 @@ Before jumping into the kernel, the following conditions must be met:
|
||||
|
||||
- If the kernel is entered at EL1:
|
||||
|
||||
- ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
|
||||
- ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
|
||||
- ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
|
||||
|
||||
- The DT or ACPI tables must describe a GICv3 interrupt controller.
|
||||
|
||||
@ -10,13 +10,45 @@ modified by the program itself. Instruction storage and the instruction cache
|
||||
program must enforce its own synchronization with the unprivileged fence.i
|
||||
instruction.
|
||||
|
||||
However, the default Linux ABI prohibits the use of fence.i in userspace
|
||||
applications. At any point the scheduler may migrate a task onto a new hart. If
|
||||
migration occurs after the userspace synchronized the icache and instruction
|
||||
storage with fence.i, the icache on the new hart will no longer be clean. This
|
||||
is due to the behavior of fence.i only affecting the hart that it is called on.
|
||||
Thus, the hart that the task has been migrated to may not have synchronized
|
||||
instruction storage and icache.
|
||||
CMODX in the Kernel Space
|
||||
-------------------------
|
||||
|
||||
Dynamic ftrace
|
||||
---------------------
|
||||
|
||||
Essentially, dynamic ftrace directs the control flow by inserting a function
|
||||
call at each patchable function entry, and patches it dynamically at runtime to
|
||||
enable or disable the redirection. In the case of RISC-V, 2 instructions,
|
||||
AUIPC + JALR, are required to compose a function call. However, it is impossible
|
||||
to patch 2 instructions and expect that a concurrent read-side executes them
|
||||
without a race condition. This series makes atmoic code patching possible in
|
||||
RISC-V ftrace. Kernel preemption makes things even worse as it allows the old
|
||||
state to persist across the patching process with stop_machine().
|
||||
|
||||
In order to get rid of stop_machine() and run dynamic ftrace with full kernel
|
||||
preemption, we partially initialize each patchable function entry at boot-time,
|
||||
setting the first instruction to AUIPC, and the second to NOP. Now, atmoic
|
||||
patching is possible because the kernel only has to update one instruction.
|
||||
According to Ziccif, as long as an instruction is naturally aligned, the ISA
|
||||
guarantee an atomic update.
|
||||
|
||||
By fixing down the first instruction, AUIPC, the range of the ftrace trampoline
|
||||
is limited to +-2K from the predetermined target, ftrace_caller, due to the lack
|
||||
of immediate encoding space in RISC-V. To address the issue, we introduce
|
||||
CALL_OPS, where an 8B naturally align metadata is added in front of each
|
||||
pacthable function. The metadata is resolved at the first trampoline, then the
|
||||
execution can be derect to another custom trampoline.
|
||||
|
||||
CMODX in the User Space
|
||||
-----------------------
|
||||
|
||||
Though fence.i is an unprivileged instruction, the default Linux ABI prohibits
|
||||
the use of fence.i in userspace applications. At any point the scheduler may
|
||||
migrate a task onto a new hart. If migration occurs after the userspace
|
||||
synchronized the icache and instruction storage with fence.i, the icache on the
|
||||
new hart will no longer be clean. This is due to the behavior of fence.i only
|
||||
affecting the hart that it is called on. Thus, the hart that the task has been
|
||||
migrated to may not have synchronized instruction storage and icache.
|
||||
|
||||
There are two ways to solve this problem: use the riscv_flush_icache() syscall,
|
||||
or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl() and emit fence.i in
|
||||
|
||||
@ -271,6 +271,10 @@ The following keys are defined:
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as
|
||||
ratified in commit 49f49c842ff9 ("Update to Rafified state") of
|
||||
riscv-zabha.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
|
||||
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
|
||||
mistakenly classified as a bitmask rather than a value.
|
||||
@ -335,3 +339,25 @@ The following keys are defined:
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
|
||||
represents the size of the Zicbom block in bytes.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the
|
||||
sifive vendor extensions that are compatible with the
|
||||
:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
|
||||
|
||||
* SIFIVE
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
|
||||
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
|
||||
Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
|
||||
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
|
||||
Instruction Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
|
||||
vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
|
||||
Clip Instructions Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
|
||||
vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
|
||||
Instruction Extensions Specification.
|
||||
@ -115,15 +115,15 @@ managing and controlling ublk devices with help of several control commands:
|
||||
|
||||
- ``UBLK_CMD_START_DEV``
|
||||
|
||||
After the server prepares userspace resources (such as creating per-queue
|
||||
pthread & io_uring for handling ublk IO), this command is sent to the
|
||||
After the server prepares userspace resources (such as creating I/O handler
|
||||
threads & io_uring for handling ublk IO), this command is sent to the
|
||||
driver for allocating & exposing ``/dev/ublkb*``. Parameters set via
|
||||
``UBLK_CMD_SET_PARAMS`` are applied for creating the device.
|
||||
|
||||
- ``UBLK_CMD_STOP_DEV``
|
||||
|
||||
Halt IO on ``/dev/ublkb*`` and remove the device. When this command returns,
|
||||
ublk server will release resources (such as destroying per-queue pthread &
|
||||
ublk server will release resources (such as destroying I/O handler threads &
|
||||
io_uring).
|
||||
|
||||
- ``UBLK_CMD_DEL_DEV``
|
||||
@ -208,15 +208,15 @@ managing and controlling ublk devices with help of several control commands:
|
||||
modify how I/O is handled while the ublk server is dying/dead (this is called
|
||||
the ``nosrv`` case in the driver code).
|
||||
|
||||
With just ``UBLK_F_USER_RECOVERY`` set, after one ubq_daemon(ublk server's io
|
||||
handler) is dying, ublk does not delete ``/dev/ublkb*`` during the whole
|
||||
With just ``UBLK_F_USER_RECOVERY`` set, after the ublk server exits,
|
||||
ublk does not delete ``/dev/ublkb*`` during the whole
|
||||
recovery stage and ublk device ID is kept. It is ublk server's
|
||||
responsibility to recover the device context by its own knowledge.
|
||||
Requests which have not been issued to userspace are requeued. Requests
|
||||
which have been issued to userspace are aborted.
|
||||
|
||||
With ``UBLK_F_USER_RECOVERY_REISSUE`` additionally set, after one ubq_daemon
|
||||
(ublk server's io handler) is dying, contrary to ``UBLK_F_USER_RECOVERY``,
|
||||
With ``UBLK_F_USER_RECOVERY_REISSUE`` additionally set, after the ublk server
|
||||
exits, contrary to ``UBLK_F_USER_RECOVERY``,
|
||||
requests which have been issued to userspace are requeued and will be
|
||||
re-issued to the new process after handling ``UBLK_CMD_END_USER_RECOVERY``.
|
||||
``UBLK_F_USER_RECOVERY_REISSUE`` is designed for backends who tolerate
|
||||
@ -241,10 +241,11 @@ can be controlled/accessed just inside this container.
|
||||
Data plane
|
||||
----------
|
||||
|
||||
ublk server needs to create per-queue IO pthread & io_uring for handling IO
|
||||
commands via io_uring passthrough. The per-queue IO pthread
|
||||
focuses on IO handling and shouldn't handle any control & management
|
||||
tasks.
|
||||
The ublk server should create dedicated threads for handling I/O. Each
|
||||
thread should have its own io_uring through which it is notified of new
|
||||
I/O, and through which it can complete I/O. These dedicated threads
|
||||
should focus on IO handling and shouldn't handle any control &
|
||||
management tasks.
|
||||
|
||||
The's IO is assigned by a unique tag, which is 1:1 mapping with IO
|
||||
request of ``/dev/ublkb*``.
|
||||
@ -265,6 +266,18 @@ with specified IO tag in the command data:
|
||||
destined to ``/dev/ublkb*``. This command is sent only once from the server
|
||||
IO pthread for ublk driver to setup IO forward environment.
|
||||
|
||||
Once a thread issues this command against a given (qid,tag) pair, the thread
|
||||
registers itself as that I/O's daemon. In the future, only that I/O's daemon
|
||||
is allowed to issue commands against the I/O. If any other thread attempts
|
||||
to issue a command against a (qid,tag) pair for which the thread is not the
|
||||
daemon, the command will fail. Daemons can be reset only be going through
|
||||
recovery.
|
||||
|
||||
The ability for every (qid,tag) pair to have its own independent daemon task
|
||||
is indicated by the ``UBLK_F_PER_IO_DAEMON`` feature. If this feature is not
|
||||
supported by the driver, daemons must be per-queue instead - i.e. all I/Os
|
||||
associated to a single qid must be handled by the same task.
|
||||
|
||||
- ``UBLK_IO_COMMIT_AND_FETCH_REQ``
|
||||
|
||||
When an IO request is destined to ``/dev/ublkb*``, the driver stores
|
||||
@ -339,6 +352,83 @@ For reaching best IO performance, ublk server should align its segment
|
||||
parameter of `struct ublk_param_segment` with backend for avoiding
|
||||
unnecessary IO split, which usually hurts io_uring performance.
|
||||
|
||||
Auto Buffer Registration
|
||||
------------------------
|
||||
|
||||
The ``UBLK_F_AUTO_BUF_REG`` feature automatically handles buffer registration
|
||||
and unregistration for I/O requests, which simplifies the buffer management
|
||||
process and reduces overhead in the ublk server implementation.
|
||||
|
||||
This is another feature flag for using zero copy, and it is compatible with
|
||||
``UBLK_F_SUPPORT_ZERO_COPY``.
|
||||
|
||||
Feature Overview
|
||||
~~~~~~~~~~~~~~~~
|
||||
|
||||
This feature automatically registers request buffers to the io_uring context
|
||||
before delivering I/O commands to the ublk server and unregisters them when
|
||||
completing I/O commands. This eliminates the need for manual buffer
|
||||
registration/unregistration via ``UBLK_IO_REGISTER_IO_BUF`` and
|
||||
``UBLK_IO_UNREGISTER_IO_BUF`` commands, then IO handling in ublk server
|
||||
can avoid dependency on the two uring_cmd operations.
|
||||
|
||||
IOs can't be issued concurrently to io_uring if there is any dependency
|
||||
among these IOs. So this way not only simplifies ublk server implementation,
|
||||
but also makes concurrent IO handling becomes possible by removing the
|
||||
dependency on buffer registration & unregistration commands.
|
||||
|
||||
Usage Requirements
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
1. The ublk server must create a sparse buffer table on the same ``io_ring_ctx``
|
||||
used for ``UBLK_IO_FETCH_REQ`` and ``UBLK_IO_COMMIT_AND_FETCH_REQ``. If
|
||||
uring_cmd is issued on a different ``io_ring_ctx``, manual buffer
|
||||
unregistration is required.
|
||||
|
||||
2. Buffer registration data must be passed via uring_cmd's ``sqe->addr`` with the
|
||||
following structure::
|
||||
|
||||
struct ublk_auto_buf_reg {
|
||||
__u16 index; /* Buffer index for registration */
|
||||
__u8 flags; /* Registration flags */
|
||||
__u8 reserved0; /* Reserved for future use */
|
||||
__u32 reserved1; /* Reserved for future use */
|
||||
};
|
||||
|
||||
ublk_auto_buf_reg_to_sqe_addr() is for converting the above structure into
|
||||
``sqe->addr``.
|
||||
|
||||
3. All reserved fields in ``ublk_auto_buf_reg`` must be zeroed.
|
||||
|
||||
4. Optional flags can be passed via ``ublk_auto_buf_reg.flags``.
|
||||
|
||||
Fallback Behavior
|
||||
~~~~~~~~~~~~~~~~~
|
||||
|
||||
If auto buffer registration fails:
|
||||
|
||||
1. When ``UBLK_AUTO_BUF_REG_FALLBACK`` is enabled:
|
||||
|
||||
- The uring_cmd is completed
|
||||
- ``UBLK_IO_F_NEED_REG_BUF`` is set in ``ublksrv_io_desc.op_flags``
|
||||
- The ublk server must manually deal with the failure, such as, register
|
||||
the buffer manually, or using user copy feature for retrieving the data
|
||||
for handling ublk IO
|
||||
|
||||
2. If fallback is not enabled:
|
||||
|
||||
- The ublk I/O request fails silently
|
||||
- The uring_cmd won't be completed
|
||||
|
||||
Limitations
|
||||
~~~~~~~~~~~
|
||||
|
||||
- Requires same ``io_ring_ctx`` for all operations
|
||||
- May require manual buffer management in fallback cases
|
||||
- io_ring_ctx buffer table has a max size of 16K, which may not be enough
|
||||
in case that too many ublk devices are handled by this single io_ring_ctx
|
||||
and each one has very large queue depth
|
||||
|
||||
References
|
||||
==========
|
||||
|
||||
|
||||
@ -233,10 +233,16 @@ attempts in order to enforce the LRU property which have increasing impacts on
|
||||
other CPUs involved in the following operation attempts:
|
||||
|
||||
- Attempt to use CPU-local state to batch operations
|
||||
- Attempt to fetch free nodes from global lists
|
||||
- Attempt to fetch ``target_free`` free nodes from global lists
|
||||
- Attempt to pull any node from a global list and remove it from the hashmap
|
||||
- Attempt to pull any node from any CPU's list and remove it from the hashmap
|
||||
|
||||
The number of nodes to borrow from the global list in a batch, ``target_free``,
|
||||
depends on the size of the map. Larger batch size reduces lock contention, but
|
||||
may also exhaust the global structure. The value is computed at map init to
|
||||
avoid exhaustion, by limiting aggregate reservation by all CPUs to half the map
|
||||
size. With a minimum of a single element and maximum budget of 128 at a time.
|
||||
|
||||
This algorithm is described visually in the following diagram. See the
|
||||
description in commit 3a08c2fd7634 ("bpf: LRU List") for a full explanation of
|
||||
the corresponding operations:
|
||||
|
||||
@ -35,18 +35,18 @@ digraph {
|
||||
fn_bpf_lru_list_pop_free_to_local [shape=rectangle,fillcolor=2,
|
||||
label="Flush local pending,
|
||||
Rotate Global list, move
|
||||
LOCAL_FREE_TARGET
|
||||
target_free
|
||||
from global -> local"]
|
||||
// Also corresponds to:
|
||||
// fn__local_list_flush()
|
||||
// fn_bpf_lru_list_rotate()
|
||||
fn___bpf_lru_node_move_to_free[shape=diamond,fillcolor=2,
|
||||
label="Able to free\nLOCAL_FREE_TARGET\nnodes?"]
|
||||
label="Able to free\ntarget_free\nnodes?"]
|
||||
|
||||
fn___bpf_lru_list_shrink_inactive [shape=rectangle,fillcolor=3,
|
||||
label="Shrink inactive list
|
||||
up to remaining
|
||||
LOCAL_FREE_TARGET
|
||||
target_free
|
||||
(global LRU -> local)"]
|
||||
fn___bpf_lru_list_shrink [shape=diamond,fillcolor=2,
|
||||
label="> 0 entries in\nlocal free list?"]
|
||||
|
||||
@ -6,18 +6,8 @@ The following document describes how to use Symbol Namespaces to structure the
|
||||
export surface of in-kernel symbols exported through the family of
|
||||
EXPORT_SYMBOL() macros.
|
||||
|
||||
.. Table of Contents
|
||||
|
||||
=== 1 Introduction
|
||||
=== 2 How to define Symbol Namespaces
|
||||
--- 2.1 Using the EXPORT_SYMBOL macros
|
||||
--- 2.2 Using the DEFAULT_SYMBOL_NAMESPACE define
|
||||
=== 3 How to use Symbols exported in Namespaces
|
||||
=== 4 Loading Modules that use namespaced Symbols
|
||||
=== 5 Automatically creating MODULE_IMPORT_NS statements
|
||||
|
||||
1. Introduction
|
||||
===============
|
||||
Introduction
|
||||
============
|
||||
|
||||
Symbol Namespaces have been introduced as a means to structure the export
|
||||
surface of the in-kernel API. It allows subsystem maintainers to partition
|
||||
@ -28,15 +18,18 @@ kernel. As of today, modules that make use of symbols exported into namespaces,
|
||||
are required to import the namespace. Otherwise the kernel will, depending on
|
||||
its configuration, reject loading the module or warn about a missing import.
|
||||
|
||||
2. How to define Symbol Namespaces
|
||||
==================================
|
||||
Additionally, it is possible to put symbols into a module namespace, strictly
|
||||
limiting which modules are allowed to use these symbols.
|
||||
|
||||
How to define Symbol Namespaces
|
||||
===============================
|
||||
|
||||
Symbols can be exported into namespace using different methods. All of them are
|
||||
changing the way EXPORT_SYMBOL and friends are instrumented to create ksymtab
|
||||
entries.
|
||||
|
||||
2.1 Using the EXPORT_SYMBOL macros
|
||||
==================================
|
||||
Using the EXPORT_SYMBOL macros
|
||||
------------------------------
|
||||
|
||||
In addition to the macros EXPORT_SYMBOL() and EXPORT_SYMBOL_GPL(), that allow
|
||||
exporting of kernel symbols to the kernel symbol table, variants of these are
|
||||
@ -54,8 +47,8 @@ refer to ``NULL``. There is no default namespace if none is defined. ``modpost``
|
||||
and kernel/module/main.c make use the namespace at build time or module load
|
||||
time, respectively.
|
||||
|
||||
2.2 Using the DEFAULT_SYMBOL_NAMESPACE define
|
||||
=============================================
|
||||
Using the DEFAULT_SYMBOL_NAMESPACE define
|
||||
-----------------------------------------
|
||||
|
||||
Defining namespaces for all symbols of a subsystem can be very verbose and may
|
||||
become hard to maintain. Therefore a default define (DEFAULT_SYMBOL_NAMESPACE)
|
||||
@ -83,8 +76,24 @@ unit as preprocessor statement. The above example would then read::
|
||||
within the corresponding compilation unit before the #include for
|
||||
<linux/export.h>. Typically it's placed before the first #include statement.
|
||||
|
||||
3. How to use Symbols exported in Namespaces
|
||||
============================================
|
||||
Using the EXPORT_SYMBOL_GPL_FOR_MODULES() macro
|
||||
-----------------------------------------------
|
||||
|
||||
Symbols exported using this macro are put into a module namespace. This
|
||||
namespace cannot be imported.
|
||||
|
||||
The macro takes a comma separated list of module names, allowing only those
|
||||
modules to access this symbol. Simple tail-globs are supported.
|
||||
|
||||
For example::
|
||||
|
||||
EXPORT_SYMBOL_GPL_FOR_MODULES(preempt_notifier_inc, "kvm,kvm-*")
|
||||
|
||||
will limit usage of this symbol to modules whoes name matches the given
|
||||
patterns.
|
||||
|
||||
How to use Symbols exported in Namespaces
|
||||
=========================================
|
||||
|
||||
In order to use symbols that are exported into namespaces, kernel modules need
|
||||
to explicitly import these namespaces. Otherwise the kernel might reject to
|
||||
@ -106,11 +115,10 @@ inspected with modinfo::
|
||||
|
||||
|
||||
It is advisable to add the MODULE_IMPORT_NS() statement close to other module
|
||||
metadata definitions like MODULE_AUTHOR() or MODULE_LICENSE(). Refer to section
|
||||
5. for a way to create missing import statements automatically.
|
||||
metadata definitions like MODULE_AUTHOR() or MODULE_LICENSE().
|
||||
|
||||
4. Loading Modules that use namespaced Symbols
|
||||
==============================================
|
||||
Loading Modules that use namespaced Symbols
|
||||
===========================================
|
||||
|
||||
At module loading time (e.g. ``insmod``), the kernel will check each symbol
|
||||
referenced from the module for its availability and whether the namespace it
|
||||
@ -121,8 +129,8 @@ allow loading of modules that don't satisfy this precondition, a configuration
|
||||
option is available: Setting MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y will
|
||||
enable loading regardless, but will emit a warning.
|
||||
|
||||
5. Automatically creating MODULE_IMPORT_NS statements
|
||||
=====================================================
|
||||
Automatically creating MODULE_IMPORT_NS statements
|
||||
==================================================
|
||||
|
||||
Missing namespaces imports can easily be detected at build time. In fact,
|
||||
modpost will emit a warning if a module uses a symbol from a namespace
|
||||
@ -154,3 +162,6 @@ in-tree modules::
|
||||
You can also run nsdeps for external module builds. A typical usage is::
|
||||
|
||||
$ make -C <path_to_kernel_src> M=$PWD nsdeps
|
||||
|
||||
Note: it will happily generate an import statement for the module namespace;
|
||||
which will not work and generates build and runtime failures.
|
||||
|
||||
@ -30,6 +30,19 @@ properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum: [apb_pclk, atclk]
|
||||
- items: # Zynq-700
|
||||
- const: apb_pclk
|
||||
- const: dbg_trc
|
||||
- const: dbg_apb
|
||||
|
||||
in-ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
additionalProperties: false
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/atmel,sama5d2-secumod.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip AT91 Security Module (SECUMOD)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
|
||||
description:
|
||||
The Security Module also offers the PIOBU pins which can be used as GPIO pins.
|
||||
Note that they maintain their voltage during Backup/Self-refresh.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: atmel,sama5d2-secumod
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sama7d65-secumod
|
||||
- microchip,sama7g5-secumod
|
||||
- const: atmel,sama5d2-secumod
|
||||
- const: syscon
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
security-module@fc040000 {
|
||||
compatible = "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xfc040000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
@ -46,28 +46,3 @@ Examples:
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
Security Module (SECUMOD)
|
||||
|
||||
The Security Module macrocell provides all necessary secure functions to avoid
|
||||
voltage, temperature, frequency and mechanical attacks on the chip. It also
|
||||
embeds secure memories that can be scrambled.
|
||||
|
||||
The Security Module also offers the PIOBU pins which can be used as GPIO pins.
|
||||
Note that they maintain their voltage during Backup/Self-refresh.
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-secumod", "syscon".
|
||||
<chip> can be "sama5d2".
|
||||
- reg: Should contain registers location and length
|
||||
- gpio-controller: Marks the port as GPIO controller.
|
||||
- #gpio-cells: There are 2. The pin number is the
|
||||
first, the second represents additional
|
||||
parameters such as GPIO_ACTIVE_HIGH/LOW.
|
||||
|
||||
|
||||
secumod@fc040000 {
|
||||
compatible = "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xfc040000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
@ -118,15 +118,11 @@ $defs:
|
||||
ti,lvds-vod-swing-clock-microvolt:
|
||||
description: LVDS diferential output voltage <min max> for clock
|
||||
lanes in microvolts.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
ti,lvds-vod-swing-data-microvolt:
|
||||
description: LVDS diferential output voltage <min max> for data
|
||||
lanes in microvolts.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
allOf:
|
||||
|
||||
44
Documentation/devicetree/bindings/dma/arm,dma-350.yaml
Normal file
44
Documentation/devicetree/bindings/dma/arm,dma-350.yaml
Normal file
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/arm,dma-350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm CoreLink DMA-350 Controller
|
||||
|
||||
maintainers:
|
||||
- Robin Murphy <robin.murphy@arm.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,dma-350
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Base and size of the full register map
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Channel 0 interrupt
|
||||
- description: Channel 1 interrupt
|
||||
- description: Channel 2 interrupt
|
||||
- description: Channel 3 interrupt
|
||||
- description: Channel 4 interrupt
|
||||
- description: Channel 5 interrupt
|
||||
- description: Channel 6 interrupt
|
||||
- description: Channel 7 interrupt
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
description: The cell is the trigger input number
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
@ -48,11 +48,11 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
maxItems: 65
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
maxItems: 64
|
||||
maxItems: 65
|
||||
|
||||
"#dma-cells":
|
||||
description: |
|
||||
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
- enum:
|
||||
- nvidia,tegra210-adma
|
||||
- nvidia,tegra186-adma
|
||||
- nvidia,tegra264-adma
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra234-adma
|
||||
@ -92,6 +93,7 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra186-adma
|
||||
- nvidia,tegra264-adma
|
||||
then:
|
||||
anyOf:
|
||||
- properties:
|
||||
|
||||
@ -42,6 +42,8 @@ properties:
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
iommus:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
@ -11,7 +11,8 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r7s72100-dmac # RZ/A1H
|
||||
- renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
|
||||
@ -20,10 +21,13 @@ properties:
|
||||
- renesas,r9a08g045-dmac # RZ/G3S
|
||||
- const: renesas,rz-dmac
|
||||
|
||||
- const: renesas,r9a09g057-dmac # RZ/V2H(P)
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Control and channel register block
|
||||
- description: DMA extended resource selector block
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 17
|
||||
@ -52,6 +56,7 @@ properties:
|
||||
items:
|
||||
- description: DMA main clock
|
||||
- description: DMA register access clock
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@ -61,10 +66,10 @@ properties:
|
||||
'#dma-cells':
|
||||
const: 1
|
||||
description:
|
||||
The cell specifies the encoded MID/RID values of the DMAC port
|
||||
connected to the DMA client and the slave channel configuration
|
||||
parameters.
|
||||
bits[0:9] - Specifies MID/RID value
|
||||
The cell specifies the encoded MID/RID or the REQ No values of
|
||||
the DMAC port connected to the DMA client and the slave channel
|
||||
configuration parameters.
|
||||
bits[0:9] - Specifies the MID/RID or the REQ No value
|
||||
bit[10] - Specifies DMA request high enable (HIEN)
|
||||
bit[11] - Specifies DMA request detection type (LVL)
|
||||
bits[12:14] - Specifies DMAACK output mode (AM)
|
||||
@ -80,12 +85,26 @@ properties:
|
||||
items:
|
||||
- description: Reset for DMA ARESETN reset terminal
|
||||
- description: Reset for DMA RST_ASYNC reset terminal
|
||||
minItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: arst
|
||||
- const: rst_async
|
||||
|
||||
renesas,icu:
|
||||
description:
|
||||
It must contain the phandle to the ICU and the index of the DMAC as seen
|
||||
from the ICU.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: Phandle to the ICU node.
|
||||
- description:
|
||||
The number of the DMAC as seen from the ICU, i.e. parameter k from
|
||||
register ICU_DMkSELy. This may differ from the actual DMAC instance
|
||||
number.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -98,13 +117,25 @@ allOf:
|
||||
- $ref: dma-controller.yaml#
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,r7s72100-dmac
|
||||
- renesas,r9a07g043-dmac
|
||||
- renesas,r9a07g044-dmac
|
||||
- renesas,r9a07g054-dmac
|
||||
- renesas,r9a08g045-dmac
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
clocks:
|
||||
minItems: 2
|
||||
resets:
|
||||
minItems: 2
|
||||
|
||||
renesas,icu: false
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
@ -112,6 +143,46 @@ allOf:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r7s72100-dmac
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
clocks: false
|
||||
clock-names: false
|
||||
power-domains: false
|
||||
resets: false
|
||||
reset-names: false
|
||||
renesas,icu: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r9a09g057-dmac
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
clocks:
|
||||
maxItems: 1
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clock-names: false
|
||||
reset-names: false
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- power-domains
|
||||
- renesas,icu
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -97,7 +97,10 @@ properties:
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: module reset
|
||||
- description:
|
||||
Module reset. This property is optional for controllers in Tegra194,
|
||||
Tegra234 etc where an internal software reset is available as an
|
||||
alternative.
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
@ -116,6 +119,13 @@ properties:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml
|
||||
- if:
|
||||
@ -169,6 +179,18 @@ allOf:
|
||||
properties:
|
||||
power-domains: false
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra194-i2c
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@ -25,6 +25,7 @@ description: |
|
||||
* https://www.analog.com/en/products/ad7386-4.html
|
||||
* https://www.analog.com/en/products/ad7387-4.html
|
||||
* https://www.analog.com/en/products/ad7388-4.html
|
||||
* https://www.analog.com/en/products/ad7389-4.html
|
||||
* https://www.analog.com/en/products/adaq4370-4.html
|
||||
* https://www.analog.com/en/products/adaq4380-4.html
|
||||
* https://www.analog.com/en/products/adaq4381-4.html
|
||||
@ -49,6 +50,7 @@ properties:
|
||||
- adi,ad7386-4
|
||||
- adi,ad7387-4
|
||||
- adi,ad7388-4
|
||||
- adi,ad7389-4
|
||||
- adi,adaq4370-4
|
||||
- adi,adaq4380-4
|
||||
- adi,adaq4381-4
|
||||
@ -213,6 +215,15 @@ allOf:
|
||||
properties:
|
||||
refin-supply: false
|
||||
|
||||
# adi,ad7389-4 is internal reference only
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: adi,ad7389-4
|
||||
then:
|
||||
properties:
|
||||
refio-supply: false
|
||||
|
||||
# adaq devices need more supplies and using channel to declare gain property
|
||||
# only applies to adaq devices
|
||||
- if:
|
||||
|
||||
@ -17,7 +17,9 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- adi,ad7091
|
||||
- adi,ad7091r
|
||||
- adi,ad7273
|
||||
@ -46,6 +48,9 @@ properties:
|
||||
- ti,ads7867
|
||||
- ti,ads7868
|
||||
- lltc,ltc2314-14
|
||||
- items:
|
||||
- const: rohm,bu79100g
|
||||
- const: ti,ads7866
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -45,6 +45,14 @@ properties:
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
'#trigger-source-cells':
|
||||
description: |
|
||||
Cell indicates the output signal: 0 = BUSY, 1 = FIRSTDATA.
|
||||
|
||||
For convenience, macros for these values are available in
|
||||
dt-bindings/iio/adc/adi,ad7606.h.
|
||||
const: 1
|
||||
|
||||
# According to the datasheet, "Data is clocked in from SDI on the falling
|
||||
# edge of SCLK, while data is clocked out on DOUTA on the rising edge of
|
||||
# SCLK". Also, even if not stated textually in the datasheet, it is made
|
||||
|
||||
@ -23,6 +23,7 @@ properties:
|
||||
- amlogic,meson8m2-saradc
|
||||
- amlogic,meson-gxbb-saradc
|
||||
- amlogic,meson-gxl-saradc
|
||||
- amlogic,meson-gxlx-saradc
|
||||
- amlogic,meson-gxm-saradc
|
||||
- amlogic,meson-axg-saradc
|
||||
- amlogic,meson-g12a-saradc
|
||||
|
||||
@ -34,6 +34,7 @@ properties:
|
||||
- const: mediatek,mt2701-auxadc
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt6893-auxadc
|
||||
- mediatek,mt8183-auxadc
|
||||
- mediatek,mt8186-auxadc
|
||||
- mediatek,mt8188-auxadc
|
||||
|
||||
@ -32,6 +32,9 @@ properties:
|
||||
spi-max-frequency:
|
||||
maximum: 20000000
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: |
|
||||
Phandle and clock identifier for external sampling clock.
|
||||
@ -71,6 +74,7 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -80,6 +84,7 @@ examples:
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <15 2>;
|
||||
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
spi-max-frequency = <20000000>;
|
||||
microchip,device-addr = <0>;
|
||||
vref-supply = <&vref_reg>;
|
||||
|
||||
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/adc/nuvoton,nct7201.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Nuvoton nct7201 and similar ADCs
|
||||
|
||||
maintainers:
|
||||
- Eason Yang <j2anfernee@gmail.com>
|
||||
|
||||
description: |
|
||||
The NCT7201/NCT7202 is a Nuvoton Hardware Monitor IC, contains up to 12
|
||||
voltage monitoring channels, with SMBus interface, and up to 4 sets SMBus
|
||||
address selection by ADDR connection. It also provides ALERT# signal for
|
||||
event notification and reset input RSTIN# to recover it from a fault
|
||||
condition.
|
||||
|
||||
NCT7201 contains 8 voltage monitor inputs (VIN1~VIN8).
|
||||
NCT7202 contains 12 voltage monitor inputs (VIN1~VIN12).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nuvoton,nct7201
|
||||
- nuvoton,nct7202
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
vdd-supply:
|
||||
description:
|
||||
A 3.3V to supply that powers the chip.
|
||||
|
||||
vref-supply:
|
||||
description:
|
||||
The regulator supply for the ADC reference voltage.
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
adc@1d {
|
||||
compatible = "nuvoton,nct7202";
|
||||
reg = <0x1d>;
|
||||
vdd-supply = <&vdd>;
|
||||
vref-supply = <&vref>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
...
|
||||
69
Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml
Normal file
69
Documentation/devicetree/bindings/iio/adc/rohm,bd79104.yaml
Normal file
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/adc/rohm,bd79104.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROHM Semiconductor BD79104 ADC
|
||||
|
||||
maintainers:
|
||||
- Matti Vaittinen <mazziesaccount@gmail.com>
|
||||
|
||||
description: |
|
||||
12 bit SPI ADC with 8 channels.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rohm,bd79104
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
vdd-supply: true
|
||||
iovdd-supply: true
|
||||
|
||||
# The component data-sheet says the frequency is 20M. I, however, found
|
||||
# that the ROHM evaluation board BD79104FV-EVK-001 had problems with 20M.
|
||||
# I have successfully used it with 4M. My _assumption_ is that this is not
|
||||
# the limitation of the component itself, but a limitation of the EVK.
|
||||
spi-max-frequency:
|
||||
maximum: 20000000
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
spi-cpha: true
|
||||
spi-cpol: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vdd-supply
|
||||
- iovdd-supply
|
||||
- spi-cpha
|
||||
- spi-cpol
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
adc@0 {
|
||||
compatible = "rohm,bd79104";
|
||||
reg = <0>;
|
||||
vdd-supply = <&vdd_supply>;
|
||||
iovdd-supply = <&iovdd_supply>;
|
||||
spi-max-frequency = <4000000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
...
|
||||
114
Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml
Normal file
114
Documentation/devicetree/bindings/iio/adc/rohm,bd79124.yaml
Normal file
@ -0,0 +1,114 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/adc/rohm,bd79124.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROHM BD79124 ADC/GPO
|
||||
|
||||
maintainers:
|
||||
- Matti Vaittinen <mazziesaccount@gmail.com>
|
||||
|
||||
description: |
|
||||
The ROHM BD79124 is a 12-bit, 8-channel, SAR ADC. The ADC supports
|
||||
an automatic measurement mode, with an alarm interrupt for out-of-window
|
||||
measurements. ADC input pins can be also configured as general purpose
|
||||
outputs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rohm,bd79124
|
||||
|
||||
reg:
|
||||
description:
|
||||
I2C slave address.
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 1
|
||||
description:
|
||||
The pin number.
|
||||
|
||||
vdd-supply: true
|
||||
|
||||
iovdd-supply: true
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^channel@[0-7]+$":
|
||||
type: object
|
||||
$ref: /schemas/iio/adc/adc.yaml#
|
||||
description: Represents ADC channel.
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: AIN pin number
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- iovdd-supply
|
||||
- vdd-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
adc: adc@10 {
|
||||
compatible = "rohm,bd79124";
|
||||
reg = <0x10>;
|
||||
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <29 8>;
|
||||
|
||||
vdd-supply = <&dummyreg>;
|
||||
iovdd-supply = <&dummyreg>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
channel@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
channel@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
channel@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
channel@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/chemical/winsen,mhz19b.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MHZ19B CO2 sensor
|
||||
|
||||
maintainers:
|
||||
- Gyeyoung Baek <gye976@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: winsen,mhz19b
|
||||
|
||||
vin-supply:
|
||||
description: Regulator that provides power to the sensor
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- vin-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
serial {
|
||||
co2-sensor {
|
||||
compatible = "winsen,mhz19b";
|
||||
vin-supply = <&vdd>;
|
||||
};
|
||||
};
|
||||
...
|
||||
100
Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml
Normal file
100
Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml
Normal file
@ -0,0 +1,100 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/iio/dac/adi,ad3530r.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Analog Devices AD3530R and Similar DACs
|
||||
|
||||
maintainers:
|
||||
- Kim Seer Paller <kimseer.paller@analog.com>
|
||||
|
||||
description: |
|
||||
The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power,
|
||||
16-bit, buffered voltage output digital-to-analog converters (DACs) with
|
||||
software-programmable gain controls, providing full-scale output spans of 2.5V
|
||||
or 5V for reference voltages of 2.5V. These devices operate from a single 2.7V
|
||||
to 5.5V supply and are guaranteed monotonic by design. The "R" variants
|
||||
include a 2.5V, 5ppm/°C internal reference, which is disabled by default.
|
||||
Datasheet can be found here:
|
||||
https://www.analog.com/media/en/technical-documentation/data-sheets/ad3530_ad530r.pdf
|
||||
https://www.analog.com/media/en/technical-documentation/data-sheets/ad3531-ad3531r.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,ad3530
|
||||
- adi,ad3530r
|
||||
- adi,ad3531
|
||||
- adi,ad3531r
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
spi-max-frequency:
|
||||
maximum: 50000000
|
||||
|
||||
vdd-supply:
|
||||
description: Power Supply Input.
|
||||
|
||||
iovdd-supply:
|
||||
description: Digital Power Supply Input.
|
||||
|
||||
io-channels:
|
||||
description:
|
||||
ADC channel used to monitor internal die temperature, output voltages, and
|
||||
current of a selected channel via the MUXOUT pin.
|
||||
maxItems: 1
|
||||
|
||||
ref-supply:
|
||||
description:
|
||||
Reference Input/Output. The voltage at the REF pin sets the full-scale
|
||||
range of all channels. If not provided the internal reference is used and
|
||||
also provided on the VREF pin.
|
||||
|
||||
reset-gpios:
|
||||
description:
|
||||
Active low signal that is falling edge sensitive. When it is deasserted,
|
||||
the digital core initialization is performed and all DAC registers except
|
||||
the Interface Configuration A register are reset to their default values.
|
||||
maxItems: 1
|
||||
|
||||
ldac-gpios:
|
||||
description:
|
||||
LDAC pin to be used as a hardware trigger to update the DAC channels. If
|
||||
not present, the DAC channels are updated by Software LDAC.
|
||||
maxItems: 1
|
||||
|
||||
adi,range-double:
|
||||
description:
|
||||
Configure the output range for all channels. If the property is present,
|
||||
the output will range from 0V to 2Vref. If the property is not present,
|
||||
the output will range from 0V to Vref.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vdd-supply
|
||||
- iovdd-supply
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dac@0 {
|
||||
compatible = "adi,ad3530r";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
|
||||
vdd-supply = <&vdd>;
|
||||
iovdd-supply = <&iovdd>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -217,7 +217,7 @@ required:
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -27,6 +27,8 @@ properties:
|
||||
|
||||
vdrive-supply: true
|
||||
|
||||
vrefin-supply: true
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
@ -144,7 +144,7 @@ required:
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -124,7 +124,7 @@ required:
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -64,7 +64,7 @@ required:
|
||||
- reg
|
||||
- vdd-supply
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -5,19 +5,26 @@
|
||||
$id: http://devicetree.org/schemas/iio/dac/rohm,bd79703.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROHM BD79703 DAC device driver
|
||||
title: ROHM BD79700, BD79701, BD79702 and BD79703 DACs
|
||||
|
||||
maintainers:
|
||||
- Matti Vaittinen <mazziesaccount@gmail.com>
|
||||
|
||||
description: |
|
||||
The ROHM BD79703 is a 6 channel, 8-bit DAC.
|
||||
Datasheet can be found here:
|
||||
The ROHM BD7970[0,1,2,3] are 8-bit DACs. The BD79700 has 2 channels,
|
||||
BD79701 3 channels, BD79702 4 channels and BD79703 has 6 channels.
|
||||
Datasheets for BD79702 and BD79703 can be found from
|
||||
https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79702fv-lb_bd79703fv-lb-e.pdf
|
||||
and for the BD79700 and the BD79701 from
|
||||
https://fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79700fvm-lb_bd79701fvm-lb-e.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rohm,bd79703
|
||||
enum:
|
||||
- rohm,bd79700
|
||||
- rohm,bd79701
|
||||
- rohm,bd79702
|
||||
- rohm,bd79703
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -27,23 +34,35 @@ properties:
|
||||
|
||||
vfs-supply:
|
||||
description:
|
||||
The regulator to use as a full scale voltage. The voltage should be between 2.7V .. VCC
|
||||
The regulator to use as a full scale voltage. The voltage should be
|
||||
between 2.7V .. VCC. Not present on BD79700 and BD79701.
|
||||
|
||||
vcc-supply:
|
||||
description:
|
||||
The regulator supplying the operating voltage. Should be between 2.7V ... 5.5V
|
||||
The regulator supplying the operating voltage. Should be between
|
||||
2.7V ... 5.5V. Is used also as a Vfs on BD79700 and BD79701.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- spi-max-frequency
|
||||
- vfs-supply
|
||||
- vcc-supply
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rohm,bd79702
|
||||
- rohm,bd79703
|
||||
then:
|
||||
required:
|
||||
- vfs-supply
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -44,6 +44,24 @@ properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
adi,lpf-margin-mhz:
|
||||
description:
|
||||
Sets the minimum distance between the fundamental frequency of `rf_in`
|
||||
and the corner frequency of the low-pass, output filter when operated in
|
||||
'auto' mode. The selected low-pass corner frequency will be greater than,
|
||||
or equal to, `rf_in` + `lpf-margin-hz`. If not setting is found that
|
||||
satisfies this relationship the filter will be put into 'bypass'.
|
||||
default: 0
|
||||
|
||||
adi,hpf-margin-mhz:
|
||||
description:
|
||||
Sets the minimum distance between the fundamental frequency of `rf_in`
|
||||
and the corner frequency of the high-pass, input filter when operated in
|
||||
'auto' mode. The selected high-pass corner frequency will be less than,
|
||||
or equal to, `rf_in` - `hpf-margin-hz`. If not setting is found that
|
||||
satisfies this relationship the filter will be put into 'bypass'.
|
||||
default: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -61,6 +79,8 @@ examples:
|
||||
spi-max-frequency = <10000000>;
|
||||
clocks = <&admv8818_rfin>;
|
||||
clock-names = "rf_in";
|
||||
adi,lpf-margin-mhz = <300>;
|
||||
adi,hpf-margin-mhz = <300>;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
||||
@ -53,7 +53,7 @@ required:
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -39,7 +39,16 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum:
|
||||
- INT1
|
||||
- INT2
|
||||
|
||||
drive-open-drain:
|
||||
type: boolean
|
||||
@ -76,6 +85,7 @@ examples:
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-names = "INT1";
|
||||
vdd-supply = <&vdd>;
|
||||
vddio-supply = <&vddio>;
|
||||
};
|
||||
@ -95,6 +105,7 @@ examples:
|
||||
spi-cpol;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-names = "INT1";
|
||||
vdd-supply = <&vdd>;
|
||||
vddio-supply = <&vddio>;
|
||||
};
|
||||
|
||||
@ -24,6 +24,10 @@ properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO connected to the DVI reset pin (active low)
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -32,6 +36,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -39,6 +44,7 @@ examples:
|
||||
light-sensor@23 {
|
||||
compatible = "rohm,bh1750";
|
||||
reg = <0x23>;
|
||||
reset-gpios = <&gpio2 17 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -102,7 +102,7 @@ required:
|
||||
allOf:
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
dependentSchemas:
|
||||
honeywell,pmin-pascal:
|
||||
|
||||
@ -115,7 +115,7 @@ allOf:
|
||||
honeywell,pmin-pascal: false
|
||||
honeywell,pmax-pascal: false
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -86,13 +86,13 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
|
||||
|
||||
snoc: interconnect@580000 {
|
||||
interconnect@580000 {
|
||||
compatible = "qcom,msm8953-snoc";
|
||||
reg = <0x580000 0x16080>;
|
||||
|
||||
#interconnect-cells = <2>;
|
||||
|
||||
snoc_mm: interconnect-snoc {
|
||||
interconnect-snoc {
|
||||
compatible = "qcom,msm8953-snoc-mm";
|
||||
|
||||
#interconnect-cells = <2>;
|
||||
|
||||
@ -52,7 +52,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
bimc: interconnect@fc380000 {
|
||||
interconnect@fc380000 {
|
||||
reg = <0xfc380000 0x6a000>;
|
||||
compatible = "qcom,msm8974-bimc";
|
||||
#interconnect-cells = <1>;
|
||||
|
||||
@ -28,6 +28,7 @@ properties:
|
||||
- const: qcom,osm-l3
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sa8775p-epss-l3
|
||||
- qcom,sc7280-epss-l3
|
||||
- qcom,sc8280xp-epss-l3
|
||||
- qcom,sm6375-cpucp-l3
|
||||
|
||||
@ -43,7 +43,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
bimc: interconnect@400000 {
|
||||
interconnect@400000 {
|
||||
compatible = "qcom,msm8916-bimc";
|
||||
reg = <0x00400000 0x62000>;
|
||||
#interconnect-cells = <1>;
|
||||
|
||||
@ -129,14 +129,14 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/interconnect/qcom,sdm845.h>
|
||||
|
||||
mem_noc: interconnect@1380000 {
|
||||
interconnect@1380000 {
|
||||
compatible = "qcom,sdm845-mem-noc";
|
||||
reg = <0x01380000 0x27200>;
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@1740000 {
|
||||
interconnect@1740000 {
|
||||
compatible = "qcom,sdm845-mmss-noc";
|
||||
reg = <0x01740000 0x1c1000>;
|
||||
#interconnect-cells = <1>;
|
||||
|
||||
120
Documentation/devicetree/bindings/leds/ti,tps61310.yaml
Normal file
120
Documentation/devicetree/bindings/leds/ti,tps61310.yaml
Normal file
@ -0,0 +1,120 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/leds/ti,tps61310.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments TPS6131X flash LED driver
|
||||
|
||||
maintainers:
|
||||
- Matthias Fend <matthias.fend@emfend.at>
|
||||
|
||||
description: |
|
||||
The TPS61310/TPS61311 is a flash LED driver with I2C interface.
|
||||
Its power stage is capable of supplying a maximum total current of roughly 1500mA.
|
||||
The TPS6131x provides three constant-current sinks, capable of sinking
|
||||
up to 2 x 400mA (LED1 and LED3) and 800mA (LED2) in flash mode.
|
||||
In torch mode, each sink (LED1, LED2, LED3) supports currents up to 175mA.
|
||||
Since the three current sinks share most of the control components such as
|
||||
flash timer, control logic, safety timer and the operating mode, they cannot
|
||||
be used completely independently of each other. Therefore, only one LED is
|
||||
supported, but the current sinks can be combined accordingly.
|
||||
|
||||
The data sheet can be found at:
|
||||
https://www.ti.com/lit/ds/symlink/tps61310.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- ti,tps61311
|
||||
- const: ti,tps61310
|
||||
- items:
|
||||
- const: ti,tps61310
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO connected to NRESET pin
|
||||
|
||||
ti,valley-current-limit:
|
||||
type: boolean
|
||||
description:
|
||||
Reduce the valley peak current limit from 1750mA to 1250mA (TPS61310) or
|
||||
from 2480mA to 1800mA (TPS61311).
|
||||
|
||||
led:
|
||||
type: object
|
||||
$ref: common.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
led-sources:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
enum: [1, 2, 3]
|
||||
|
||||
led-max-microamp:
|
||||
oneOf:
|
||||
- minimum: 50000
|
||||
maximum: 350000
|
||||
multipleOf: 50000
|
||||
- minimum: 25000
|
||||
maximum: 525000
|
||||
multipleOf: 25000
|
||||
|
||||
flash-max-microamp:
|
||||
oneOf:
|
||||
- minimum: 50000
|
||||
maximum: 800000
|
||||
multipleOf: 50000
|
||||
- minimum: 25000
|
||||
maximum: 1500000
|
||||
multipleOf: 25000
|
||||
|
||||
flash-max-timeout-us:
|
||||
enum: [ 5300, 10700, 16000, 21300, 26600, 32000, 37300, 68200, 71500,
|
||||
102200, 136300, 170400, 204500, 340800, 579300, 852000 ]
|
||||
|
||||
required:
|
||||
- led-sources
|
||||
- led-max-microamp
|
||||
- flash-max-microamp
|
||||
- flash-max-timeout-us
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- led
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led-controller@33 {
|
||||
compatible = "ti,tps61311", "ti,tps61310";
|
||||
reg = <0x33>;
|
||||
|
||||
reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
led {
|
||||
function = LED_FUNCTION_FLASH;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
led-sources = <1>, <2>, <3>;
|
||||
led-max-microamp = <525000>;
|
||||
flash-max-microamp = <1500000>;
|
||||
flash-max-timeout-us = <852000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- atmel,at91sam9260-gpbr
|
||||
- microchip,sama7d65-gpbr
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
-------------------------------
|
||||
BCM590xx Power Management Units
|
||||
-------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm59056"
|
||||
- reg: I2C slave address
|
||||
- interrupts: interrupt for the PMU. Generic interrupt client node bindings
|
||||
are described in interrupt-controller/interrupts.txt
|
||||
|
||||
------------------
|
||||
Voltage Regulators
|
||||
------------------
|
||||
|
||||
Optional child nodes:
|
||||
- regulators: container node for regulators following the generic
|
||||
regulator binding in regulator/regulator.txt
|
||||
|
||||
The valid regulator node names for BCM59056 are:
|
||||
rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo,
|
||||
mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo,
|
||||
csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
|
||||
gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6,
|
||||
vbus
|
||||
|
||||
Example:
|
||||
pmu: bcm59056@8 {
|
||||
compatible = "brcm,bcm59056";
|
||||
reg = <0x08>;
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
regulators {
|
||||
rfldo_reg: rfldo {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
...
|
||||
};
|
||||
};
|
||||
76
Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml
Normal file
76
Documentation/devicetree/bindings/mfd/brcm,bcm59056.yaml
Normal file
@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/brcm,bcm59056.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM590xx Power Management Units
|
||||
|
||||
maintainers:
|
||||
- Artur Weber <aweber.kernel@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm59054
|
||||
- brcm,bcm59056
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm59054
|
||||
then:
|
||||
properties:
|
||||
regulators:
|
||||
$ref: /schemas/regulator/brcm,bcm59054.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,bcm59056
|
||||
then:
|
||||
properties:
|
||||
regulators:
|
||||
$ref: /schemas/regulator/brcm,bcm59056.yaml#
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmic@8 {
|
||||
compatible = "brcm,bcm59056";
|
||||
reg = <0x08>;
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
regulators {
|
||||
rfldo {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -90,15 +90,6 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
led-1 {
|
||||
pwms = <&iqs620a_pwm 0 1000000>;
|
||||
max-brightness = <255>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
/* Single inductive button with bipolar dock/tablet-mode switch. */
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt6893-scpsys
|
||||
- mediatek,mt8167-scpsys
|
||||
- mediatek,mt8173-scpsys
|
||||
- mediatek,mt8183-scpsys
|
||||
|
||||
@ -76,12 +76,6 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ocelot_clock: ocelot-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@ -63,14 +63,3 @@ examples:
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ec 0 50000>;
|
||||
power-supply = <&backlight_regulator>;
|
||||
};
|
||||
|
||||
backlight_regulator: regulator-dummy {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "backlight";
|
||||
};
|
||||
|
||||
@ -4,19 +4,21 @@
|
||||
$id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROHM BD96801 Scalable Power Management Integrated Circuit
|
||||
title: ROHM BD96801/BD96805 Scalable Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
|
||||
|
||||
description:
|
||||
BD96801 is an automotive grade single-chip power management IC.
|
||||
It integrates 4 buck converters and 3 LDOs with safety features like
|
||||
BD96801 and BD96805 are automotive grade, single-chip power management ICs.
|
||||
They both integrate 4 buck converters and 3 LDOs with safety features like
|
||||
over-/under voltage and over current detection and a watchdog.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rohm,bd96801
|
||||
enum:
|
||||
- rohm,bd96801
|
||||
- rohm,bd96805
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
101
Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml
Normal file
101
Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml
Normal file
@ -0,0 +1,101 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/rohm,bd96802-pmic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROHM BD96802 / BD96806 Scalable Power Management Integrated Circuit
|
||||
|
||||
maintainers:
|
||||
- Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
|
||||
|
||||
description: |
|
||||
BD96802Qxx-C and BD96806 are automotive grade configurable Power Management
|
||||
Integrated Circuits supporting Functional Safety features for application
|
||||
processors, SoCs and FPGAs
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rohm,bd96802
|
||||
- rohm,bd96806
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
The PMIC provides intb and errb IRQ lines. The errb IRQ line is used
|
||||
for fatal IRQs which will cause the PMIC to shut down power outputs.
|
||||
In many systems this will shut down the SoC contolling the PMIC and
|
||||
connecting/handling the errb can be omitted. However, there are cases
|
||||
where the SoC is not powered by the PMIC or has a short time backup
|
||||
energy to handle shutdown of critical hardware. In that case it may be
|
||||
useful to connect the errb and handle errb events.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- enum: [intb, errb]
|
||||
- const: errb
|
||||
|
||||
regulators:
|
||||
$ref: ../regulator/rohm,bd96802-regulator.yaml
|
||||
description:
|
||||
List of child nodes that specify the regulators.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- regulators
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pmic: pmic@62 {
|
||||
reg = <0x62>;
|
||||
compatible = "rohm,bd96802";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "intb", "errb";
|
||||
|
||||
regulators {
|
||||
buck1 {
|
||||
regulator-name = "buck1";
|
||||
regulator-ramp-delay = <1250>;
|
||||
/* 0.5V min INITIAL - 150 mV tune */
|
||||
regulator-min-microvolt = <350000>;
|
||||
/* 3.3V + 150mV tune */
|
||||
regulator-max-microvolt = <3450000>;
|
||||
|
||||
/* These can be set only when PMIC is in STBY */
|
||||
rohm,initial-voltage-microvolt = <500000>;
|
||||
regulator-ov-error-microvolt = <230000>;
|
||||
regulator-uv-error-microvolt = <230000>;
|
||||
regulator-temp-protection-kelvin = <1>;
|
||||
regulator-temp-warn-kelvin = <0>;
|
||||
};
|
||||
buck2 {
|
||||
regulator-name = "buck2";
|
||||
regulator-min-microvolt = <350000>;
|
||||
regulator-max-microvolt = <3450000>;
|
||||
|
||||
rohm,initial-voltage-microvolt = <3000000>;
|
||||
regulator-ov-error-microvolt = <18000>;
|
||||
regulator-uv-error-microvolt = <18000>;
|
||||
regulator-temp-protection-kelvin = <1>;
|
||||
regulator-temp-warn-kelvin = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -20,6 +20,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s2mpg10-pmic
|
||||
- samsung,s2mps11-pmic
|
||||
- samsung,s2mps13-pmic
|
||||
- samsung,s2mps14-pmic
|
||||
@ -58,16 +59,39 @@ properties:
|
||||
reset (setting buck voltages to default values).
|
||||
type: boolean
|
||||
|
||||
system-power-controller: true
|
||||
|
||||
wakeup-source: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- regulators
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,s2mpg10-pmic
|
||||
then:
|
||||
properties:
|
||||
reg: false
|
||||
samsung,s2mps11-acokb-ground: false
|
||||
samsung,s2mps11-wrstbi-ground: false
|
||||
|
||||
oneOf:
|
||||
- required: [interrupts]
|
||||
- required: [interrupts-extended]
|
||||
|
||||
else:
|
||||
properties:
|
||||
system-power-controller: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -21,7 +21,12 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-lptimer
|
||||
oneOf:
|
||||
- items:
|
||||
- const: st,stm32mp25-lptimer
|
||||
- const: st,stm32-lptimer
|
||||
- items:
|
||||
- const: st,stm32-lptimer
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -48,13 +53,21 @@ properties:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
pwm:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-pwm-lp
|
||||
oneOf:
|
||||
- items:
|
||||
- const: st,stm32mp25-pwm-lp
|
||||
- const: st,stm32-pwm-lp
|
||||
- items:
|
||||
- const: st,stm32-pwm-lp
|
||||
|
||||
"#pwm-cells":
|
||||
const: 3
|
||||
@ -69,7 +82,12 @@ properties:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-lptimer-counter
|
||||
oneOf:
|
||||
- items:
|
||||
- const: st,stm32mp25-lptimer-counter
|
||||
- const: st,stm32-lptimer-counter
|
||||
- items:
|
||||
- const: st,stm32-lptimer-counter
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -80,7 +98,12 @@ properties:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-lptimer-timer
|
||||
oneOf:
|
||||
- items:
|
||||
- const: st,stm32mp25-lptimer-timer
|
||||
- const: st,stm32-lptimer-timer
|
||||
- items:
|
||||
- const: st,stm32-lptimer-timer
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -92,13 +115,18 @@ patternProperties:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32-lptimer-trigger
|
||||
oneOf:
|
||||
- items:
|
||||
- const: st,stm32mp25-lptimer-trigger
|
||||
- const: st,stm32-lptimer-trigger
|
||||
- items:
|
||||
- const: st,stm32-lptimer-trigger
|
||||
|
||||
reg:
|
||||
description: Identify trigger hardware block.
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 2
|
||||
maximum: 4
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -84,6 +84,7 @@ select:
|
||||
- mediatek,mt2701-pctl-a-syscfg
|
||||
- mediatek,mt2712-pctl-a-syscfg
|
||||
- mediatek,mt6397-pctl-pmic-syscfg
|
||||
- mediatek,mt7988-topmisc
|
||||
- mediatek,mt8135-pctl-a-syscfg
|
||||
- mediatek,mt8135-pctl-b-syscfg
|
||||
- mediatek,mt8173-pctl-a-syscfg
|
||||
@ -98,6 +99,8 @@ select:
|
||||
- mstar,msc313-pmsleep
|
||||
- nuvoton,ma35d1-sys
|
||||
- nuvoton,wpcm450-shm
|
||||
- qcom,apq8064-mmss-sfpb
|
||||
- qcom,apq8064-sps-sic
|
||||
- rockchip,px30-qos
|
||||
- rockchip,rk3036-qos
|
||||
- rockchip,rk3066-qos
|
||||
@ -187,9 +190,11 @@ properties:
|
||||
- mediatek,mt2701-pctl-a-syscfg
|
||||
- mediatek,mt2712-pctl-a-syscfg
|
||||
- mediatek,mt6397-pctl-pmic-syscfg
|
||||
- mediatek,mt7988-topmisc
|
||||
- mediatek,mt8135-pctl-a-syscfg
|
||||
- mediatek,mt8135-pctl-b-syscfg
|
||||
- mediatek,mt8173-pctl-a-syscfg
|
||||
- mediatek,mt8365-infracfg-nao
|
||||
- mediatek,mt8365-syscfg
|
||||
- microchip,lan966x-cpu-syscon
|
||||
- microchip,mpfs-sysreg-scb
|
||||
@ -201,6 +206,8 @@ properties:
|
||||
- mstar,msc313-pmsleep
|
||||
- nuvoton,ma35d1-sys
|
||||
- nuvoton,wpcm450-shm
|
||||
- qcom,apq8064-mmss-sfpb
|
||||
- qcom,apq8064-sps-sic
|
||||
- rockchip,px30-qos
|
||||
- rockchip,rk3036-qos
|
||||
- rockchip,rk3066-qos
|
||||
|
||||
26
Documentation/devicetree/bindings/mips/econet.yaml
Normal file
26
Documentation/devicetree/bindings/mips/econet.yaml
Normal file
@ -0,0 +1,26 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mips/econet.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: EcoNet MIPS SoCs
|
||||
|
||||
maintainers:
|
||||
- Caleb James DeLisle <cjd@cjdns.fr>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Boards with EcoNet EN751221 family SoC
|
||||
items:
|
||||
- enum:
|
||||
- smartfiber,xp8421-b
|
||||
- const: econet,en751221
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@ -25,6 +25,10 @@ properties:
|
||||
description:
|
||||
List of gpios used to control the multiplexer, least significant bit first.
|
||||
|
||||
mux-supply:
|
||||
description:
|
||||
Regulator to power on the multiplexer.
|
||||
|
||||
'#mux-control-cells':
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
|
||||
@ -0,0 +1,50 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/net/wireless/realtek,rtl8188e.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Realtek RTL8188E USB WiFi
|
||||
|
||||
maintainers:
|
||||
- J. Neuschäfer <j.ne@posteo.net>
|
||||
|
||||
description:
|
||||
Realtek RTL8188E is a family of USB-connected 2.4 GHz WiFi modules.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/usb/usb-device.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: usbbda,179 # RTL8188ETV
|
||||
|
||||
reg: true
|
||||
|
||||
vdd-supply:
|
||||
description:
|
||||
Regulator for the 3V3 supply.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- vdd-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
usb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wifi: wifi@1 {
|
||||
compatible = "usbbda,179";
|
||||
reg = <1>;
|
||||
vdd-supply = <&vcc3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/nvmem/apple,spmi-nvmem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SPMI NVMEM
|
||||
|
||||
description: Exports a series of SPMI registers as NVMEM cells
|
||||
|
||||
maintainers:
|
||||
- Sasha Finkelstein <fnkl.kernel@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: nvmem.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,maverick-pmic
|
||||
- apple,sera-pmic
|
||||
- apple,stowe-pmic
|
||||
- const: apple,spmi-nvmem
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
pmic@f {
|
||||
compatible = "apple,maverick-pmic", "apple,spmi-nvmem";
|
||||
reg = <0xf SPMI_USID>;
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
boot_stage: boot-stage@6001 {
|
||||
reg = <0x6001 0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -17,6 +17,10 @@ description: |
|
||||
implements its root ports. But the ATU found on most DesignWare
|
||||
PCIe host bridges is absent.
|
||||
|
||||
On systems derived from T602x, the PHY registers are in a region
|
||||
separate from the port registers. In that case, there is one PHY
|
||||
register range per port register range.
|
||||
|
||||
All root ports share a single ECAM space, but separate GPIOs are
|
||||
used to take the PCI devices on those ports out of reset. Therefore
|
||||
the standard "reset-gpios" and "max-link-speed" properties appear on
|
||||
@ -30,16 +34,18 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- apple,t8103-pcie
|
||||
- apple,t8112-pcie
|
||||
- apple,t6000-pcie
|
||||
- const: apple,pcie
|
||||
- const: apple,t6020-pcie
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
maxItems: 10
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
@ -50,6 +56,10 @@ properties:
|
||||
- const: port1
|
||||
- const: port2
|
||||
- const: port3
|
||||
- const: phy0
|
||||
- const: phy1
|
||||
- const: phy2
|
||||
- const: phy3
|
||||
|
||||
ranges:
|
||||
minItems: 2
|
||||
@ -98,6 +108,15 @@ allOf:
|
||||
maxItems: 5
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: apple,t6020-pcie
|
||||
then:
|
||||
properties:
|
||||
reg-names:
|
||||
minItems: 10
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
@ -224,8 +224,7 @@ examples:
|
||||
|
||||
/* PCIe endpoint */
|
||||
pci-ep@0,0 {
|
||||
assigned-addresses =
|
||||
<0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
|
||||
assigned-addresses = <0x82010000 0x0 0xf8000000 0x6 0x00000000 0x0 0x2000>;
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
compatible = "pci14e4,1688";
|
||||
};
|
||||
|
||||
100
Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml
Normal file
100
Documentation/devicetree/bindings/pci/marvell,armada8k-pcie.yaml
Normal file
@ -0,0 +1,100 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 7K/8K PCIe interface
|
||||
|
||||
maintainers:
|
||||
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
||||
|
||||
description:
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- marvell,armada8k-pcie
|
||||
required:
|
||||
- compatible
|
||||
|
||||
allOf:
|
||||
- $ref: snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- marvell,armada8k-pcie
|
||||
- const: snps,dw-pcie
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: ctrl
|
||||
- const: config
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: reg
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
marvell,reset-gpio:
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
|
||||
required:
|
||||
- interrupt-map
|
||||
- clocks
|
||||
- msi-parent
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
pcie@f2600000 {
|
||||
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
||||
reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;
|
||||
reg-names = "ctrl", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
msi-parent = <&gic_v2m0>;
|
||||
|
||||
ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>, /* downstream I/O */
|
||||
<0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&cpm_syscon0 1 13>;
|
||||
};
|
||||
...
|
||||
277
Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml
Normal file
277
Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml
Normal file
@ -0,0 +1,277 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell EBU PCIe interfaces
|
||||
|
||||
maintainers:
|
||||
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
||||
- Pali Rohár <pali@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,armada-370-pcie
|
||||
- marvell,armada-xp-pcie
|
||||
- marvell,dove-pcie
|
||||
- marvell,kirkwood-pcie
|
||||
|
||||
ranges:
|
||||
description: >
|
||||
The ranges describing the MMIO registers have the following layout:
|
||||
|
||||
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
|
||||
|
||||
where:
|
||||
|
||||
* r is a 32-bits value that gives the offset of the MMIO registers of
|
||||
this PCIe interface, from the base of the internal registers.
|
||||
|
||||
* s is a 32-bits value that give the size of this MMIO registers area.
|
||||
This range entry translates the '0x82000000 0 r' PCI address into the
|
||||
'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
|
||||
register window (as identified by MBUS_ID(0xf0, 0x01)).
|
||||
|
||||
The ranges describing the MBus windows have the following layout:
|
||||
|
||||
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
|
||||
|
||||
where:
|
||||
|
||||
* t is the type of the MBus window (as defined by the standard PCI DT
|
||||
bindings), 1 for I/O and 2 for memory.
|
||||
|
||||
* s is the PCI slot that corresponds to this PCIe interface
|
||||
|
||||
* w is the 'target ID' value for the MBus window
|
||||
|
||||
* a the 'attribute' value for the MBus window.
|
||||
|
||||
Since the location and size of the different MBus windows is not fixed in
|
||||
hardware, and only determined in runtime, those ranges cover the full first
|
||||
4 GB of the physical address space, and do not translate into a valid CPU
|
||||
address.
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'^pcie@':
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus-common.yaml#
|
||||
- $ref: /schemas/pci/pci-device.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: intx
|
||||
- const: error
|
||||
|
||||
reset-delay-us:
|
||||
default: 100000
|
||||
description: todo
|
||||
|
||||
marvell,pcie-port:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
description: todo
|
||||
|
||||
marvell,pcie-lane:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 3
|
||||
description: todo
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- assigned-addresses
|
||||
- clocks
|
||||
- interrupt-map
|
||||
- marvell,pcie-port
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@f001000000000000 {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
msi-parent = <&mpic>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
/* low-active PERST# reset on GPIO 25 */
|
||||
reset-gpios = <&gpio0 25 1>;
|
||||
/* wait 20ms for device settle after reset deassertion */
|
||||
reset-delay-us = <20000>;
|
||||
clocks = <&gateclk 5>;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 7>;
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 8>;
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 9>;
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -50,7 +50,7 @@ properties:
|
||||
items:
|
||||
pattern: '^fic[0-3]$'
|
||||
|
||||
dma-coherent: true
|
||||
dma-noncoherent: true
|
||||
|
||||
ranges:
|
||||
minItems: 1
|
||||
|
||||
@ -1,310 +0,0 @@
|
||||
* Marvell EBU PCIe interfaces
|
||||
|
||||
Mandatory properties:
|
||||
|
||||
- compatible: one of the following values:
|
||||
marvell,armada-370-pcie
|
||||
marvell,armada-xp-pcie
|
||||
marvell,dove-pcie
|
||||
marvell,kirkwood-pcie
|
||||
- #address-cells, set to <3>
|
||||
- #size-cells, set to <2>
|
||||
- #interrupt-cells, set to <1>
|
||||
- bus-range: PCI bus numbers covered
|
||||
- device_type, set to "pci"
|
||||
- ranges: ranges describing the MMIO registers to control the PCIe
|
||||
interfaces, and ranges describing the MBus windows needed to access
|
||||
the memory and I/O regions of each PCIe interface.
|
||||
- msi-parent: Link to the hardware entity that serves as the Message
|
||||
Signaled Interrupt controller for this PCI controller.
|
||||
|
||||
The ranges describing the MMIO registers have the following layout:
|
||||
|
||||
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
|
||||
|
||||
where:
|
||||
|
||||
* r is a 32-bits value that gives the offset of the MMIO
|
||||
registers of this PCIe interface, from the base of the internal
|
||||
registers.
|
||||
|
||||
* s is a 32-bits value that give the size of this MMIO
|
||||
registers area. This range entry translates the '0x82000000 0 r' PCI
|
||||
address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
|
||||
of the internal register window (as identified by MBUS_ID(0xf0,
|
||||
0x01)).
|
||||
|
||||
The ranges describing the MBus windows have the following layout:
|
||||
|
||||
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
|
||||
|
||||
where:
|
||||
|
||||
* t is the type of the MBus window (as defined by the standard PCI DT
|
||||
bindings), 1 for I/O and 2 for memory.
|
||||
|
||||
* s is the PCI slot that corresponds to this PCIe interface
|
||||
|
||||
* w is the 'target ID' value for the MBus window
|
||||
|
||||
* a the 'attribute' value for the MBus window.
|
||||
|
||||
Since the location and size of the different MBus windows is not fixed in
|
||||
hardware, and only determined in runtime, those ranges cover the full first
|
||||
4 GB of the physical address space, and do not translate into a valid CPU
|
||||
address.
|
||||
|
||||
In addition, the device tree node must have sub-nodes describing each
|
||||
PCIe interface, having the following mandatory properties:
|
||||
|
||||
- reg: used only for interrupt mapping, so only the first four bytes
|
||||
are used to refer to the correct bus number and device number.
|
||||
- assigned-addresses: reference to the MMIO registers used to control
|
||||
this PCIe interface.
|
||||
- clocks: the clock associated to this PCIe interface
|
||||
- marvell,pcie-port: the physical PCIe port number
|
||||
- status: either "disabled" or "okay"
|
||||
- device_type, set to "pci"
|
||||
- #address-cells, set to <3>
|
||||
- #size-cells, set to <2>
|
||||
- #interrupt-cells, set to <1>
|
||||
- ranges, translating the MBus windows ranges of the parent node into
|
||||
standard PCI addresses.
|
||||
- interrupt-map-mask and interrupt-map, standard PCI properties to
|
||||
define the mapping of the PCIe interface to interrupt numbers.
|
||||
|
||||
and the following optional properties:
|
||||
- marvell,pcie-lane: the physical PCIe lane number, for ports having
|
||||
multiple lanes. If this property is not found, we assume that the
|
||||
value is 0.
|
||||
- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
|
||||
- reset-gpios: optional GPIO to PERST#
|
||||
- reset-delay-us: delay in us to wait after reset de-assertion, if not
|
||||
specified will default to 100ms, as required by the PCIe specification.
|
||||
- interrupt-names: list of interrupt names, supported are:
|
||||
- "intx" - interrupt line triggered by one of the legacy interrupt
|
||||
- interrupts or interrupts-extended: List of the interrupt sources which
|
||||
corresponding to the "interrupt-names". If non-empty then also additional
|
||||
'interrupt-controller' subnode must be defined.
|
||||
|
||||
Example:
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
msi-parent = <&mpic>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
/* low-active PERST# reset on GPIO 25 */
|
||||
reset-gpios = <&gpio0 25 1>;
|
||||
/* wait 20ms for device settle after reset deassertion */
|
||||
reset-delay-us = <20000>;
|
||||
clocks = <&gateclk 5>;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 7>;
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 8>;
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 9>;
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 11>;
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 12>;
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 26>;
|
||||
};
|
||||
|
||||
pcie@a,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&gateclk 27>;
|
||||
};
|
||||
};
|
||||
@ -74,7 +74,7 @@ properties:
|
||||
|
||||
reset-gpios:
|
||||
description: Must contain a phandle to a GPIO controller followed by GPIO
|
||||
that is being used as PERST input signal. Please refer to pci.txt.
|
||||
that is being used as PERST input signal.
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
|
||||
@ -1,48 +0,0 @@
|
||||
* Marvell Armada 7K/8K PCIe interface
|
||||
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,armada8k-pcie"
|
||||
- reg: must contain two register regions
|
||||
- the control register region
|
||||
- the config space region
|
||||
- reg-names:
|
||||
- "ctrl" for the control register region
|
||||
- "config" for the config space region
|
||||
- interrupts: Interrupt specifier for the PCIe controller
|
||||
- clocks: reference to the PCIe controller clocks
|
||||
- clock-names: mandatory if there is a second clock, in this case the
|
||||
name must be "core" for the first clock and "reg" for the second
|
||||
one
|
||||
|
||||
Optional properties:
|
||||
- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
|
||||
Either 1, 2 or 4 PHYs might be needed depending on the number of
|
||||
PCIe lanes.
|
||||
- phy-names: names of the PHYs corresponding to the number of lanes.
|
||||
Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
|
||||
2 PHYs.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@f2600000 {
|
||||
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
||||
reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
|
||||
reg-names = "ctrl", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
|
||||
bus-range = <0 0xff>;
|
||||
ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
|
||||
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-lanes = <1>;
|
||||
clocks = <&cpm_syscon0 1 13>;
|
||||
};
|
||||
@ -1,171 +0,0 @@
|
||||
This document describes the generic device tree binding for describing the
|
||||
relationship between PCI(e) devices and IOMMU(s).
|
||||
|
||||
Each PCI(e) device under a root complex is uniquely identified by its Requester
|
||||
ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
|
||||
Function number.
|
||||
|
||||
For the purpose of this document, when treated as a numeric value, a RID is
|
||||
formatted such that:
|
||||
|
||||
* Bits [15:8] are the Bus number.
|
||||
* Bits [7:3] are the Device number.
|
||||
* Bits [2:0] are the Function number.
|
||||
* Any other bits required for padding must be zero.
|
||||
|
||||
IOMMUs may distinguish PCI devices through sideband data derived from the
|
||||
Requester ID. While a given PCI device can only master through one IOMMU, a
|
||||
root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
|
||||
bus).
|
||||
|
||||
The generic 'iommus' property is insufficient to describe this relationship,
|
||||
and a mechanism is required to map from a PCI device to its IOMMU and sideband
|
||||
data.
|
||||
|
||||
For generic IOMMU bindings, see
|
||||
Documentation/devicetree/bindings/iommu/iommu.txt.
|
||||
|
||||
|
||||
PCI root complex
|
||||
================
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
|
||||
- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
|
||||
data.
|
||||
|
||||
The property is an arbitrary number of tuples of
|
||||
(rid-base,iommu,iommu-base,length).
|
||||
|
||||
Any RID r in the interval [rid-base, rid-base + length) is associated with
|
||||
the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
|
||||
|
||||
- iommu-map-mask: A mask to be applied to each Requester ID prior to being
|
||||
mapped to an IOMMU specifier per the iommu-map property.
|
||||
|
||||
|
||||
Example (1)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the IOMMU is the RID,
|
||||
* identity-mapped.
|
||||
*/
|
||||
iommu-map = <0x0 &iommu 0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (2)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the IOMMU is the RID with the
|
||||
* function bits masked out.
|
||||
*/
|
||||
iommu-map = <0x0 &iommu 0x0 0x10000>;
|
||||
iommu-map-mask = <0xfff8>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (3)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the IOMMU is the RID,
|
||||
* but the high bits of the bus number are flipped.
|
||||
*/
|
||||
iommu-map = <0x0000 &iommu 0x8000 0x8000>,
|
||||
<0x8000 &iommu 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (4)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
iommu_a: iommu@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
iommu_b: iommu@b {
|
||||
reg = <0xb 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
iommu_c: iommu@c {
|
||||
reg = <0xc 0x1>;
|
||||
compatible = "vendor,some-iommu";
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* Devices with bus number 0-127 are mastered via IOMMU
|
||||
* a, with sideband data being RID[14:0].
|
||||
* Devices with bus number 128-255 are mastered via
|
||||
* IOMMU b, with sideband data being RID[14:0].
|
||||
* No devices master via IOMMU c.
|
||||
*/
|
||||
iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
|
||||
<0x8000 &iommu_b 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
@ -1,220 +0,0 @@
|
||||
This document describes the generic device tree binding for describing the
|
||||
relationship between PCI devices and MSI controllers.
|
||||
|
||||
Each PCI device under a root complex is uniquely identified by its Requester ID
|
||||
(AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
|
||||
Function number.
|
||||
|
||||
For the purpose of this document, when treated as a numeric value, a RID is
|
||||
formatted such that:
|
||||
|
||||
* Bits [15:8] are the Bus number.
|
||||
* Bits [7:3] are the Device number.
|
||||
* Bits [2:0] are the Function number.
|
||||
* Any other bits required for padding must be zero.
|
||||
|
||||
MSIs may be distinguished in part through the use of sideband data accompanying
|
||||
writes. In the case of PCI devices, this sideband data may be derived from the
|
||||
Requester ID. A mechanism is required to associate a device with both the MSI
|
||||
controllers it can address, and the sideband data that will be associated with
|
||||
its writes to those controllers.
|
||||
|
||||
For generic MSI bindings, see
|
||||
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
|
||||
|
||||
|
||||
PCI root complex
|
||||
================
|
||||
|
||||
Optional properties
|
||||
-------------------
|
||||
|
||||
- msi-map: Maps a Requester ID to an MSI controller and associated
|
||||
msi-specifier data. The property is an arbitrary number of tuples of
|
||||
(rid-base,msi-controller,msi-base,length), where:
|
||||
|
||||
* rid-base is a single cell describing the first RID matched by the entry.
|
||||
|
||||
* msi-controller is a single phandle to an MSI controller
|
||||
|
||||
* msi-base is an msi-specifier describing the msi-specifier produced for the
|
||||
first RID matched by the entry.
|
||||
|
||||
* length is a single cell describing how many consecutive RIDs are matched
|
||||
following the rid-base.
|
||||
|
||||
Any RID r in the interval [rid-base, rid-base + length) is associated with
|
||||
the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
|
||||
|
||||
- msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
|
||||
to an msi-specifier per the msi-map property.
|
||||
|
||||
- msi-parent: Describes the MSI parent of the root complex itself. Where
|
||||
the root complex and MSI controller do not pass sideband data with MSI
|
||||
writes, this property may be used to describe the MSI controller(s)
|
||||
used by PCI devices under the root complex, if defined as such in the
|
||||
binding for the root complex.
|
||||
|
||||
|
||||
Example (1)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, identity-mapped.
|
||||
*/
|
||||
msi-map = <0x0 &msi_a 0x0 0x10000>,
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (2)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, masked to only the device and function bits.
|
||||
*/
|
||||
msi-map = <0x0 &msi_a 0x0 0x100>,
|
||||
msi-map-mask = <0xff>
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (3)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, but the high bit of the bus number is
|
||||
* ignored.
|
||||
*/
|
||||
msi-map = <0x0000 &msi 0x0000 0x8000>,
|
||||
<0x8000 &msi 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (4)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to the MSI controller is
|
||||
* the RID, but the high bit of the bus number is
|
||||
* negated.
|
||||
*/
|
||||
msi-map = <0x0000 &msi 0x8000 0x8000>,
|
||||
<0x8000 &msi 0x0000 0x8000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Example (5)
|
||||
===========
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
msi_a: msi-controller@a {
|
||||
reg = <0xa 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
msi_b: msi-controller@b {
|
||||
reg = <0xb 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
msi_c: msi-controller@c {
|
||||
reg = <0xc 0x1>;
|
||||
compatible = "vendor,some-controller";
|
||||
msi-controller;
|
||||
#msi-cells = <1>;
|
||||
};
|
||||
|
||||
pci: pci@f {
|
||||
reg = <0xf 0x1>;
|
||||
compatible = "vendor,pcie-root-complex";
|
||||
device_type = "pci";
|
||||
|
||||
/*
|
||||
* The sideband data provided to MSI controller a is the
|
||||
* RID, but the high bit of the bus number is negated.
|
||||
* The sideband data provided to MSI controller b is the
|
||||
* RID, identity-mapped.
|
||||
* MSI controller c is not addressable.
|
||||
*/
|
||||
msi-map = <0x0000 &msi_a 0x8000 0x08000>,
|
||||
<0x8000 &msi_a 0x0000 0x08000>,
|
||||
<0x0000 &msi_b 0x0000 0x10000>;
|
||||
};
|
||||
};
|
||||
@ -1,84 +0,0 @@
|
||||
PCI bus bridges have standardized Device Tree bindings:
|
||||
|
||||
PCI Bus Binding to: IEEE Std 1275-1994
|
||||
https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
|
||||
|
||||
And for the interrupt mapping part:
|
||||
|
||||
Open Firmware Recommended Practice: Interrupt Mapping
|
||||
https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
|
||||
|
||||
Additionally to the properties specified in the above standards a host bridge
|
||||
driver implementation may support the following properties:
|
||||
|
||||
- linux,pci-domain:
|
||||
If present this property assigns a fixed PCI domain number to a host bridge,
|
||||
otherwise an unstable (across boots) unique number will be assigned.
|
||||
It is required to either not set this property at all or set it for all
|
||||
host bridges in the system, otherwise potentially conflicting domain numbers
|
||||
may be assigned to root buses behind different host bridges. The domain
|
||||
number for each host bridge in the system must be unique.
|
||||
- max-link-speed:
|
||||
If present this property specifies PCI gen for link capability. Host
|
||||
drivers could add this as a strategy to avoid unnecessary operation for
|
||||
unsupported link speed, for instance, trying to do training for
|
||||
unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
|
||||
for gen2, and '1' for gen1. Any other values are invalid.
|
||||
- reset-gpios:
|
||||
If present this property specifies PERST# GPIO. Host drivers can parse the
|
||||
GPIO and apply fundamental reset to endpoints.
|
||||
- supports-clkreq:
|
||||
If present this property specifies that CLKREQ signal routing exists from
|
||||
root port to downstream device and host bridge drivers can do programming
|
||||
which depends on CLKREQ signal existence. For example, programming root port
|
||||
not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
|
||||
|
||||
PCI-PCI Bridge properties
|
||||
-------------------------
|
||||
|
||||
PCIe root ports and switch ports may be described explicitly in the device
|
||||
tree, as children of the host bridge node. Even though those devices are
|
||||
discoverable by probing, it might be necessary to describe properties that
|
||||
aren't provided by standard PCIe capabilities.
|
||||
|
||||
Required properties:
|
||||
|
||||
- reg:
|
||||
Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
|
||||
document, it is a five-cell address encoded as (phys.hi phys.mid
|
||||
phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
|
||||
0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
|
||||
|
||||
The bus number is defined by firmware, through the standard bridge
|
||||
configuration mechanism. If this port is a switch port, then firmware
|
||||
allocates the bus number and writes it into the Secondary Bus Number
|
||||
register of the bridge directly above this port. Otherwise, the bus
|
||||
number of a root port is the first number in the bus-range property,
|
||||
defaulting to zero.
|
||||
|
||||
If firmware leaves the ARI Forwarding Enable bit set in the bridge
|
||||
above this port, then phys.hi contains the 8-bit function number as
|
||||
0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
|
||||
recommends that firmware only leaves ARI enabled when it knows that the
|
||||
OS is ARI-aware.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- external-facing:
|
||||
When present, the port is external-facing. All bridges and endpoints
|
||||
downstream of this port are external to the machine. The OS can, for
|
||||
example, use this information to identify devices that cannot be
|
||||
trusted with relaxed DMA protection, as users could easily attach
|
||||
malicious devices to this port.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@10000000 {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
...
|
||||
pcie@0008 {
|
||||
/* Root port 00:01.0 is external-facing */
|
||||
reg = <0x00000800 0 0 0 0>;
|
||||
external-facing;
|
||||
};
|
||||
};
|
||||
@ -45,9 +45,10 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -57,6 +58,7 @@ properties:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -129,7 +131,8 @@ examples:
|
||||
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
@ -137,7 +140,8 @@ examples:
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7";
|
||||
"msi7",
|
||||
"global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@ -54,9 +54,10 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -66,6 +67,7 @@ properties:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -149,9 +151,10 @@ examples:
|
||||
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
"msi4", "msi5", "msi6", "msi7", "global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
||||
@ -49,9 +49,10 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -61,6 +62,7 @@ properties:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -136,7 +138,8 @@ examples:
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0",
|
||||
"msi1",
|
||||
"msi2",
|
||||
@ -144,7 +147,8 @@ examples:
|
||||
"msi4",
|
||||
"msi5",
|
||||
"msi6",
|
||||
"msi7";
|
||||
"msi7",
|
||||
"global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
|
||||
@ -49,9 +49,10 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -61,6 +62,7 @@ properties:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -128,9 +130,10 @@ examples:
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
"msi4", "msi5", "msi6", "msi7", "global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
|
||||
@ -61,9 +61,10 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -73,6 +74,7 @@ properties:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -143,9 +145,10 @@ examples:
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
"msi4", "msi5", "msi6", "msi7", "global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
|
||||
@ -51,9 +51,10 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -63,6 +64,7 @@ properties:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
@ -132,9 +134,10 @@ examples:
|
||||
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
"msi4", "msi5", "msi6", "msi7", "global";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
||||
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq5018
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064-v2
|
||||
@ -168,6 +169,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq5018
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-ipq9574
|
||||
@ -175,14 +177,16 @@ allOf:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
maxItems: 6
|
||||
reg-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: dbi # DesignWare PCIe registers
|
||||
- const: elbi # External local bus interface registers
|
||||
- const: atu # ATU address space
|
||||
- const: parf # Qualcomm specific registers
|
||||
- const: config # PCIe configuration space
|
||||
- const: mhi # MHI registers
|
||||
|
||||
- if:
|
||||
properties:
|
||||
@ -322,6 +326,53 @@ allOf:
|
||||
- const: ahb # AHB reset
|
||||
- const: phy_ahb # PHY AHB reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq5018
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface # PCIe to SysNOC BIU clock
|
||||
- const: axi_m # AXI Master clock
|
||||
- const: axi_s # AXI Slave clock
|
||||
- const: ahb # AHB clock
|
||||
- const: aux # Auxiliary clock
|
||||
- const: axi_bridge # AXI bridge clock
|
||||
resets:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
reset-names:
|
||||
items:
|
||||
- const: pipe # PIPE reset
|
||||
- const: sleep # Sleep reset
|
||||
- const: sticky # Core sticky reset
|
||||
- const: axi_m # AXI master reset
|
||||
- const: axi_s # AXI slave reset
|
||||
- const: ahb # AHB reset
|
||||
- const: axi_m_sticky # AXI master sticky reset
|
||||
- const: axi_s_sticky # AXI slave sticky reset
|
||||
interrupts:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@ -562,6 +613,7 @@ allOf:
|
||||
enum:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq5018
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064v2
|
||||
- qcom,pcie-ipq8074
|
||||
@ -589,7 +641,11 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-msm8996
|
||||
- qcom,pcie-msm8998
|
||||
- qcom,pcie-sdm845
|
||||
then:
|
||||
oneOf:
|
||||
@ -602,8 +658,9 @@ allOf:
|
||||
- properties:
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
maxItems: 9
|
||||
interrupt-names:
|
||||
minItems: 8
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
@ -613,6 +670,7 @@ allOf:
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
- const: global
|
||||
|
||||
- if:
|
||||
properties:
|
||||
@ -622,11 +680,8 @@ allOf:
|
||||
- qcom,pcie-apq8064
|
||||
- qcom,pcie-apq8084
|
||||
- qcom,pcie-ipq4019
|
||||
- qcom,pcie-ipq6018
|
||||
- qcom,pcie-ipq8064
|
||||
- qcom,pcie-ipq8064-v2
|
||||
- qcom,pcie-ipq8074
|
||||
- qcom,pcie-ipq8074-gen3
|
||||
- qcom,pcie-qcs404
|
||||
then:
|
||||
properties:
|
||||
|
||||
@ -65,7 +65,11 @@ properties:
|
||||
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
|
||||
nf_err_rx, f_err_rx, radm_qoverflow
|
||||
- description:
|
||||
eDMA write channel 0 interrupt
|
||||
If the matching interrupt name is "msi", then this is the combined
|
||||
MSI line interrupt, which is to support MSI interrupts output to GIC
|
||||
controller via GIC SPI interrupt instead of GIC ITS interrupt.
|
||||
If the matching interrupt name is "dma0", then this is the eDMA write
|
||||
channel 0 interrupt.
|
||||
- description:
|
||||
eDMA write channel 1 interrupt
|
||||
- description:
|
||||
@ -81,7 +85,9 @@ properties:
|
||||
- const: msg
|
||||
- const: legacy
|
||||
- const: err
|
||||
- const: dma0
|
||||
- enum:
|
||||
- msi
|
||||
- dma0
|
||||
- const: dma1
|
||||
- const: dma2
|
||||
- const: dma3
|
||||
|
||||
@ -16,16 +16,14 @@ description: |+
|
||||
PCIe IP and thus inherits all the common properties defined in
|
||||
snps,dw-pcie.yaml.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: rockchip,rk3568-pcie
|
||||
- items:
|
||||
- enum:
|
||||
- rockchip,rk3562-pcie
|
||||
- rockchip,rk3576-pcie
|
||||
- rockchip,rk3588-pcie
|
||||
- const: rockchip,rk3568-pcie
|
||||
|
||||
@ -71,9 +69,59 @@ properties:
|
||||
|
||||
vpcie3v3-supply: true
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
- $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3562-pcie
|
||||
- rockchip,rk3576-pcie
|
||||
then:
|
||||
required:
|
||||
- msi-map
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,rk3562-pcie
|
||||
- rockchip,rk3576-pcie
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: sys
|
||||
- const: pmc
|
||||
- const: msg
|
||||
- const: legacy
|
||||
- const: err
|
||||
- const: msi
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 5
|
||||
interrupt-names:
|
||||
minItems: 5
|
||||
items:
|
||||
- const: sys
|
||||
- const: pmc
|
||||
- const: msg
|
||||
- const: legacy
|
||||
- const: err
|
||||
- const: dma0
|
||||
- const: dma1
|
||||
- const: dma2
|
||||
- const: dma3
|
||||
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
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Loading…
Reference in New Issue
Block a user