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drm/i915: set watermarks for third pipe on IVB

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The watermark reg for the third pipe is in an unusual offset; add
support for it and set watermarks for 3 pipe configs.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Jesse Barnes 2011-10-12 15:36:42 -07:00 committed by Keith Packard
parent d4270e57ef
commit d6c892df7e
2 changed files with 15 additions and 0 deletions
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1
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2435,6 +2435,7 @@
#define WM0_PIPE_CURSOR_MASK (0x1f) #define WM0_PIPE_CURSOR_MASK (0x1f)
#define WM0_PIPEB_ILK 0x45104 #define WM0_PIPEB_ILK 0x45104
#define WM0_PIPEC_IVB 0x45200
#define WM1_LP_ILK 0x45108 #define WM1_LP_ILK 0x45108
#define WM1_LP_SR_EN (1<<31) #define WM1_LP_SR_EN (1<<31)
#define WM1_LP_LATENCY_SHIFT 24 #define WM1_LP_LATENCY_SHIFT 24

14
drivers/gpu/drm/i915/intel_display.c
View File

@ -4540,6 +4540,20 @@ static void sandybridge_update_wm(struct drm_device *dev)
enabled |= 2; enabled |= 2;
} }
/* IVB has 3 pipes */
if (IS_IVYBRIDGE(dev) &&
g4x_compute_wm0(dev, 2,
&sandybridge_display_wm_info, latency,
&sandybridge_cursor_wm_info, latency,
&plane_wm, &cursor_wm)) {
I915_WRITE(WM0_PIPEC_IVB,
(plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
" plane %d, cursor: %d\n",
plane_wm, cursor_wm);
enabled |= 3;
}
/* /*
* Calculate and update the self-refresh watermark only when one * Calculate and update the self-refresh watermark only when one
* display plane is used. * display plane is used.