torvalds/linux
torvalds/linux
2
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-09-04 20:19:47 +08:00
Code

PCI: tegra: Use helper function for_each_child_of_node_scoped()

Browse Source 
The for_each_available_child_of_node_scoped() helper provides
a scope-based clean-up functionality to put the device_node
automatically, and as such, there is no need to call of_node_put()
directly.

Thus, use this helper to simplify the code.

Signed-off-by: Zhang Zekun <zhangzekun11@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240831040413.126417-7-zhangzekun11@huawei.com
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Zhang Zekun 2024-08-31 12:04:13 +08:00 committed by Krzysztof Wilczyński
parent f60b4e06a9
commit bffc72387a
No known key found for this signature in database
GPG Key ID: 7C64768D3DE334E7
1 changed files with 28 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
drivers/pci/controller/pci-tegra.c
View File

@ -2106,47 +2106,39 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
{
struct device *dev = pcie->dev;
struct device_node *np = dev->of_node, *port;
struct device_node *np = dev->of_node;
const struct tegra_pcie_soc *soc = pcie->soc;
u32 lanes = 0, mask = 0;
unsigned int lane = 0;
int err;
/* parse root ports */
for_each_child_of_node(np, port) {
for_each_child_of_node_scoped(np, port) {
struct tegra_pcie_port *rp;
unsigned int index;
u32 value;
char *label;
err = of_pci_get_devfn(port);
if (err < 0) {
dev_err(dev, "failed to parse address: %d\n", err);
goto err_node_put;
}
if (err < 0)
return dev_err_probe(dev, err, "failed to parse address\n");
index = PCI_SLOT(err);
if (index < 1 || index > soc->num_ports) {
dev_err(dev, "invalid port number: %d\n", index);
err = -EINVAL;
goto err_node_put;
}
if (index < 1 || index > soc->num_ports)
return dev_err_probe(dev, -EINVAL,
"invalid port number: %d\n", index);
index--;
err = of_property_read_u32(port, "nvidia,num-lanes", &value);
if (err < 0) {
dev_err(dev, "failed to parse # of lanes: %d\n",
err);
goto err_node_put;
}
if (err < 0)
return dev_err_probe(dev, err,
"failed to parse # of lanes\n");
if (value > 16) {
dev_err(dev, "invalid # of lanes: %u\n", value);
err = -EINVAL;
goto err_node_put;
}
if (value > 16)
return dev_err_probe(dev, -EINVAL,
"invalid # of lanes: %u\n", value);
lanes |= value << (index << 3);
@ -2159,16 +2151,12 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
lane += value;
rp = devm_kzalloc(dev, sizeof(*rp), GFP_KERNEL);
if (!rp) {
err = -ENOMEM;
goto err_node_put;
}
if (!rp)
return -ENOMEM;
err = of_address_to_resource(port, 0, &rp->regs);
if (err < 0) {
dev_err(dev, "failed to parse address: %d\n", err);
goto err_node_put;
}
if (err < 0)
return dev_err_probe(dev, err, "failed to parse address\n");
INIT_LIST_HEAD(&rp->list);
rp->index = index;
@ -2177,16 +2165,12 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
rp->np = port;
rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs);
if (IS_ERR(rp->base)) {
err = PTR_ERR(rp->base);
goto err_node_put;
}
if (IS_ERR(rp->base))
return PTR_ERR(rp->base);
label = devm_kasprintf(dev, GFP_KERNEL, "pex-reset-%u", index);
if (!label) {
err = -ENOMEM;
goto err_node_put;
}
if (!label)
return -ENOMEM;
/*
* Returns -ENOENT if reset-gpios property is not populated
@ -2199,34 +2183,26 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
GPIOD_OUT_LOW,
label);
if (IS_ERR(rp->reset_gpio)) {
if (PTR_ERR(rp->reset_gpio) == -ENOENT) {
if (PTR_ERR(rp->reset_gpio) == -ENOENT)
rp->reset_gpio = NULL;
} else {
dev_err(dev, "failed to get reset GPIO: %ld\n",
PTR_ERR(rp->reset_gpio));
err = PTR_ERR(rp->reset_gpio);
goto err_node_put;
}
else
return dev_err_probe(dev, PTR_ERR(rp->reset_gpio),
"failed to get reset GPIO\n");
}
list_add_tail(&rp->list, &pcie->ports);
}
err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
if (err < 0) {
dev_err(dev, "invalid lane configuration\n");
return err;
}
if (err < 0)
return dev_err_probe(dev, err,
"invalid lane configuration\n");
err = tegra_pcie_get_regulators(pcie, mask);
if (err < 0)
return err;
return 0;
err_node_put:
of_node_put(port);
return err;
}
/*