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RISC-V SpacemiT DT changes for 6.16
- Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKTBAABCgB9FiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmgkEphfFIAAAAAALgAo aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldEI1 QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRUQACgkQMarqR1lN u+2A0Q//fwnp36zuiqqYoZ7N9iFmLYjJlM9UEU2FSZ0/RWxL/1Y7ZBNAUajf7e7p N124gpRM5BJMyA+vHEJH1t8WblKoxwt9fjbn9QlcDYnoq5NuHjLkxwfySe+2V5tW kZoPrSwgZ3ODKn/HL+/ghT4ckNV6V+al6yh9x3Cv70ZYZjSOzRwshIf7JJBjzp9X y89QfuqRVT1YMdzCnWTMb7OVFM1fbPP88jjUR43VRieW9ER/8oaaNQNxg9r3wDFZ V6yOIhI5i43jDZcCKZLJCH+WjcIjDj8zQTbIvZOdZuFOR8FPPK2f+zvJ77C2eT6f fG6iB/yAWMFGNPQ064wWev43Ppq7KDkt2/qzTecBJRg6/+x6ILQy9TElkazkJDb2 EYIiucWoPqNMjSL3BRohJ+d6fSaFHaujhP5MGBYPVA6drAIYlwFPhH2HfebECUt9 4Ip9yzdTJAlXhvzlfXL6KBSCft2LinKVHEFvaNJKaZ5V6E93GP+lNv4rkgRoF+Hz uZsMpE2ex7uAskhFT4DQF7VAKaUvLSBUDVM8La1wy3jJFEl+w7YsSxYRTk3bRYt1 bSUdxCDDR+sD26ceMpiILdEy9cDE91B+ypUF1pu3C4P0vYEDi5pdIiuZmaYuAuXm SSC7ymRy2Ao0TGOtycRInTRtGzFnk9DZKLk+HU8rDJOq3WGpjFg= =yMSa -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmguShMACgkQmmx57+YA GNkNvQ/9EIjYie44k9ZyGxjQHuht6IayZHxyQvNVEp/Ef9l/S3M1PUMexgeHLG+0 8z8eITaP+9zz0wYA0mdoFdh8kdvHkGDVh8cKFrAQmXb1DMk/scQVfOShwh7F4wb4 bTohJIq4pVh/Y/b7Yz9kuCKZFmqx5Wpfg+s5iw9vR4SZ7kRCYnhdbBBXo9dOAFN/ KoGPQf6Pw3pKGMrxRifYyvrhJYuDZER3U+oERA+Rr2pB5tRf1TRHSvHNY//gBmVh bwh09t49pqkMWY0iJoJe7syIRjSLwzZF5HIPZYW8f33r/HKYYrS6quTuq9X3hnGI WYwBUftxIW9EU0vFQ/U+vZZRbArYfuydvpuh1iaHSo3ZBeu9cHQKH4HFQg/oUoaG rgvRKBd0Zb+bChvkpTj6hPrFht9m1IYhoDnazD9hhKXXHVSZsENm/3jhpUmQdOfW vpzW6AWUKCM7+ScFqMyvzTvCnuBdZNGzS1L9SWMwv8k6vs5mhTuO1Zqzli2WDEae D1MNzonF5NR91K4ayYMOz+HOZzQ6cOzJHUADd7Zk/zh0BClS0h6M88Dqql0C68ww 3Oeao9Z1e9BhO7Ubzh+/YV3fRff+/U1UZnRpFQnnqzbVw8YmAbivltJj86R7ftVp HnW5S9NLUz+UonGAwRRWck78I4/pRG2EbyQvFofta0U7ILePDYM= =09rm -----END PGP SIGNATURE----- Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux into soc/dt RISC-V SpacemiT DT changes for 6.16 - Add clock driver, fix for pinctrl/uart - Add gpio support, enable LED heartbeat * tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: add gpio LED for system heartbeat riscv: dts: spacemit: add gpio support for K1 SoC riscv: dts: spacemit: Acquire clocks for UART riscv: dts: spacemit: Acquire clocks for pinctrl riscv: dts: spacemit: Add clock tree for SpacemiT K1 dt-bindings: clock: spacemit: Add spacemit,k1-pll dt-bindings: soc: spacemit: Add spacemit,k1-syscon Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
ba32d96e90
50
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
Normal file
50
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
Normal file
@ -0,0 +1,50 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT K1 PLL
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maintainers:
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- Haylen Chu <heylenay@4d2.org>
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properties:
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compatible:
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const: spacemit,k1-pll
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reg:
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maxItems: 1
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clocks:
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description: External 24MHz oscillator
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spacemit,mpmu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL
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lock status.
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"#clock-cells":
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const: 1
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description:
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See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
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required:
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- compatible
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- reg
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- clocks
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- spacemit,mpmu
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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clock-controller@d4090000 {
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compatible = "spacemit,k1-pll";
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reg = <0xd4090000 0x1000>;
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clocks = <&vctcxo_24m>;
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spacemit,mpmu = <&sysctl_mpmu>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,80 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SpacemiT K1 SoC System Controller
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maintainers:
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- Haylen Chu <heylenay@4d2.org>
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description:
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System controllers found on SpacemiT K1 SoC, which are capable of
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clock, reset and power-management functions.
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properties:
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compatible:
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enum:
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- spacemit,k1-syscon-apbc
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- spacemit,k1-syscon-apmu
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- spacemit,k1-syscon-mpmu
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reg:
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maxItems: 1
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: osc
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- const: vctcxo_1m
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- const: vctcxo_3m
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- const: vctcxo_24m
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"#clock-cells":
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const: 1
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description:
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See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
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"#power-domain-cells":
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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- "#reset-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: spacemit,k1-syscon-apbc
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then:
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properties:
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"#power-domain-cells": false
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else:
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required:
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- "#power-domain-cells"
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additionalProperties: false
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examples:
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- |
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system-controller@d4050000 {
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compatible = "spacemit,k1-syscon-mpmu";
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reg = <0xd4050000 0x209c>;
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clocks = <&osc>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
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clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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@ -17,6 +17,17 @@
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chosen {
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stdout-path = "serial0";
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};
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leds {
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compatible = "gpio-leds";
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led1 {
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label = "sys-led";
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gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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};
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};
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&uart0 {
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@ -7,6 +7,9 @@
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#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
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/* Map GPIO pin to each bank's <index, offset> */
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#define K1_GPIO(x) (x / 32) (x % 32)
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&pinctrl {
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uart0_2_cfg: uart0-2-cfg {
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uart0-2-pins {
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@ -3,6 +3,8 @@
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* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
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*/
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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/dts-v1/;
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/ {
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#address-cells = <2>;
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@ -306,6 +308,36 @@
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};
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};
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clocks {
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vctcxo_1m: clock-1m {
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compatible = "fixed-clock";
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clock-frequency = <1000000>;
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clock-output-names = "vctcxo_1m";
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#clock-cells = <0>;
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};
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vctcxo_24m: clock-24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "vctcxo_24m";
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#clock-cells = <0>;
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};
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vctcxo_3m: clock-3m {
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compatible = "fixed-clock";
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clock-frequency = <3000000>;
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clock-output-names = "vctcxo_3m";
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#clock-cells = <0>;
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};
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osc_32k: clock-32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "osc_32k";
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#clock-cells = <0>;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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@ -314,11 +346,24 @@
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dma-noncoherent;
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ranges;
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syscon_apbc: system-controller@d4015000 {
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compatible = "spacemit,k1-syscon-apbc";
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reg = <0x0 0xd4015000 0x0 0x1000>;
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clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
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<&vctcxo_24m>;
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clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
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"vctcxo_24m";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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uart0: serial@d4017000 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017000 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART0>,
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<&syscon_apbc CLK_UART0_BUS>;
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clock-names = "core", "bus";
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interrupts = <42>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -327,8 +372,10 @@
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uart2: serial@d4017100 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017100 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART2>,
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<&syscon_apbc CLK_UART2_BUS>;
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clock-names = "core", "bus";
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interrupts = <44>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -337,8 +384,10 @@
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uart3: serial@d4017200 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017200 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART3>,
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<&syscon_apbc CLK_UART3_BUS>;
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clock-names = "core", "bus";
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interrupts = <45>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -347,8 +396,10 @@
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uart4: serial@d4017300 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017300 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART4>,
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<&syscon_apbc CLK_UART4_BUS>;
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clock-names = "core", "bus";
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interrupts = <46>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -357,8 +408,10 @@
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uart5: serial@d4017400 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017400 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART5>,
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<&syscon_apbc CLK_UART5_BUS>;
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clock-names = "core", "bus";
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interrupts = <47>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -367,8 +420,10 @@
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uart6: serial@d4017500 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017500 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART6>,
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<&syscon_apbc CLK_UART6_BUS>;
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clock-names = "core", "bus";
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interrupts = <48>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -377,8 +432,10 @@
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uart7: serial@d4017600 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017600 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART7>,
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<&syscon_apbc CLK_UART7_BUS>;
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clock-names = "core", "bus";
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interrupts = <49>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -387,8 +444,10 @@
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uart8: serial@d4017700 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017700 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART8>,
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<&syscon_apbc CLK_UART8_BUS>;
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clock-names = "core", "bus";
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interrupts = <50>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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@ -397,16 +456,71 @@
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uart9: serial@d4017800 {
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compatible = "spacemit,k1-uart", "intel,xscale-uart";
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reg = <0x0 0xd4017800 0x0 0x100>;
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clocks = <&syscon_apbc CLK_UART9>,
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<&syscon_apbc CLK_UART9_BUS>;
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clock-names = "core", "bus";
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interrupts = <51>;
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clock-frequency = <14857000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
|
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};
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|
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gpio: gpio@d4019000 {
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compatible = "spacemit,k1-gpio";
|
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reg = <0x0 0xd4019000 0x0 0x100>;
|
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clocks = <&syscon_apbc CLK_GPIO>,
|
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<&syscon_apbc CLK_GPIO_BUS>;
|
||||
clock-names = "core", "bus";
|
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gpio-controller;
|
||||
#gpio-cells = <3>;
|
||||
interrupts = <58>;
|
||||
interrupt-parent = <&plic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
gpio-ranges = <&pinctrl 0 0 0 32>,
|
||||
<&pinctrl 1 0 32 32>,
|
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<&pinctrl 2 0 64 32>,
|
||||
<&pinctrl 3 0 96 32>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@d401e000 {
|
||||
compatible = "spacemit,k1-pinctrl";
|
||||
reg = <0x0 0xd401e000 0x0 0x400>;
|
||||
clocks = <&syscon_apbc CLK_AIB>,
|
||||
<&syscon_apbc CLK_AIB_BUS>;
|
||||
clock-names = "func", "bus";
|
||||
};
|
||||
|
||||
syscon_mpmu: system-controller@d4050000 {
|
||||
compatible = "spacemit,k1-syscon-mpmu";
|
||||
reg = <0x0 0xd4050000 0x0 0x209c>;
|
||||
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
|
||||
<&vctcxo_24m>;
|
||||
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
|
||||
"vctcxo_24m";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pll: clock-controller@d4090000 {
|
||||
compatible = "spacemit,k1-pll";
|
||||
reg = <0x0 0xd4090000 0x0 0x1000>;
|
||||
clocks = <&vctcxo_24m>;
|
||||
spacemit,mpmu = <&syscon_mpmu>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
syscon_apmu: system-controller@d4282800 {
|
||||
compatible = "spacemit,k1-syscon-apmu";
|
||||
reg = <0x0 0xd4282800 0x0 0x400>;
|
||||
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
|
||||
<&vctcxo_24m>;
|
||||
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
|
||||
"vctcxo_24m";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
plic: interrupt-controller@e0000000 {
|
||||
|
||||
247
include/dt-bindings/clock/spacemit,k1-syscon.h
Normal file
247
include/dt-bindings/clock/spacemit,k1-syscon.h
Normal file
@ -0,0 +1,247 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
|
||||
#define _DT_BINDINGS_SPACEMIT_CCU_H_
|
||||
|
||||
/* APBS (PLL) clocks */
|
||||
#define CLK_PLL1 0
|
||||
#define CLK_PLL2 1
|
||||
#define CLK_PLL3 2
|
||||
#define CLK_PLL1_D2 3
|
||||
#define CLK_PLL1_D3 4
|
||||
#define CLK_PLL1_D4 5
|
||||
#define CLK_PLL1_D5 6
|
||||
#define CLK_PLL1_D6 7
|
||||
#define CLK_PLL1_D7 8
|
||||
#define CLK_PLL1_D8 9
|
||||
#define CLK_PLL1_D11 10
|
||||
#define CLK_PLL1_D13 11
|
||||
#define CLK_PLL1_D23 12
|
||||
#define CLK_PLL1_D64 13
|
||||
#define CLK_PLL1_D10_AUD 14
|
||||
#define CLK_PLL1_D100_AUD 15
|
||||
#define CLK_PLL2_D1 16
|
||||
#define CLK_PLL2_D2 17
|
||||
#define CLK_PLL2_D3 18
|
||||
#define CLK_PLL2_D4 19
|
||||
#define CLK_PLL2_D5 20
|
||||
#define CLK_PLL2_D6 21
|
||||
#define CLK_PLL2_D7 22
|
||||
#define CLK_PLL2_D8 23
|
||||
#define CLK_PLL3_D1 24
|
||||
#define CLK_PLL3_D2 25
|
||||
#define CLK_PLL3_D3 26
|
||||
#define CLK_PLL3_D4 27
|
||||
#define CLK_PLL3_D5 28
|
||||
#define CLK_PLL3_D6 29
|
||||
#define CLK_PLL3_D7 30
|
||||
#define CLK_PLL3_D8 31
|
||||
#define CLK_PLL3_80 32
|
||||
#define CLK_PLL3_40 33
|
||||
#define CLK_PLL3_20 34
|
||||
|
||||
/* MPMU clocks */
|
||||
#define CLK_PLL1_307P2 0
|
||||
#define CLK_PLL1_76P8 1
|
||||
#define CLK_PLL1_61P44 2
|
||||
#define CLK_PLL1_153P6 3
|
||||
#define CLK_PLL1_102P4 4
|
||||
#define CLK_PLL1_51P2 5
|
||||
#define CLK_PLL1_51P2_AP 6
|
||||
#define CLK_PLL1_57P6 7
|
||||
#define CLK_PLL1_25P6 8
|
||||
#define CLK_PLL1_12P8 9
|
||||
#define CLK_PLL1_12P8_WDT 10
|
||||
#define CLK_PLL1_6P4 11
|
||||
#define CLK_PLL1_3P2 12
|
||||
#define CLK_PLL1_1P6 13
|
||||
#define CLK_PLL1_0P8 14
|
||||
#define CLK_PLL1_409P6 15
|
||||
#define CLK_PLL1_204P8 16
|
||||
#define CLK_PLL1_491 17
|
||||
#define CLK_PLL1_245P76 18
|
||||
#define CLK_PLL1_614 19
|
||||
#define CLK_PLL1_47P26 20
|
||||
#define CLK_PLL1_31P5 21
|
||||
#define CLK_PLL1_819 22
|
||||
#define CLK_PLL1_1228 23
|
||||
#define CLK_SLOW_UART 24
|
||||
#define CLK_SLOW_UART1 25
|
||||
#define CLK_SLOW_UART2 26
|
||||
#define CLK_WDT 27
|
||||
#define CLK_RIPC 28
|
||||
#define CLK_I2S_SYSCLK 29
|
||||
#define CLK_I2S_BCLK 30
|
||||
#define CLK_APB 31
|
||||
#define CLK_WDT_BUS 32
|
||||
|
||||
/* APBC clocks */
|
||||
#define CLK_UART0 0
|
||||
#define CLK_UART2 1
|
||||
#define CLK_UART3 2
|
||||
#define CLK_UART4 3
|
||||
#define CLK_UART5 4
|
||||
#define CLK_UART6 5
|
||||
#define CLK_UART7 6
|
||||
#define CLK_UART8 7
|
||||
#define CLK_UART9 8
|
||||
#define CLK_GPIO 9
|
||||
#define CLK_PWM0 10
|
||||
#define CLK_PWM1 11
|
||||
#define CLK_PWM2 12
|
||||
#define CLK_PWM3 13
|
||||
#define CLK_PWM4 14
|
||||
#define CLK_PWM5 15
|
||||
#define CLK_PWM6 16
|
||||
#define CLK_PWM7 17
|
||||
#define CLK_PWM8 18
|
||||
#define CLK_PWM9 19
|
||||
#define CLK_PWM10 20
|
||||
#define CLK_PWM11 21
|
||||
#define CLK_PWM12 22
|
||||
#define CLK_PWM13 23
|
||||
#define CLK_PWM14 24
|
||||
#define CLK_PWM15 25
|
||||
#define CLK_PWM16 26
|
||||
#define CLK_PWM17 27
|
||||
#define CLK_PWM18 28
|
||||
#define CLK_PWM19 29
|
||||
#define CLK_SSP3 30
|
||||
#define CLK_RTC 31
|
||||
#define CLK_TWSI0 32
|
||||
#define CLK_TWSI1 33
|
||||
#define CLK_TWSI2 34
|
||||
#define CLK_TWSI4 35
|
||||
#define CLK_TWSI5 36
|
||||
#define CLK_TWSI6 37
|
||||
#define CLK_TWSI7 38
|
||||
#define CLK_TWSI8 39
|
||||
#define CLK_TIMERS1 40
|
||||
#define CLK_TIMERS2 41
|
||||
#define CLK_AIB 42
|
||||
#define CLK_ONEWIRE 43
|
||||
#define CLK_SSPA0 44
|
||||
#define CLK_SSPA1 45
|
||||
#define CLK_DRO 46
|
||||
#define CLK_IR 47
|
||||
#define CLK_TSEN 48
|
||||
#define CLK_IPC_AP2AUD 49
|
||||
#define CLK_CAN0 50
|
||||
#define CLK_CAN0_BUS 51
|
||||
#define CLK_UART0_BUS 52
|
||||
#define CLK_UART2_BUS 53
|
||||
#define CLK_UART3_BUS 54
|
||||
#define CLK_UART4_BUS 55
|
||||
#define CLK_UART5_BUS 56
|
||||
#define CLK_UART6_BUS 57
|
||||
#define CLK_UART7_BUS 58
|
||||
#define CLK_UART8_BUS 59
|
||||
#define CLK_UART9_BUS 60
|
||||
#define CLK_GPIO_BUS 61
|
||||
#define CLK_PWM0_BUS 62
|
||||
#define CLK_PWM1_BUS 63
|
||||
#define CLK_PWM2_BUS 64
|
||||
#define CLK_PWM3_BUS 65
|
||||
#define CLK_PWM4_BUS 66
|
||||
#define CLK_PWM5_BUS 67
|
||||
#define CLK_PWM6_BUS 68
|
||||
#define CLK_PWM7_BUS 69
|
||||
#define CLK_PWM8_BUS 70
|
||||
#define CLK_PWM9_BUS 71
|
||||
#define CLK_PWM10_BUS 72
|
||||
#define CLK_PWM11_BUS 73
|
||||
#define CLK_PWM12_BUS 74
|
||||
#define CLK_PWM13_BUS 75
|
||||
#define CLK_PWM14_BUS 76
|
||||
#define CLK_PWM15_BUS 77
|
||||
#define CLK_PWM16_BUS 78
|
||||
#define CLK_PWM17_BUS 79
|
||||
#define CLK_PWM18_BUS 80
|
||||
#define CLK_PWM19_BUS 81
|
||||
#define CLK_SSP3_BUS 82
|
||||
#define CLK_RTC_BUS 83
|
||||
#define CLK_TWSI0_BUS 84
|
||||
#define CLK_TWSI1_BUS 85
|
||||
#define CLK_TWSI2_BUS 86
|
||||
#define CLK_TWSI4_BUS 87
|
||||
#define CLK_TWSI5_BUS 88
|
||||
#define CLK_TWSI6_BUS 89
|
||||
#define CLK_TWSI7_BUS 90
|
||||
#define CLK_TWSI8_BUS 91
|
||||
#define CLK_TIMERS1_BUS 92
|
||||
#define CLK_TIMERS2_BUS 93
|
||||
#define CLK_AIB_BUS 94
|
||||
#define CLK_ONEWIRE_BUS 95
|
||||
#define CLK_SSPA0_BUS 96
|
||||
#define CLK_SSPA1_BUS 97
|
||||
#define CLK_TSEN_BUS 98
|
||||
#define CLK_IPC_AP2AUD_BUS 99
|
||||
|
||||
/* APMU clocks */
|
||||
#define CLK_CCI550 0
|
||||
#define CLK_CPU_C0_HI 1
|
||||
#define CLK_CPU_C0_CORE 2
|
||||
#define CLK_CPU_C0_ACE 3
|
||||
#define CLK_CPU_C0_TCM 4
|
||||
#define CLK_CPU_C1_HI 5
|
||||
#define CLK_CPU_C1_CORE 6
|
||||
#define CLK_CPU_C1_ACE 7
|
||||
#define CLK_CCIC_4X 8
|
||||
#define CLK_CCIC1PHY 9
|
||||
#define CLK_SDH_AXI 10
|
||||
#define CLK_SDH0 11
|
||||
#define CLK_SDH1 12
|
||||
#define CLK_SDH2 13
|
||||
#define CLK_USB_P1 14
|
||||
#define CLK_USB_AXI 15
|
||||
#define CLK_USB30 16
|
||||
#define CLK_QSPI 17
|
||||
#define CLK_QSPI_BUS 18
|
||||
#define CLK_DMA 19
|
||||
#define CLK_AES 20
|
||||
#define CLK_VPU 21
|
||||
#define CLK_GPU 22
|
||||
#define CLK_EMMC 23
|
||||
#define CLK_EMMC_X 24
|
||||
#define CLK_AUDIO 25
|
||||
#define CLK_HDMI 26
|
||||
#define CLK_PMUA_ACLK 27
|
||||
#define CLK_PCIE0_MASTER 28
|
||||
#define CLK_PCIE0_SLAVE 29
|
||||
#define CLK_PCIE0_DBI 30
|
||||
#define CLK_PCIE1_MASTER 31
|
||||
#define CLK_PCIE1_SLAVE 32
|
||||
#define CLK_PCIE1_DBI 33
|
||||
#define CLK_PCIE2_MASTER 34
|
||||
#define CLK_PCIE2_SLAVE 35
|
||||
#define CLK_PCIE2_DBI 36
|
||||
#define CLK_EMAC0_BUS 37
|
||||
#define CLK_EMAC0_PTP 38
|
||||
#define CLK_EMAC1_BUS 39
|
||||
#define CLK_EMAC1_PTP 40
|
||||
#define CLK_JPG 41
|
||||
#define CLK_CCIC2PHY 42
|
||||
#define CLK_CCIC3PHY 43
|
||||
#define CLK_CSI 44
|
||||
#define CLK_CAMM0 45
|
||||
#define CLK_CAMM1 46
|
||||
#define CLK_CAMM2 47
|
||||
#define CLK_ISP_CPP 48
|
||||
#define CLK_ISP_BUS 49
|
||||
#define CLK_ISP 50
|
||||
#define CLK_DPU_MCLK 51
|
||||
#define CLK_DPU_ESC 52
|
||||
#define CLK_DPU_BIT 53
|
||||
#define CLK_DPU_PXCLK 54
|
||||
#define CLK_DPU_HCLK 55
|
||||
#define CLK_DPU_SPI 56
|
||||
#define CLK_DPU_SPI_HBUS 57
|
||||
#define CLK_DPU_SPIBUS 58
|
||||
#define CLK_DPU_SPI_ACLK 59
|
||||
#define CLK_V2D 60
|
||||
#define CLK_EMMC_BUS 61
|
||||
|
||||
#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
|
||||
Loading…
Reference in New Issue
Block a user