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thermal: Add Mediatek thermal driver for mt2701.
This patch adds support for mt2701 chip to mtk_thermal, and integrate both mt8173 and mt2701 on the same driver. MT8173 has four banks and five sensors, and MT2701 has only one bank and three sensors. Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
This commit is contained in:
dawei.chien@mediatek.com
Zhang Rui
parent
77d6e7212c
commit
b7cf005373
@ -2,6 +2,7 @@
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Hanyi Wu <hanyi.wu@mediatek.com>
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* Sascha Hauer <s.hauer@pengutronix.de>
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* Dawei Chien <dawei.chien@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -21,6 +22,7 @@
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#include <linux/nvmem-consumer.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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@ -88,6 +90,7 @@
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#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
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#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
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/* MT8173 thermal sensors */
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#define MT8173_TS1 0
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#define MT8173_TS2 1
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#define MT8173_TS3 2
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@ -106,7 +109,12 @@
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/* The number of sensing points per bank */
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#define MT8173_NUM_SENSORS_PER_ZONE 4
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/* Layout of the fuses providing the calibration data */
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/*
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* Layout of the fuses providing the calibration data
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* These macros could be used for both MT8173 and MT2701.
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* MT8173 has five sensors and need five VTS calibration data,
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* and MT2701 has three sensors and need three VTS calibration data.
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*/
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#define MT8173_CALIB_BUF0_VALID BIT(0)
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#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
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#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
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@ -117,24 +125,50 @@
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#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
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#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
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/* MT2701 thermal sensors */
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#define MT2701_TS1 0
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#define MT2701_TS2 1
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#define MT2701_TSABB 2
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/* AUXADC channel 11 is used for the temperature sensors */
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#define MT2701_TEMP_AUXADC_CHANNEL 11
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/* The total number of temperature sensors in the MT2701 */
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#define MT2701_NUM_SENSORS 3
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#define THERMAL_NAME "mtk-thermal"
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/* The number of sensing points per bank */
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#define MT2701_NUM_SENSORS_PER_ZONE 3
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struct mtk_thermal;
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struct thermal_bank_cfg {
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unsigned int num_sensors;
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const int *sensors;
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};
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struct mtk_thermal_bank {
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struct mtk_thermal *mt;
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int id;
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};
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struct mtk_thermal_data {
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s32 num_banks;
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s32 num_sensors;
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s32 auxadc_channel;
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const int *sensor_mux_values;
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const int *msr;
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const int *adcpnp;
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struct thermal_bank_cfg bank_data[];
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};
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struct mtk_thermal {
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struct device *dev;
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void __iomem *thermal_base;
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struct clk *clk_peri_therm;
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struct clk *clk_auxadc;
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struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
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/* lock: for getting and putting banks */
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struct mutex lock;
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@ -144,16 +178,44 @@ struct mtk_thermal {
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s32 o_slope;
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s32 vts[MT8173_NUM_SENSORS];
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const struct mtk_thermal_data *conf;
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struct mtk_thermal_bank banks[];
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};
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struct mtk_thermal_bank_cfg {
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unsigned int num_sensors;
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unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
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/* MT8173 thermal sensor data */
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const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
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{ MT8173_TS2, MT8173_TS3 },
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{ MT8173_TS2, MT8173_TS4 },
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{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
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{ MT8173_TS2 },
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};
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static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
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const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
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TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR2
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};
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/*
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const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
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TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
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};
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const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
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/* MT2701 thermal sensor data */
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const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
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MT2701_TS1, MT2701_TS2, MT2701_TSABB
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};
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const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
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TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
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};
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const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
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TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
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};
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const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
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/**
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* The MT8173 thermal controller has four banks. Each bank can read up to
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* four temperature sensors simultaneously. The MT8173 has a total of 5
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* temperature sensors. We use each bank to measure a certain area of the
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@ -166,42 +228,53 @@ static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
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* data, and this indeed needs the temperatures of the individual banks
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* for making better decisions.
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*/
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static const struct mtk_thermal_bank_cfg bank_data[] = {
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static const struct mtk_thermal_data mt8173_thermal_data = {
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.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
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.num_banks = MT8173_NUM_ZONES,
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.num_sensors = MT8173_NUM_SENSORS,
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.bank_data = {
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{
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.num_sensors = 2,
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.sensors = { MT8173_TS2, MT8173_TS3 },
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.sensors = mt8173_bank_data[0],
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}, {
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.num_sensors = 2,
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.sensors = { MT8173_TS2, MT8173_TS4 },
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.sensors = mt8173_bank_data[1],
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}, {
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.num_sensors = 3,
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.sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
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.sensors = mt8173_bank_data[2],
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}, {
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.num_sensors = 1,
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.sensors = { MT8173_TS2 },
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.sensors = mt8173_bank_data[3],
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},
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},
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.msr = mt8173_msr,
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.adcpnp = mt8173_adcpnp,
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.sensor_mux_values = mt8173_mux_values,
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};
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struct mtk_thermal_sense_point {
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int msr;
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int adcpnp;
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};
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static const struct mtk_thermal_sense_point
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sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
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/**
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* The MT2701 thermal controller has one bank, which can read up to
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* three temperature sensors simultaneously. The MT2701 has a total of 3
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* temperature sensors.
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*
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* The thermal core only gets the maximum temperature of this one bank,
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* so the bank concept wouldn't be necessary here. However, the SVS (Smart
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* Voltage Scaling) unit makes its decisions based on the same bank
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* data.
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*/
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static const struct mtk_thermal_data mt2701_thermal_data = {
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.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
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.num_banks = 1,
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.num_sensors = MT2701_NUM_SENSORS,
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.bank_data = {
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{
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.msr = TEMP_MSR0,
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.adcpnp = TEMP_ADCPNP0,
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}, {
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.msr = TEMP_MSR1,
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.adcpnp = TEMP_ADCPNP1,
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}, {
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.msr = TEMP_MSR2,
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.adcpnp = TEMP_ADCPNP2,
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}, {
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.msr = TEMP_MSR3,
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.adcpnp = TEMP_ADCPNP3,
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.num_sensors = 3,
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.sensors = mt2701_bank_data,
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},
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},
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.msr = mt2701_msr,
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.adcpnp = mt2701_adcpnp,
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.sensor_mux_values = mt2701_mux_values,
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};
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/**
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@ -270,13 +343,16 @@ static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
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static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
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{
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struct mtk_thermal *mt = bank->mt;
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const struct mtk_thermal_data *conf = mt->conf;
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int i, temp = INT_MIN, max = INT_MIN;
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u32 raw;
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for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
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raw = readl(mt->thermal_base + sensing_points[i].msr);
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for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
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raw = readl(mt->thermal_base + conf->msr[i]);
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temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);
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temp = raw_to_mcelsius(mt,
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conf->bank_data[bank->id].sensors[i],
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raw);
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/*
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* The first read of a sensor often contains very high bogus
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@ -299,7 +375,7 @@ static int mtk_read_temp(void *data, int *temperature)
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int i;
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int tempmax = INT_MIN;
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for (i = 0; i < MT8173_NUM_ZONES; i++) {
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for (i = 0; i < mt->conf->num_banks; i++) {
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struct mtk_thermal_bank *bank = &mt->banks[i];
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mtk_thermal_get_bank(bank);
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@ -322,7 +398,7 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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u32 apmixed_phys_base, u32 auxadc_phys_base)
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{
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struct mtk_thermal_bank *bank = &mt->banks[num];
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const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
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const struct mtk_thermal_data *conf = mt->conf;
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int i;
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bank->id = num;
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@ -368,7 +444,7 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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* this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
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* automatically by hw
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*/
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writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);
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writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX);
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/* AHB address for auxadc mux selection */
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writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
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@ -379,18 +455,18 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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mt->thermal_base + TEMP_PNPMUXADDR);
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/* AHB value for auxadc enable */
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writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
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writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN);
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/* AHB address for auxadc enable (channel 0 immediate mode selected) */
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writel(auxadc_phys_base + AUXADC_CON1_SET_V,
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mt->thermal_base + TEMP_ADCENADDR);
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/* AHB address for auxadc valid bit */
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writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
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writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
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mt->thermal_base + TEMP_ADCVALIDADDR);
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/* AHB address for auxadc voltage output */
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writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
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writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
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mt->thermal_base + TEMP_ADCVOLTADDR);
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/* read valid & voltage are at the same register */
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@ -407,11 +483,12 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
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writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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mt->thermal_base + TEMP_ADCWRITECTRL);
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for (i = 0; i < cfg->num_sensors; i++)
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writel(sensor_mux_values[cfg->sensors[i]],
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mt->thermal_base + sensing_points[i].adcpnp);
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for (i = 0; i < conf->bank_data[num].num_sensors; i++)
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writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
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mt->thermal_base + conf->adcpnp[i]);
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writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
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writel((1 << conf->bank_data[num].num_sensors) - 1,
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mt->thermal_base + TEMP_MONCTL0);
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writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
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TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
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@ -442,7 +519,7 @@ static int mtk_thermal_get_calibration_data(struct device *dev,
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/* Start with default values */
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mt->adc_ge = 512;
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for (i = 0; i < MT8173_NUM_SENSORS; i++)
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for (i = 0; i < mt->conf->num_sensors; i++)
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mt->vts[i] = 260;
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mt->degc_cali = 40;
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mt->o_slope = 0;
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@ -486,18 +563,36 @@ out:
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return ret;
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}
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static const struct of_device_id mtk_thermal_of_match[] = {
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{
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.compatible = "mediatek,mt8173-thermal",
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.data = (void *)&mt8173_thermal_data,
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},
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{
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.compatible = "mediatek,mt2701-thermal",
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.data = (void *)&mt2701_thermal_data,
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}, {
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},
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};
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MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
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static int mtk_thermal_probe(struct platform_device *pdev)
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{
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int ret, i;
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struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
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struct mtk_thermal *mt;
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struct resource *res;
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const struct of_device_id *of_id;
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u64 auxadc_phys_base, apmixed_phys_base;
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mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
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if (!mt)
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return -ENOMEM;
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of_id = of_match_device(mtk_thermal_of_match, &pdev->dev);
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if (of_id)
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mt->conf = (const struct mtk_thermal_data *)of_id->data;
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mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
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if (IS_ERR(mt->clk_peri_therm))
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return PTR_ERR(mt->clk_peri_therm);
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@ -565,7 +660,7 @@ static int mtk_thermal_probe(struct platform_device *pdev)
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goto err_disable_clk_auxadc;
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}
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for (i = 0; i < MT8173_NUM_ZONES; i++)
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for (i = 0; i < mt->conf->num_banks; i++)
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mtk_thermal_init_bank(mt, i, apmixed_phys_base,
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auxadc_phys_base);
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@ -592,13 +687,6 @@ static int mtk_thermal_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id mtk_thermal_of_match[] = {
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{
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.compatible = "mediatek,mt8173-thermal",
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}, {
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},
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};
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static struct platform_driver mtk_thermal_driver = {
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.probe = mtk_thermal_probe,
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.remove = mtk_thermal_remove,
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@ -610,6 +698,7 @@ static struct platform_driver mtk_thermal_driver = {
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module_platform_driver(mtk_thermal_driver);
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MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
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MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
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MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
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MODULE_DESCRIPTION("Mediatek thermal driver");
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