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locking: Move common qspinlock helpers to a private header
Move qspinlock helper functions that encode, decode tail word, set and clear the pending and locked bits, and other miscellaneous definitions and macros to a private header. To this end, create a qspinlock.h header file in kernel/locking. Subsequent commits will introduce a modified qspinlock slow path function, thus moving shared code to a private header will help minimize unnecessary code duplication. Reviewed-by: Barret Rhoden <brho@google.com> Signed-off-by: Kumar Kartikeya Dwivedi <memxor@gmail.com> Link: https://lore.kernel.org/r/20250316040541.108729-3-memxor@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Kumar Kartikeya Dwivedi
Alexei Starovoitov
parent
8707d1eedc
commit
ac08f68f1f
@ -25,8 +25,9 @@
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#include <trace/events/lock.h>
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/*
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* Include queued spinlock statistics code
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* Include queued spinlock definitions and statistics code
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*/
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#include "qspinlock.h"
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#include "qspinlock_stat.h"
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/*
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@ -67,36 +68,6 @@
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*/
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#include "mcs_spinlock.h"
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#define MAX_NODES 4
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/*
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* On 64-bit architectures, the mcs_spinlock structure will be 16 bytes in
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* size and four of them will fit nicely in one 64-byte cacheline. For
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* pvqspinlock, however, we need more space for extra data. To accommodate
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* that, we insert two more long words to pad it up to 32 bytes. IOW, only
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* two of them can fit in a cacheline in this case. That is OK as it is rare
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* to have more than 2 levels of slowpath nesting in actual use. We don't
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* want to penalize pvqspinlocks to optimize for a rare case in native
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* qspinlocks.
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*/
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struct qnode {
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struct mcs_spinlock mcs;
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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long reserved[2];
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#endif
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};
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/*
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* The pending bit spinning loop count.
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* This heuristic is used to limit the number of lockword accesses
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* made by atomic_cond_read_relaxed when waiting for the lock to
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* transition out of the "== _Q_PENDING_VAL" state. We don't spin
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* indefinitely because there's no guarantee that we'll make forward
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* progress.
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*/
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#ifndef _Q_PENDING_LOOPS
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#define _Q_PENDING_LOOPS 1
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#endif
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/*
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* Per-CPU queue node structures; we can never have more than 4 nested
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@ -106,161 +77,7 @@ struct qnode {
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*
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* PV doubles the storage and uses the second cacheline for PV state.
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*/
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static DEFINE_PER_CPU_ALIGNED(struct qnode, qnodes[MAX_NODES]);
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/*
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* We must be able to distinguish between no-tail and the tail at 0:0,
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* therefore increment the cpu number by one.
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*/
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static inline __pure u32 encode_tail(int cpu, int idx)
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{
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u32 tail;
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tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
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tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
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return tail;
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}
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static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
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{
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int cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1;
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int idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
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return per_cpu_ptr(&qnodes[idx].mcs, cpu);
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}
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static inline __pure
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struct mcs_spinlock *grab_mcs_node(struct mcs_spinlock *base, int idx)
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{
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return &((struct qnode *)base + idx)->mcs;
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}
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#define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK)
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#if _Q_PENDING_BITS == 8
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/**
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* clear_pending - clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,* -> *,0,*
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*/
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static __always_inline void clear_pending(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->pending, 0);
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}
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*
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* Lock stealing is not allowed if this function is used.
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL);
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}
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/*
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail), which heads an address dependency
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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/*
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* We can use relaxed semantics since the caller ensures that the
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* MCS node is properly initialized before updating the tail.
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*/
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return (u32)xchg_relaxed(&lock->tail,
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tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
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}
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#else /* _Q_PENDING_BITS == 8 */
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/**
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* clear_pending - clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,* -> *,0,*
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*/
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static __always_inline void clear_pending(struct qspinlock *lock)
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{
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atomic_andnot(_Q_PENDING_VAL, &lock->val);
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}
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val);
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}
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/**
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail)
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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u32 old, new;
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old = atomic_read(&lock->val);
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do {
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new = (old & _Q_LOCKED_PENDING_MASK) | tail;
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/*
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* We can use relaxed semantics since the caller ensures that
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* the MCS node is properly initialized before updating the
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* tail.
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*/
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} while (!atomic_try_cmpxchg_relaxed(&lock->val, &old, new));
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return old;
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}
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#endif /* _Q_PENDING_BITS == 8 */
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/**
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* queued_fetch_set_pending_acquire - fetch the whole lock value and set pending
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* @lock : Pointer to queued spinlock structure
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* Return: The previous lock value
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*
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* *,*,* -> *,1,*
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*/
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#ifndef queued_fetch_set_pending_acquire
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static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock)
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{
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return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val);
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}
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#endif
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/**
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* set_locked - Set the lock bit and own the lock
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* @lock: Pointer to queued spinlock structure
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*
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* *,*,0 -> *,0,1
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*/
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static __always_inline void set_locked(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);
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}
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static DEFINE_PER_CPU_ALIGNED(struct qnode, qnodes[_Q_MAX_NODES]);
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/*
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* Generate the native code for queued_spin_unlock_slowpath(); provide NOPs for
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@ -410,7 +227,7 @@ pv_queue:
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* any MCS node. This is not the most elegant solution, but is
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* simple enough.
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*/
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if (unlikely(idx >= MAX_NODES)) {
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if (unlikely(idx >= _Q_MAX_NODES)) {
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lockevent_inc(lock_no_node);
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while (!queued_spin_trylock(lock))
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cpu_relax();
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@ -465,7 +282,7 @@ pv_queue:
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* head of the waitqueue.
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*/
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if (old & _Q_TAIL_MASK) {
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prev = decode_tail(old);
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prev = decode_tail(old, qnodes);
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/* Link @node into the waitqueue. */
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WRITE_ONCE(prev->next, node);
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201
kernel/locking/qspinlock.h
Normal file
201
kernel/locking/qspinlock.h
Normal file
@ -0,0 +1,201 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Queued spinlock defines
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*
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* This file contains macro definitions and functions shared between different
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* qspinlock slow path implementations.
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*/
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#ifndef __LINUX_QSPINLOCK_H
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#define __LINUX_QSPINLOCK_H
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#include <asm-generic/percpu.h>
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#include <linux/percpu-defs.h>
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#include <asm-generic/qspinlock.h>
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#include <asm-generic/mcs_spinlock.h>
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#define _Q_MAX_NODES 4
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/*
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* The pending bit spinning loop count.
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* This heuristic is used to limit the number of lockword accesses
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* made by atomic_cond_read_relaxed when waiting for the lock to
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* transition out of the "== _Q_PENDING_VAL" state. We don't spin
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* indefinitely because there's no guarantee that we'll make forward
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* progress.
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*/
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#ifndef _Q_PENDING_LOOPS
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#define _Q_PENDING_LOOPS 1
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#endif
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/*
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* On 64-bit architectures, the mcs_spinlock structure will be 16 bytes in
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* size and four of them will fit nicely in one 64-byte cacheline. For
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* pvqspinlock, however, we need more space for extra data. To accommodate
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* that, we insert two more long words to pad it up to 32 bytes. IOW, only
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* two of them can fit in a cacheline in this case. That is OK as it is rare
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* to have more than 2 levels of slowpath nesting in actual use. We don't
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* want to penalize pvqspinlocks to optimize for a rare case in native
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* qspinlocks.
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*/
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struct qnode {
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struct mcs_spinlock mcs;
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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long reserved[2];
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#endif
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};
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/*
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* We must be able to distinguish between no-tail and the tail at 0:0,
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* therefore increment the cpu number by one.
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*/
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static inline __pure u32 encode_tail(int cpu, int idx)
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{
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u32 tail;
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tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
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tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
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return tail;
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}
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static inline __pure struct mcs_spinlock *decode_tail(u32 tail,
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struct qnode __percpu *qnodes)
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{
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int cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1;
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int idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
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return per_cpu_ptr(&qnodes[idx].mcs, cpu);
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}
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static inline __pure
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struct mcs_spinlock *grab_mcs_node(struct mcs_spinlock *base, int idx)
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{
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return &((struct qnode *)base + idx)->mcs;
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}
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#define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK)
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#if _Q_PENDING_BITS == 8
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/**
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* clear_pending - clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,* -> *,0,*
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*/
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static __always_inline void clear_pending(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->pending, 0);
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}
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*
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* Lock stealing is not allowed if this function is used.
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL);
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}
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/*
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail), which heads an address dependency
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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/*
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* We can use relaxed semantics since the caller ensures that the
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* MCS node is properly initialized before updating the tail.
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*/
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return (u32)xchg_relaxed(&lock->tail,
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tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
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}
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#else /* _Q_PENDING_BITS == 8 */
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/**
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* clear_pending - clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,* -> *,0,*
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*/
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static __always_inline void clear_pending(struct qspinlock *lock)
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{
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atomic_andnot(_Q_PENDING_VAL, &lock->val);
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}
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val);
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}
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/**
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail)
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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u32 old, new;
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old = atomic_read(&lock->val);
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do {
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new = (old & _Q_LOCKED_PENDING_MASK) | tail;
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/*
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* We can use relaxed semantics since the caller ensures that
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* the MCS node is properly initialized before updating the
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* tail.
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*/
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} while (!atomic_try_cmpxchg_relaxed(&lock->val, &old, new));
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return old;
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}
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#endif /* _Q_PENDING_BITS == 8 */
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/**
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* queued_fetch_set_pending_acquire - fetch the whole lock value and set pending
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* @lock : Pointer to queued spinlock structure
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* Return: The previous lock value
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*
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* *,*,* -> *,1,*
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*/
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#ifndef queued_fetch_set_pending_acquire
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static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock)
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{
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return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val);
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}
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#endif
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/**
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* set_locked - Set the lock bit and own the lock
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* @lock: Pointer to queued spinlock structure
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*
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* *,*,0 -> *,0,1
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*/
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static __always_inline void set_locked(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);
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}
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#endif /* __LINUX_QSPINLOCK_H */
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