From 7009646d937f9a1147b401362260939bba52082f Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 2 Sep 2025 12:21:43 +0800 Subject: [PATCH 01/27] dt-binding: Update oss email address for Coresight documents Update the OSS email addresses across all Coresight documents, as the previous addresses have been deprecated. Signed-off-by: Jie Gan Acked-by: Rob Herring (Arm) Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20250902042143.1010-1-jie.gan@oss.qualcomm.com --- .../sysfs-bus-coresight-devices-dummy-source | 4 +- .../testing/sysfs-bus-coresight-devices-tpdm | 56 +++++++++---------- .../arm/arm,coresight-dummy-sink.yaml | 2 +- .../arm/arm,coresight-dummy-source.yaml | 2 +- .../bindings/arm/qcom,coresight-ctcu.yaml | 6 +- .../arm/qcom,coresight-remote-etm.yaml | 4 +- .../bindings/arm/qcom,coresight-tnoc.yaml | 2 +- .../bindings/arm/qcom,coresight-tpda.yaml | 4 +- .../bindings/arm/qcom,coresight-tpdm.yaml | 4 +- 9 files changed, 42 insertions(+), 42 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source b/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source index 321e3ee1fc9d..c8c58914116e 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source @@ -1,7 +1,7 @@ What: /sys/bus/coresight/devices/dummy_source/enable_source Date: Dec 2024 KernelVersion: 6.14 -Contact: Mao Jinlong +Contact: Mao Jinlong Description: (RW) Enable/disable tracing of dummy source. A sink should be activated before enabling the source. The path of coresight components linking the source to the sink is configured and managed automatically by the @@ -10,7 +10,7 @@ Description: (RW) Enable/disable tracing of dummy source. A sink should be activ What: /sys/bus/coresight/devices/dummy_source/traceid Date: Dec 2024 KernelVersion: 6.14 -Contact: Mao Jinlong +Contact: Mao Jinlong Description: (R) Show the trace ID that will appear in the trace stream coming from this trace entity. diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm index 98f1c6545027..f8016df64532 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -1,7 +1,7 @@ What: /sys/bus/coresight/devices//integration_test Date: January 2023 KernelVersion: 6.2 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (Write) Run integration test for tpdm. Integration test will generate test data for tpdm. It can help to make @@ -15,7 +15,7 @@ Description: What: /sys/bus/coresight/devices//reset_dataset Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (Write) Reset the dataset of the tpdm. @@ -25,7 +25,7 @@ Description: What: /sys/bus/coresight/devices//dsb_trig_type Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the trigger type of the DSB for tpdm. @@ -36,7 +36,7 @@ Description: What: /sys/bus/coresight/devices//dsb_trig_ts Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the trigger timestamp of the DSB for tpdm. @@ -47,7 +47,7 @@ Description: What: /sys/bus/coresight/devices//dsb_mode Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the programming mode of the DSB for tpdm. @@ -61,7 +61,7 @@ Description: What: /sys/bus/coresight/devices//dsb_edge/ctrl_idx Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the index number of the edge detection for the DSB subunit TPDM. Since there are at most 256 edge detections, this @@ -70,7 +70,7 @@ Description: What: /sys/bus/coresight/devices//dsb_edge/ctrl_val Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: Write a data to control the edge detection corresponding to the index number. Before writing data to this sysfs file, @@ -86,7 +86,7 @@ Description: What: /sys/bus/coresight/devices//dsb_edge/ctrl_mask Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: Write a data to mask the edge detection corresponding to the index number. Before writing data to this sysfs file, "ctrl_idx" should @@ -98,21 +98,21 @@ Description: What: /sys/bus/coresight/devices//dsb_edge/edcr[0:15] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: Read a set of the edge control value of the DSB in TPDM. What: /sys/bus/coresight/devices//dsb_edge/edcmr[0:7] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: Read a set of the edge control mask of the DSB in TPDM. What: /sys/bus/coresight/devices//dsb_trig_patt/xpr[0:7] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the value of the trigger pattern for the DSB subunit TPDM. @@ -120,7 +120,7 @@ Description: What: /sys/bus/coresight/devices//dsb_trig_patt/xpmr[0:7] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the mask of the trigger pattern for the DSB subunit TPDM. @@ -128,21 +128,21 @@ Description: What: /sys/bus/coresight/devices//dsb_patt/tpr[0:7] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the value of the pattern for the DSB subunit TPDM. What: /sys/bus/coresight/devices//dsb_patt/tpmr[0:7] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the mask of the pattern for the DSB subunit TPDM. What: /sys/bus/coresight/devices//dsb_patt/enable_ts Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (Write) Set the pattern timestamp of DSB tpdm. Read the pattern timestamp of DSB tpdm. @@ -154,7 +154,7 @@ Description: What: /sys/bus/coresight/devices//dsb_patt/set_type Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (Write) Set the pattern type of DSB tpdm. Read the pattern type of DSB tpdm. @@ -166,7 +166,7 @@ Description: What: /sys/bus/coresight/devices//dsb_msr/msr[0:31] Date: March 2023 KernelVersion: 6.7 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the MSR(mux select register) for the DSB subunit TPDM. @@ -174,7 +174,7 @@ Description: What: /sys/bus/coresight/devices//cmb_mode Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (Write) Set the data collection mode of CMB tpdm. Continuous change creates CMB data set elements on every CMBCLK edge. Trace-on-change creates CMB data set elements only when a new @@ -188,7 +188,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous What: /sys/bus/coresight/devices//cmb_trig_patt/xpr[0:1] Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the value of the trigger pattern for the CMB subunit TPDM. @@ -196,7 +196,7 @@ Description: What: /sys/bus/coresight/devices//cmb_trig_patt/xpmr[0:1] Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the mask of the trigger pattern for the CMB subunit TPDM. @@ -204,21 +204,21 @@ Description: What: /sys/bus/coresight/devices//dsb_patt/tpr[0:1] Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the value of the pattern for the CMB subunit TPDM. What: /sys/bus/coresight/devices//dsb_patt/tpmr[0:1] Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the mask of the pattern for the CMB subunit TPDM. What: /sys/bus/coresight/devices//cmb_patt/enable_ts Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (Write) Set the pattern timestamp of CMB tpdm. Read the pattern timestamp of CMB tpdm. @@ -230,7 +230,7 @@ Description: What: /sys/bus/coresight/devices//cmb_trig_ts Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the trigger timestamp of the CMB for tpdm. @@ -241,7 +241,7 @@ Description: What: /sys/bus/coresight/devices//cmb_ts_all Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Read or write the status of timestamp upon all interface. Only value 0 and 1 can be written to this node. Set this node to 1 to request @@ -253,7 +253,7 @@ Description: What: /sys/bus/coresight/devices//cmb_msr/msr[0:31] Date: January 2024 KernelVersion: 6.9 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the MSR(mux select register) for the CMB subunit TPDM. @@ -261,7 +261,7 @@ Description: What: /sys/bus/coresight/devices//mcmb_trig_lane Date: Feb 2025 KernelVersion 6.15 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get which lane participates in the output pattern match cross trigger mechanism for the MCMB subunit TPDM. @@ -269,7 +269,7 @@ Description: What: /sys/bus/coresight/devices//mcmb_lanes_select Date: Feb 2025 KernelVersion 6.15 -Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Contact: Jinlong Mao , Tao Zhang Description: (RW) Set/Get the enablement of the individual lane. diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml index ed091dc0c10a..206681ccaa4c 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml @@ -31,7 +31,7 @@ maintainers: - Mike Leach - Suzuki K Poulose - James Clark - - Mao Jinlong + - Mao Jinlong - Hao Zhang properties: diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml index 78337be42b55..0b1e12ae95c3 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml @@ -30,7 +30,7 @@ maintainers: - Mike Leach - Suzuki K Poulose - James Clark - - Mao Jinlong + - Mao Jinlong - Hao Zhang properties: diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index c969c16c21ef..2544fc1f71f5 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: CoreSight TMC Control Unit maintainers: - - Yuanfang Zhang - - Mao Jinlong - - Jie Gan + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan description: | The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml index ffe613efeabe..e3a32f30551c 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell) maintainers: - - Jinlong Mao - - Tao Zhang + - Jinlong Mao + - Tao Zhang description: Support for ETM trace collection on remote processor using coresight diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml index 9d1c93a9ade3..ef648a15b806 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Trace Network On Chip - TNOC maintainers: - - Yuanfang Zhang + - Yuanfang Zhang description: > The Trace Network On Chip (TNOC) is an integration hierarchy hardware diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml index a48c9ac3eaa9..70d297b054c3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml @@ -33,8 +33,8 @@ description: | to sink. maintainers: - - Mao Jinlong - - Tao Zhang + - Mao Jinlong + - Tao Zhang # Need a custom select here or 'arm,primecell' will match on lots of nodes select: diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index c349306f0d52..152403f548c3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -19,8 +19,8 @@ description: | sources and send it to a TPDA for packetization, timestamping, and funneling. maintainers: - - Mao Jinlong - - Tao Zhang + - Mao Jinlong + - Tao Zhang # Need a custom select here or 'arm,primecell' will match on lots of nodes select: From 51cd1fb70e08802904cd990b9b446125ee34de13 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 3 Nov 2025 15:06:21 +0800 Subject: [PATCH 02/27] dt-bindings: arm: add CTCU device for monaco The CTCU device for monaco shares the same configurations as SA8775p. Add a fallback to enable the CTCU for monaco to utilize the compitable of the SA8775p. Reviewed-by: Krzysztof Kozlowski Acked-by: Suzuki K Poulose Reviewed-by: Bjorn Andersson Signed-off-by: Jie Gan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251103-enable-ctcu-for-monaco-v4-1-92ff83201584@oss.qualcomm.com --- .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 2544fc1f71f5..e002f87361ad 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -26,8 +26,13 @@ description: | properties: compatible: - enum: - - qcom,sa8775p-ctcu + oneOf: + - items: + - enum: + - qcom,qcs8300-ctcu + - const: qcom,sa8775p-ctcu + - enum: + - qcom,sa8775p-ctcu reg: maxItems: 1 From 10d4dbdc8fbce586b17be07b8138e025381453dd Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:13 +0000 Subject: [PATCH 03/27] coresight: Change syncfreq to be a u8 TRCSYNCPR.PERIOD is the only functional part of TRCSYNCPR and it only has 5 valid bits so it can be stored in a u8. Reviewed-by: Mike Leach Reviewed-by: Leo Yan Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-1-4d319764cc58@linaro.org --- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 012c52fd1933..0287d19ce12e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -825,7 +825,6 @@ struct etmv4_config { u32 eventctrl1; u32 stall_ctrl; u32 ts_ctrl; - u32 syncfreq; u32 ccctlr; u32 bb_ctrl; u32 vinst_ctrl; @@ -833,6 +832,7 @@ struct etmv4_config { u32 vissctlr; u32 vipcssctlr; u8 seq_idx; + u8 syncfreq; u32 seq_ctrl[ETM_MAX_SEQ_STATES]; u32 seq_rst; u32 seq_state; From 38f4c42734990ddf42ad6d996b14fbff8fdec9d2 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:14 +0000 Subject: [PATCH 04/27] coresight: Repack struct etmv4_drvdata Fix holes and convert the long list of bools to single bits to save some space because there's one of these for each ETM. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-2-4d319764cc58@linaro.org --- drivers/hwtracing/coresight/coresight-etm4x.h | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 0287d19ce12e..d178d79d9827 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1016,27 +1016,27 @@ struct etmv4_drvdata { u8 ns_ex_level; u8 q_support; u8 os_lock_model; - bool sticky_enable; - bool boot_enable; - bool os_unlock; - bool instrp0; - bool q_filt; - bool trcbb; - bool trccond; - bool retstack; - bool trccci; - bool trc_error; - bool syncpr; - bool stallctl; - bool sysstall; - bool nooverflow; - bool atbtrig; - bool lpoverride; + bool sticky_enable : 1; + bool boot_enable : 1; + bool os_unlock : 1; + bool instrp0 : 1; + bool q_filt : 1; + bool trcbb : 1; + bool trccond : 1; + bool retstack : 1; + bool trccci : 1; + bool trc_error : 1; + bool syncpr : 1; + bool stallctl : 1; + bool sysstall : 1; + bool nooverflow : 1; + bool atbtrig : 1; + bool lpoverride : 1; + bool skip_power_up : 1; + bool paused : 1; u64 trfcr; struct etmv4_config config; struct etmv4_save_state *save_state; - bool skip_power_up; - bool paused; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); }; From b02450de6ba6309c66e2e056ccfbfce4bd3b0352 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:15 +0000 Subject: [PATCH 05/27] coresight: Refactor etm4_config_timestamp_event() Remove some of the magic numbers and try to clarify some of the documentation so it's clearer how this sets up the timestamp interval. Return errors directly instead of jumping to out and returning ret, nothing needs to be cleaned up at the end and it only obscures the flow and return value. Add utilities for programming resource selectors that do compile time checks for constants or WARN_ONs for non-constant values. FIELD_PREP includes compile time checks so we only need to add an additional BUILD_BUG_ON for resource == 0 in pair mode. Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-3-4d319764cc58@linaro.org --- .../coresight/coresight-etm4x-core.c | 96 ++++++++++++------- drivers/hwtracing/coresight/coresight-etm4x.h | 54 ++++++++++- 2 files changed, 112 insertions(+), 38 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 560975b70474..2ec2ae1fef58 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -642,18 +642,33 @@ static void etm4_enable_sysfs_smp_call(void *info) * TRCRSCTLR1 (always true) used to get the counter to decrement. From * there a resource selector is configured with the counter and the * timestamp control register to use the resource selector to trigger the - * event that will insert a timestamp packet in the stream. + * event that will insert a timestamp packet in the stream: + * + * +--------------+ + * | Resource 1 | fixed "always-true" resource + * +--------------+ + * | + * +------v-------+ + * | Counter x | (reload to 1 on underflow) + * +--------------+ + * | + * +------v--------------+ + * | Resource Selector y | (trigger on counter x == 0) + * +---------------------+ + * | + * +------v---------------+ + * | Timestamp Generator | (timestamp on resource y) + * +----------------------+ */ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) { - int ctridx, ret = -EINVAL; - int counter, rselector; - u32 val = 0; + int ctridx; + int rselector; struct etmv4_config *config = &drvdata->config; /* No point in trying if we don't have at least one counter */ if (!drvdata->nr_cntr) - goto out; + return -EINVAL; /* Find a counter that hasn't been initialised */ for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) @@ -663,15 +678,19 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) /* All the counters have been configured already, bail out */ if (ctridx == drvdata->nr_cntr) { pr_debug("%s: no available counter found\n", __func__); - ret = -ENOSPC; - goto out; + return -ENOSPC; } /* - * Searching for an available resource selector to use, starting at - * '2' since every implementation has at least 2 resource selector. - * ETMIDR4 gives the number of resource selector _pairs_, - * hence multiply by 2. + * Searching for an available resource selector to use, starting at '2' + * since resource 0 is the fixed 'always returns false' resource and 1 + * is the fixed 'always returns true' resource. See IHI0064H_b '7.3.64 + * TRCRSCTLRn, Resource Selection Control Registers, n=2-31'. If there + * are no resources, there would also be no counters so wouldn't get + * here. + * + * ETMIDR4 gives the number of resource selector _pairs_, hence multiply + * by 2. */ for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) if (!config->res_ctrl[rselector]) @@ -680,13 +699,9 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) if (rselector == drvdata->nr_resource * 2) { pr_debug("%s: no available resource selector found\n", __func__); - ret = -ENOSPC; - goto out; + return -ENOSPC; } - /* Remember what counter we used */ - counter = 1 << ctridx; - /* * Initialise original and reload counter value to the smallest * possible value in order to get as much precision as we can. @@ -694,26 +709,41 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) config->cntr_val[ctridx] = 1; config->cntrldvr[ctridx] = 1; - /* Set the trace counter control register */ - val = 0x1 << 16 | /* Bit 16, reload counter automatically */ - 0x0 << 7 | /* Select single resource selector */ - 0x1; /* Resource selector 1, i.e always true */ + /* + * Trace Counter Control Register TRCCNTCTLRn + * + * CNTCHAIN = 0, don't reload on the previous counter + * RLDSELF = true, reload counter automatically on underflow + * RLDEVENT = RES_SEL_FALSE (0), reload on single false resource (never reload) + * CNTEVENT = RES_SEL_TRUE (1), count single fixed 'always true' resource (always decrement) + */ + config->cntr_ctrl[ctridx] = TRCCNTCTLRn_RLDSELF | + FIELD_PREP(TRCCNTCTLRn_RLDEVENT_MASK, + etm4_res_sel_single(ETM4_RES_SEL_FALSE)) | + FIELD_PREP(TRCCNTCTLRn_CNTEVENT_MASK, + etm4_res_sel_single(ETM4_RES_SEL_TRUE)); - config->cntr_ctrl[ctridx] = val; + /* + * Resource Selection Control Register TRCRSCTLRn + * + * PAIRINV = 0, INV = 0, don't invert + * GROUP = 2, SELECT = ctridx, trigger when counter 'ctridx' reaches 0 + * + * Multiple counters can be selected, and each bit signifies a counter, + * so set bit 'ctridx' to select our counter. + */ + config->res_ctrl[rselector] = FIELD_PREP(TRCRSCTLRn_GROUP_MASK, 2) | + FIELD_PREP(TRCRSCTLRn_SELECT_MASK, 1 << ctridx); - val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ - counter << 0; /* Counter to use */ + /* + * Global Timestamp Control Register TRCTSCTLR + * + * EVENT = generate timestamp on single resource 'rselector' + */ + config->ts_ctrl = FIELD_PREP(TRCTSCTLR_EVENT_MASK, + etm4_res_sel_single(rselector)); - config->res_ctrl[rselector] = val; - - val = 0x0 << 7 | /* Select single resource selector */ - rselector; /* Resource selector */ - - config->ts_ctrl = val; - - ret = 0; -out: - return ret; + return 0; } static int etm4_parse_event_config(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index d178d79d9827..89d81ce4e04e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -225,6 +225,50 @@ #define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16) #define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0) +#define TRCCNTCTLRn_CNTCHAIN BIT(17) +#define TRCCNTCTLRn_RLDSELF BIT(16) +#define TRCCNTCTLRn_RLDEVENT_MASK GENMASK(15, 8) +#define TRCCNTCTLRn_CNTEVENT_MASK GENMASK(7, 0) + +#define TRCTSCTLR_EVENT_MASK GENMASK(7, 0) + +#define ETM4_RES_SEL_FALSE 0 /* Fixed function 'always false' resource selector */ +#define ETM4_RES_SEL_TRUE 1 /* Fixed function 'always true' resource selector */ + +#define ETM4_RES_SEL_SINGLE_MASK GENMASK(4, 0) +#define ETM4_RES_SEL_PAIR_MASK GENMASK(3, 0) +#define ETM4_RES_SEL_TYPE_PAIR BIT(7) + +/* + * Utilities for programming EVENT resource selectors, e.g. TRCCNTCTLRn_RLDEVENT. + * + * Resource selectors have a common format across registers: + * + * 7 6 5 4 0 + * +------+------+-------+ + * | TYPE | RES0 | SEL | + * +------+------+-------+ + * + * Where TYPE indicates whether the selector is for a single event or a pair. + * When TYPE is pair, SEL is 4 bits wide and using pair 0 is UNPREDICTABLE. + * Otherwise for single it's 5 bits wide. + */ +static inline u32 etm4_res_sel_single(u8 res_sel_idx) +{ + WARN_ON_ONCE(!FIELD_FIT(ETM4_RES_SEL_SINGLE_MASK, res_sel_idx)); + return FIELD_PREP(ETM4_RES_SEL_SINGLE_MASK, res_sel_idx); +} + +static inline u32 etm4_res_sel_pair(u8 res_sel_idx) +{ + if (__builtin_constant_p(res_sel_idx)) + BUILD_BUG_ON(res_sel_idx == 0); + WARN_ON_ONCE(!FIELD_FIT(ETM4_RES_SEL_PAIR_MASK, res_sel_idx) || + (res_sel_idx == 0)); + return FIELD_PREP(ETM4_RES_SEL_PAIR_MASK, res_sel_idx) | + ETM4_RES_SEL_TYPE_PAIR; +} + /* * System instructions to access ETM registers. * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions @@ -824,7 +868,7 @@ struct etmv4_config { u32 eventctrl0; u32 eventctrl1; u32 stall_ctrl; - u32 ts_ctrl; + u32 ts_ctrl; /* TRCTSCTLR */ u32 ccctlr; u32 bb_ctrl; u32 vinst_ctrl; @@ -837,11 +881,11 @@ struct etmv4_config { u32 seq_rst; u32 seq_state; u8 cntr_idx; - u32 cntrldvr[ETMv4_MAX_CNTR]; - u32 cntr_ctrl[ETMv4_MAX_CNTR]; - u32 cntr_val[ETMv4_MAX_CNTR]; + u32 cntrldvr[ETMv4_MAX_CNTR]; /* TRCCNTRLDVRn */ + u32 cntr_ctrl[ETMv4_MAX_CNTR]; /* TRCCNTCTLRn */ + u32 cntr_val[ETMv4_MAX_CNTR]; /* TRCCNTVRn */ u8 res_idx; - u32 res_ctrl[ETM_MAX_RES_SEL]; + u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */ u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP]; u32 ss_status[ETM_MAX_SS_CMP]; From 20bc2ea23774a7655d21ce2243eccfdfd4405279 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:16 +0000 Subject: [PATCH 06/27] coresight: Hide unused ETMv3 format attributes ETMv3 only has a few attributes, and setting unused ones results in an error, so hide them to begin with. Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-4-4d319764cc58@linaro.org --- .../hwtracing/coresight/coresight-etm-perf.c | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 17afa0f4cdee..3805282b97e8 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -50,27 +50,23 @@ struct etm_ctxt { static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt); static DEFINE_PER_CPU(struct coresight_device *, csdev_src); -/* - * The PMU formats were orignally for ETMv3.5/PTM's ETMCR 'config'; - * now take them as general formats and apply on all ETMs. - */ -PMU_FORMAT_ATTR(branch_broadcast, "config:"__stringify(ETM_OPT_BRANCH_BROADCAST)); PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); -/* contextid1 enables tracing CONTEXTIDR_EL1 for ETMv4 */ -PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID)); -/* contextid2 enables tracing CONTEXTIDR_EL2 for ETMv4 */ -PMU_FORMAT_ATTR(contextid2, "config:" __stringify(ETM_OPT_CTXTID2)); PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK)); +PMU_FORMAT_ATTR(sinkid, "config2:0-31"); + +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) +PMU_FORMAT_ATTR(branch_broadcast, "config:"__stringify(ETM_OPT_BRANCH_BROADCAST)); +/* contextid1 enables tracing CONTEXTIDR_EL1*/ +PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID)); +/* contextid2 enables tracing CONTEXTIDR_EL2*/ +PMU_FORMAT_ATTR(contextid2, "config:" __stringify(ETM_OPT_CTXTID2)); /* preset - if sink ID is used as a configuration selector */ PMU_FORMAT_ATTR(preset, "config:0-3"); -/* Sink ID - same for all ETMs */ -PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); - /* * contextid always traces the "PID". The PID is in CONTEXTIDR_EL1 * when the kernel is running at EL1; when the kernel is at EL2, @@ -82,27 +78,34 @@ static ssize_t format_attr_contextid_show(struct device *dev, { int pid_fmt = ETM_OPT_CTXTID; -#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) pid_fmt = is_kernel_in_hyp_mode() ? ETM_OPT_CTXTID2 : ETM_OPT_CTXTID; -#endif return sprintf(page, "config:%d\n", pid_fmt); } static struct device_attribute format_attr_contextid = __ATTR(contextid, 0444, format_attr_contextid_show, NULL); +#endif +/* + * ETMv3 only uses the first 3 attributes for programming itself (see + * ETM3X_SUPPORTED_OPTIONS). Sink ID is also supported for selecting a + * sink in both, but not used for configuring the ETM. The remaining + * attributes are ETMv4 specific. + */ static struct attribute *etm_config_formats_attr[] = { &format_attr_cycacc.attr, - &format_attr_contextid.attr, - &format_attr_contextid1.attr, - &format_attr_contextid2.attr, &format_attr_timestamp.attr, &format_attr_retstack.attr, &format_attr_sinkid.attr, +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) + &format_attr_contextid.attr, + &format_attr_contextid1.attr, + &format_attr_contextid2.attr, &format_attr_preset.attr, &format_attr_configid.attr, &format_attr_branch_broadcast.attr, &format_attr_cc_threshold.attr, +#endif NULL, }; From 458db6257149f3959469c880de80eba3e2494479 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:17 +0000 Subject: [PATCH 07/27] coresight: Define format attributes with GEN_PMU_FORMAT_ATTR() This allows us to define and consume them in a unified way in later commits. A lot of the existing code has open coded bit shifts or direct usage of whole config values which is error prone and hides which bits are in use and which are free. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-5-4d319764cc58@linaro.org --- .../hwtracing/coresight/coresight-etm-perf.c | 21 +++++++------ .../hwtracing/coresight/coresight-etm-perf.h | 31 +++++++++++++++++++ 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 3805282b97e8..bf4b105e0f41 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -50,22 +51,22 @@ struct etm_ctxt { static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt); static DEFINE_PER_CPU(struct coresight_device *, csdev_src); -PMU_FORMAT_ATTR(cycacc, "config:" __stringify(ETM_OPT_CYCACC)); -PMU_FORMAT_ATTR(timestamp, "config:" __stringify(ETM_OPT_TS)); -PMU_FORMAT_ATTR(retstack, "config:" __stringify(ETM_OPT_RETSTK)); -PMU_FORMAT_ATTR(sinkid, "config2:0-31"); +GEN_PMU_FORMAT_ATTR(cycacc); +GEN_PMU_FORMAT_ATTR(timestamp); +GEN_PMU_FORMAT_ATTR(retstack); +GEN_PMU_FORMAT_ATTR(sinkid); #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) -PMU_FORMAT_ATTR(branch_broadcast, "config:"__stringify(ETM_OPT_BRANCH_BROADCAST)); +GEN_PMU_FORMAT_ATTR(branch_broadcast); /* contextid1 enables tracing CONTEXTIDR_EL1*/ -PMU_FORMAT_ATTR(contextid1, "config:" __stringify(ETM_OPT_CTXTID)); +GEN_PMU_FORMAT_ATTR(contextid1); /* contextid2 enables tracing CONTEXTIDR_EL2*/ -PMU_FORMAT_ATTR(contextid2, "config:" __stringify(ETM_OPT_CTXTID2)); +GEN_PMU_FORMAT_ATTR(contextid2); /* preset - if sink ID is used as a configuration selector */ -PMU_FORMAT_ATTR(preset, "config:0-3"); +GEN_PMU_FORMAT_ATTR(preset); /* config ID - set if a system configuration is selected */ -PMU_FORMAT_ATTR(configid, "config2:32-63"); -PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); +GEN_PMU_FORMAT_ATTR(configid); +GEN_PMU_FORMAT_ATTR(cc_threshold); /* * contextid always traces the "PID". The PID is in CONTEXTIDR_EL1 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 5febbcdb8696..c794087a0e99 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -20,6 +20,37 @@ struct cscfg_config_desc; */ #define ETM_ADDR_CMP_MAX 8 +#define ATTR_CFG_FLD_preset_CFG config +#define ATTR_CFG_FLD_preset_LO 0 +#define ATTR_CFG_FLD_preset_HI 3 +#define ATTR_CFG_FLD_branch_broadcast_CFG config +#define ATTR_CFG_FLD_branch_broadcast_LO 8 +#define ATTR_CFG_FLD_branch_broadcast_HI 8 +#define ATTR_CFG_FLD_cycacc_CFG config +#define ATTR_CFG_FLD_cycacc_LO 12 +#define ATTR_CFG_FLD_cycacc_HI 12 +#define ATTR_CFG_FLD_contextid1_CFG config +#define ATTR_CFG_FLD_contextid1_LO 14 +#define ATTR_CFG_FLD_contextid1_HI 14 +#define ATTR_CFG_FLD_contextid2_CFG config +#define ATTR_CFG_FLD_contextid2_LO 15 +#define ATTR_CFG_FLD_contextid2_HI 15 +#define ATTR_CFG_FLD_timestamp_CFG config +#define ATTR_CFG_FLD_timestamp_LO 28 +#define ATTR_CFG_FLD_timestamp_HI 28 +#define ATTR_CFG_FLD_retstack_CFG config +#define ATTR_CFG_FLD_retstack_LO 29 +#define ATTR_CFG_FLD_retstack_HI 29 +#define ATTR_CFG_FLD_sinkid_CFG config2 +#define ATTR_CFG_FLD_sinkid_LO 0 +#define ATTR_CFG_FLD_sinkid_HI 31 +#define ATTR_CFG_FLD_configid_CFG config2 +#define ATTR_CFG_FLD_configid_LO 32 +#define ATTR_CFG_FLD_configid_HI 63 +#define ATTR_CFG_FLD_cc_threshold_CFG config3 +#define ATTR_CFG_FLD_cc_threshold_LO 0 +#define ATTR_CFG_FLD_cc_threshold_HI 11 + /** * struct etm_filter - single instruction range or start/stop configuration. * @start_addr: The address to start tracing on. From a1d19cd2b1a6c41783caa49fc28e89f434673198 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:18 +0000 Subject: [PATCH 08/27] coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() Currently we're programming attr->config directly into ETMCR after some validation. This obscures which fields are being used, and also makes it impossible to move fields around or use other configN fields in the future. Improve it by only reading the fields that are valid and then setting the appropriate ETMCR bits based on each one. The ETMCR_CTXID_SIZE part can be removed as it was never a valid option because it's not in ETM3X_SUPPORTED_OPTIONS. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-6-4d319764cc58@linaro.org --- .../coresight/coresight-etm3x-core.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index a5e809589d3e..4511fc2f8d72 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "coresight-etm.h" @@ -339,21 +340,22 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, if (attr->config & ~ETM3X_SUPPORTED_OPTIONS) return -EINVAL; - config->ctrl = attr->config; + config->ctrl = 0; - /* Don't trace contextID when runs in non-root PID namespace */ - if (!task_is_in_init_pid_ns(current)) - config->ctrl &= ~ETMCR_CTXID_SIZE; + if (ATTR_CFG_GET_FLD(attr, cycacc)) + config->ctrl |= ETMCR_CYC_ACC; + + if (ATTR_CFG_GET_FLD(attr, timestamp)) + config->ctrl |= ETMCR_TIMESTAMP_EN; /* - * Possible to have cores with PTM (supports ret stack) and ETM - * (never has ret stack) on the same SoC. So if we have a request - * for return stack that can't be honoured on this core then - * clear the bit - trace will still continue normally + * Possible to have cores with PTM (supports ret stack) and ETM (never + * has ret stack) on the same SoC. So only enable when it can be honored + * - trace will still continue normally otherwise. */ - if ((config->ctrl & ETMCR_RETURN_STACK) && - !(drvdata->etmccer & ETMCCER_RETSTACK)) - config->ctrl &= ~ETMCR_RETURN_STACK; + if (ATTR_CFG_GET_FLD(attr, retstack) && + (drvdata->etmccer & ETMCCER_RETSTACK)) + config->ctrl |= ETMCR_RETURN_STACK; return 0; } From d633fd22e8100d4363b0c44e6e92150d670bab71 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:19 +0000 Subject: [PATCH 09/27] coresight: Don't reject unrecognized ETMv3 format attributes config isn't the only field, there are also config1, config2, etc. Rejecting unrecognized attributes is therefore inconsistent as it wasn't done for all fields. It was only necessary when we were directly programming attr->config into ETMCR and didn't hide the unsupported fields, but now it's not needed so remove it. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-7-4d319764cc58@linaro.org --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 4511fc2f8d72..584d653eda81 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -333,13 +333,6 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, if (config->mode) etm_config_trace_mode(config); - /* - * At this time only cycle accurate, return stack and timestamp - * options are available. - */ - if (attr->config & ~ETM3X_SUPPORTED_OPTIONS) - return -EINVAL; - config->ctrl = 0; if (ATTR_CFG_GET_FLD(attr, cycacc)) From b945d3677754dc1031515d9cd1604d0b61bb9fa2 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:20 +0000 Subject: [PATCH 10/27] coresight: Interpret perf config with ATTR_CFG_GET_FLD() The "config:" string construction in format_attr_contextid_show() can be removed because it either showed the existing context1 or context2 formats which have already been generated, so can be called themselves. The other conversions are straightforward replacements. Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-8-4d319764cc58@linaro.org --- .../hwtracing/coresight/coresight-etm-perf.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index bf4b105e0f41..3c8a6f795094 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -77,10 +77,9 @@ static ssize_t format_attr_contextid_show(struct device *dev, struct device_attribute *attr, char *page) { - int pid_fmt = ETM_OPT_CTXTID; - - pid_fmt = is_kernel_in_hyp_mode() ? ETM_OPT_CTXTID2 : ETM_OPT_CTXTID; - return sprintf(page, "config:%d\n", pid_fmt); + if (is_kernel_in_hyp_mode()) + return contextid2_show(dev, attr, page); + return contextid1_show(dev, attr, page); } static struct device_attribute format_attr_contextid = @@ -319,7 +318,7 @@ static bool sinks_compatible(struct coresight_device *a, static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { - u32 id, cfg_hash; + u32 sink_hash, cfg_hash; int cpu = event->cpu; cpumask_t *mask; struct coresight_device *sink = NULL; @@ -332,13 +331,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, INIT_WORK(&event_data->work, free_event_data); /* First get the selected sink from user space. */ - if (event->attr.config2 & GENMASK_ULL(31, 0)) { - id = (u32)event->attr.config2; - sink = user_sink = coresight_get_sink_by_id(id); - } + sink_hash = ATTR_CFG_GET_FLD(&event->attr, sinkid); + if (sink_hash) + sink = user_sink = coresight_get_sink_by_id(sink_hash); /* check if user wants a coresight configuration selected */ - cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); + cfg_hash = ATTR_CFG_GET_FLD(&event->attr, configid); if (cfg_hash) { if (cscfg_activate_config(cfg_hash)) goto err; From afed86e6e141faa2c7433517c9d91ab4d7d9d443 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:21 +0000 Subject: [PATCH 11/27] coresight: Interpret ETMv4 config with ATTR_CFG_GET_FLD() Remove hard coded bitfield extractions and shifts and replace with ATTR_CFG_GET_FLD(). ETM4_CFG_BIT_BB was defined to give the register bit positions to userspace, TRCCONFIGR_BB should be used in the kernel so replace it. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-9-4d319764cc58@linaro.org --- .../coresight/coresight-etm4x-core.c | 44 ++++++++----------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 2ec2ae1fef58..b457f182efbe 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -780,17 +781,17 @@ static int etm4_parse_event_config(struct coresight_device *csdev, goto out; /* Go from generic option to ETMv4 specifics */ - if (attr->config & BIT(ETM_OPT_CYCACC)) { + if (ATTR_CFG_GET_FLD(attr, cycacc)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK; + cc_threshold = ATTR_CFG_GET_FLD(attr, cc_threshold); if (!cc_threshold) cc_threshold = ETM_CYC_THRESHOLD_DEFAULT; if (cc_threshold < drvdata->ccitmin) cc_threshold = drvdata->ccitmin; config->ccctlr = cc_threshold; } - if (attr->config & BIT(ETM_OPT_TS)) { + if (ATTR_CFG_GET_FLD(attr, timestamp)) { /* * Configure timestamps to be emitted at regular intervals in * order to correlate instructions executed on different CPUs @@ -810,17 +811,17 @@ static int etm4_parse_event_config(struct coresight_device *csdev, } /* Only trace contextID when runs in root PID namespace */ - if ((attr->config & BIT(ETM_OPT_CTXTID)) && + if (ATTR_CFG_GET_FLD(attr, contextid1) && task_is_in_init_pid_ns(current)) /* bit[6], Context ID tracing bit */ config->cfg |= TRCCONFIGR_CID; /* - * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID - * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the - * kernel is not running in EL2. + * If set bit contextid2 in perf config, this asks to trace VMID for + * recording CONTEXTIDR_EL2. Do not enable VMID tracing if the kernel + * is not running in EL2. */ - if (attr->config & BIT(ETM_OPT_CTXTID2)) { + if (ATTR_CFG_GET_FLD(attr, contextid2)) { if (!is_kernel_in_hyp_mode()) { ret = -EINVAL; goto out; @@ -831,26 +832,22 @@ static int etm4_parse_event_config(struct coresight_device *csdev, } /* return stack - enable if selected and supported */ - if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) + if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack) /* bit[12], Return stack enable bit */ config->cfg |= TRCCONFIGR_RS; /* - * Set any selected configuration and preset. - * - * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset) - * in the perf attributes defined in coresight-etm-perf.c. - * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config. - * A zero configid means no configuration active, preset = 0 means no preset selected. + * Set any selected configuration and preset. A zero configid means no + * configuration active, preset = 0 means no preset selected. */ - if (attr->config2 & GENMASK_ULL(63, 32)) { - cfg_hash = (u32)(attr->config2 >> 32); - preset = attr->config & 0xF; + cfg_hash = ATTR_CFG_GET_FLD(attr, configid); + if (cfg_hash) { + preset = ATTR_CFG_GET_FLD(attr, preset); ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); } /* branch broadcast - enable if selected and supported */ - if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { + if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) { if (!drvdata->trcbb) { /* * Missing BB support could cause silent decode errors @@ -859,7 +856,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, ret = -EINVAL; goto out; } else { - config->cfg |= BIT(ETM4_CFG_BIT_BB); + config->cfg |= TRCCONFIGR_BB; } } @@ -1083,11 +1080,8 @@ static int etm4_disable_perf(struct coresight_device *csdev, return -EINVAL; etm4_disable_hw(drvdata); - /* - * The config_id occupies bits 63:32 of the config2 perf event attr - * field. If this is non-zero then we will have enabled a config. - */ - if (attr->config2 & GENMASK_ULL(63, 32)) + /* If configid is non-zero then we will have enabled a config. */ + if (ATTR_CFG_GET_FLD(attr, configid)) cscfg_csdev_disable_active_config(csdev); /* From 3285c471d0c0b991e5efc96c1a8bcc9ace17b9b8 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:22 +0000 Subject: [PATCH 12/27] coresight: Remove misleading definitions ETM_OPT_* definitions duplicate the PMU format attributes that have always been published in sysfs. Hardcoding them here makes it misleading as to what the 'real' PMU API is and prevents attributes from being rearranged in the future. ETM4_CFG_BIT_* definitions just define what the Arm Architecture is which is not the responsibility of the kernel to do and doesn't scale to other registers or versions of ETM. It's not an actual software ABI/API and these definitions here mislead that it is. Any tools using the first ones would be broken anyway as they won't work when attributes are moved, so removing them is the right thing to do and will prompt a fix. Tools using the second ones can trivially redefine them locally. Perf also has its own copy of the headers so both of these things can be fixed up at a later date. Reviewed-by: Leo Yan Reviewed-by: Mike Leach Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-10-4d319764cc58@linaro.org --- include/linux/coresight-pmu.h | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 89b0ac0014b0..2e179abe472a 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -21,30 +21,6 @@ */ #define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) -/* - * Below are the definition of bit offsets for perf option, and works as - * arbitrary values for all ETM versions. - * - * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, - * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and - * directly use below macros as config bits. - */ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 - -/* ETMv4 CONFIGR programming bits for the ETM OPTs */ -#define ETM4_CFG_BIT_BB 3 -#define ETM4_CFG_BIT_CYCACC 4 -#define ETM4_CFG_BIT_CTXTID 6 -#define ETM4_CFG_BIT_VMID 7 -#define ETM4_CFG_BIT_TS 11 -#define ETM4_CFG_BIT_RETSTK 12 -#define ETM4_CFG_BIT_VMID_OPT 15 - /* * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. * Used to associate a CPU with the CoreSight Trace ID. From f4d2f5fec06a900214166136d31bdc6fe8ee00d1 Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:23 +0000 Subject: [PATCH 13/27] coresight: Prepare to allow setting the timestamp interval Timestamps are currently emitted at the maximum rate possible, which is much too frequent for most use cases. In the next commit, the timestamp field will be widened to take a value, so set the interval using the value now. Granular control is not required, so save space in the config by interpreting it as 2 ^ timestamp. And then 4 bits (0 - 15) will be enough to set the interval to be larger than the existing SYNC timestamp interval. No sysfs mode support is needed for this attribute because counter generated timestamps are only configured for Perf mode. Reviewed-by: Leo Yan Tested-by: Leo Yan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-11-4d319764cc58@linaro.org --- .../coresight/coresight-etm4x-core.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index b457f182efbe..7e9c923acf4b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -650,7 +650,7 @@ static void etm4_enable_sysfs_smp_call(void *info) * +--------------+ * | * +------v-------+ - * | Counter x | (reload to 1 on underflow) + * | Counter x | (reload to 2 ^ (ts_level - 1) on underflow) * +--------------+ * | * +------v--------------+ @@ -661,7 +661,8 @@ static void etm4_enable_sysfs_smp_call(void *info) * | Timestamp Generator | (timestamp on resource y) * +----------------------+ */ -static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) +static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, + u8 ts_level) { int ctridx; int rselector; @@ -703,12 +704,8 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) return -ENOSPC; } - /* - * Initialise original and reload counter value to the smallest - * possible value in order to get as much precision as we can. - */ - config->cntr_val[ctridx] = 1; - config->cntrldvr[ctridx] = 1; + /* Initialise original and reload counter value. */ + config->cntr_val[ctridx] = config->cntrldvr[ctridx] = 1 << (ts_level - 1); /* * Trace Counter Control Register TRCCNTCTLRn @@ -756,6 +753,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; int preset, cc_threshold; + u8 ts_level; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -791,13 +789,15 @@ static int etm4_parse_event_config(struct coresight_device *csdev, cc_threshold = drvdata->ccitmin; config->ccctlr = cc_threshold; } - if (ATTR_CFG_GET_FLD(attr, timestamp)) { + + ts_level = ATTR_CFG_GET_FLD(attr, timestamp); + if (ts_level) { /* * Configure timestamps to be emitted at regular intervals in * order to correlate instructions executed on different CPUs * (CPU-wide trace scenarios). */ - ret = etm4_config_timestamp_event(drvdata); + ret = etm4_config_timestamp_event(drvdata, ts_level); /* * No need to go further if timestamp intervals can't From 6c75940eb76db6ed003eaf8cca296ade9dd1f46d Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:24 +0000 Subject: [PATCH 14/27] coresight: Extend width of timestamp format attribute 'timestamp' is currently 1 bit wide for on/off. To enable setting different intervals, extend it to 4 bits wide. Keep the old bit position for backward compatibility ("deprecated_timestamp") but don't publish in the format/ folder. It will be removed from the documentation and can be removed completely after enough time has passed. ETM3x doesn't support different intervals, so validate that the value is either 0 or 1. Tools that read the bit positions from the format/ folder will continue to work as before, setting either 0 or 1 for off/on. Tools that incorrectly didn't do this and set the ETM_OPT_TS bit directly will also continue to work because that old bit is still checked. This avoids adding a second timestamp attribute for setting the interval. This would be awkward to use because tools would have to be updated to ensure that the timestamps are always enabled when an interval is set, and the driver would have to validate that both options are provided together. All this does is implement the semantics of a single enum but spread over multiple fields. Reviewed-by: Leo Yan Tested-by: Leo Yan Tested-by: Jie Gan Signed-off-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-12-4d319764cc58@linaro.org --- .../hwtracing/coresight/coresight-etm-perf.h | 13 ++++++--- .../coresight/coresight-etm3x-core.c | 12 ++++++++- .../coresight/coresight-etm4x-core.c | 27 +++++++++++-------- 3 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index c794087a0e99..24d929428633 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -23,6 +23,9 @@ struct cscfg_config_desc; #define ATTR_CFG_FLD_preset_CFG config #define ATTR_CFG_FLD_preset_LO 0 #define ATTR_CFG_FLD_preset_HI 3 +#define ATTR_CFG_FLD_timestamp_CFG config +#define ATTR_CFG_FLD_timestamp_LO 4 +#define ATTR_CFG_FLD_timestamp_HI 7 #define ATTR_CFG_FLD_branch_broadcast_CFG config #define ATTR_CFG_FLD_branch_broadcast_LO 8 #define ATTR_CFG_FLD_branch_broadcast_HI 8 @@ -35,9 +38,13 @@ struct cscfg_config_desc; #define ATTR_CFG_FLD_contextid2_CFG config #define ATTR_CFG_FLD_contextid2_LO 15 #define ATTR_CFG_FLD_contextid2_HI 15 -#define ATTR_CFG_FLD_timestamp_CFG config -#define ATTR_CFG_FLD_timestamp_LO 28 -#define ATTR_CFG_FLD_timestamp_HI 28 +/* + * Old position of 'timestamp' and not published in sysfs. Remove at a later + * date if necessary. + */ +#define ATTR_CFG_FLD_deprecated_timestamp_CFG config +#define ATTR_CFG_FLD_deprecated_timestamp_LO 28 +#define ATTR_CFG_FLD_deprecated_timestamp_HI 28 #define ATTR_CFG_FLD_retstack_CFG config #define ATTR_CFG_FLD_retstack_LO 29 #define ATTR_CFG_FLD_retstack_HI 29 diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 584d653eda81..57e4a21c8fdd 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -310,6 +310,7 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, { struct etm_config *config = &drvdata->config; struct perf_event_attr *attr = &event->attr; + u8 ts_level; if (!attr) return -EINVAL; @@ -338,7 +339,16 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, if (ATTR_CFG_GET_FLD(attr, cycacc)) config->ctrl |= ETMCR_CYC_ACC; - if (ATTR_CFG_GET_FLD(attr, timestamp)) + ts_level = max(ATTR_CFG_GET_FLD(attr, timestamp), + ATTR_CFG_GET_FLD(attr, deprecated_timestamp)); + + if (ts_level > 1) { + dev_dbg(&drvdata->csdev->dev, + "timestamp format attribute should be 0 (off) or 1 (on)\n"); + return -EINVAL; + } + + if (ts_level) config->ctrl |= ETMCR_TIMESTAMP_EN; /* diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7e9c923acf4b..d565a73f0042 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -750,6 +750,9 @@ static int etm4_parse_event_config(struct coresight_device *csdev, int ret = 0; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct etmv4_config *config = &drvdata->config; + struct perf_event_attr max_timestamp = { + .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, + }; struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; int preset, cc_threshold; @@ -790,21 +793,23 @@ static int etm4_parse_event_config(struct coresight_device *csdev, config->ccctlr = cc_threshold; } - ts_level = ATTR_CFG_GET_FLD(attr, timestamp); + ts_level = max(ATTR_CFG_GET_FLD(attr, timestamp), + ATTR_CFG_GET_FLD(attr, deprecated_timestamp)); if (ts_level) { /* - * Configure timestamps to be emitted at regular intervals in - * order to correlate instructions executed on different CPUs - * (CPU-wide trace scenarios). + * Don't do counter generated timestamps when ts_level == MAX. + * Leave only SYNC timestamps from TRCCONFIGR_TS. */ - ret = etm4_config_timestamp_event(drvdata, ts_level); + if (ts_level != ATTR_CFG_GET_FLD(&max_timestamp, timestamp)) { + ret = etm4_config_timestamp_event(drvdata, ts_level); - /* - * No need to go further if timestamp intervals can't - * be configured. - */ - if (ret) - goto out; + /* + * Error if user asked for timestamps but there was no + * free counter. + */ + if (ret) + goto out; + } /* bit[11], Global timestamp tracing bit */ config->cfg |= TRCCONFIGR_TS; From 19214ad0a4e38c371013cca0b2ea584aa2bee8dd Mon Sep 17 00:00:00 2001 From: James Clark Date: Fri, 28 Nov 2025 11:55:25 +0000 Subject: [PATCH 15/27] coresight: docs: Document etm4x timestamp interval option Document how the new field is used, maximum value and the interaction with SYNC timestamps. Tested-by: Leo Yan Signed-off-by: James Clark Reviewed-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-13-4d319764cc58@linaro.org --- Documentation/trace/coresight/coresight.rst | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 806699871b80..d461de4e067e 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -613,8 +613,20 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ - Session local version of the system wide setting: :ref:`ETM_MODE_RETURNSTACK ` * - timestamp - - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP - ` + - Controls generation and interval of timestamps. + + 0 = off, 1 = minimum interval .. 15 = maximum interval. + + Values 1 - 14 use a counter that decrements every cycle to generate a + timestamp on underflow. The reload value for the counter is 2 ^ (interval + - 1). If the value is 1 then the reload value is 1, if the value is 11 + then the reload value is 1024 etc. + + Setting the maximum interval (15) will disable the counter generated + timestamps, freeing the counter resource, leaving only ones emitted when + a SYNC packet is generated. The sync interval is controlled with + TRCSYNCPR.PERIOD which is every 4096 bytes of trace by default. + * - cc_threshold - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold From f9cc5b5a9e9a84d423cdc48882f1c93f1f90a32b Mon Sep 17 00:00:00 2001 From: Tao Zhang Date: Tue, 23 Dec 2025 18:09:50 +0800 Subject: [PATCH 16/27] coresight: tpda: add sysfs nodes for tpda cross-trigger configuration Introduce sysfs nodes to configure cross-trigger parameters for TPDA. These registers define the characteristics of cross-trigger packets, including generation frequency and flag values. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan [ Fix kernel version in the Documentation ] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251223-add_sysfs_nodes_to_configure_tpda-v8-1-4c95db608b62@oss.qualcomm.com --- .../testing/sysfs-bus-coresight-devices-tpda | 35 ++++++ drivers/hwtracing/coresight/coresight-tpda.c | 109 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tpda.h | 63 +++++++++- 3 files changed, 200 insertions(+), 7 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda new file mode 100644 index 000000000000..8519a08444ab --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -0,0 +1,35 @@ +What: /sys/bus/coresight/devices//trig_async_enable +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger synchronization sequence interface. + +What: /sys/bus/coresight/devices//trig_flag_ts_enable +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FLAG packet request interface. + +What: /sys/bus/coresight/devices//trig_freq_enable +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable cross trigger FREQ packet request interface. + +What: /sys/bus/coresight/devices//freq_ts_enable +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Enable/disable the timestamp for all FREQ packets. + +What: /sys/bus/coresight/devices//cmbchan_mode +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the CMB/MCMB channel mode for all enabled ports. + Value 0 means raw channel mapping mode. Value 1 means channel pair marking mode. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 3a3825d27f86..2186223ad33e 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -137,12 +137,32 @@ static int tpda_get_element_size(struct tpda_drvdata *drvdata, /* Settings pre enabling port control register */ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) { - u32 val; + u32 val = 0; - val = readl_relaxed(drvdata->base + TPDA_CR); - val &= ~TPDA_CR_ATID; val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + if (drvdata->trig_async) + val |= TPDA_CR_SRIE; + + if (drvdata->trig_flag_ts) + val |= TPDA_CR_FLRIE; + + if (drvdata->trig_freq) + val |= TPDA_CR_FRIE; + + if (drvdata->freq_ts) + val |= TPDA_CR_FREQTS; + + if (drvdata->cmbchan_mode) + val |= TPDA_CR_CMBCHANMODE; + writel_relaxed(val, drvdata->base + TPDA_CR); + + /* + * If FLRIE bit is set, set the master and channel + * id as zero + */ + if (drvdata->trig_flag_ts) + writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); } static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -258,6 +278,87 @@ static const struct coresight_ops tpda_cs_ops = { .link_ops = &tpda_link_ops, }; +/* Read cross-trigger register member */ +static ssize_t tpda_trig_sysfs_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_trig_sysfs_attribute *tpda_attr = + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FREQTS: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->freq_ts); + case FRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_freq); + case FLRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_flag_ts); + case SRIE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->trig_async); + case CMBCHANMODE: + return sysfs_emit(buf, "%u\n", (unsigned int)drvdata->cmbchan_mode); + + } + return -EINVAL; +} + +static ssize_t tpda_trig_sysfs_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_trig_sysfs_attribute *tpda_attr = + container_of(attr, struct tpda_trig_sysfs_attribute, attr); + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + switch (tpda_attr->mem) { + case FREQTS: + drvdata->freq_ts = !!val; + break; + case FRIE: + drvdata->trig_freq = !!val; + break; + case FLRIE: + drvdata->trig_flag_ts = !!val; + break; + case SRIE: + drvdata->trig_async = !!val; + break; + case CMBCHANMODE: + drvdata->cmbchan_mode = !!val; + break; + default: + return -EINVAL; + } + + return size; +} + +static struct attribute *tpda_attrs[] = { + tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), + tpda_trig_sysfs_rw(trig_freq_enable, FRIE), + tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), + tpda_trig_sysfs_rw(trig_async_enable, SRIE), + tpda_trig_sysfs_rw(cmbchan_mode, CMBCHANMODE), + NULL, +}; + +static struct attribute_group tpda_attr_grp = { + .attrs = tpda_attrs, +}; + +static const struct attribute_group *tpda_attr_grps[] = { + &tpda_attr_grp, + NULL, +}; + static int tpda_init_default_data(struct tpda_drvdata *drvdata) { int atid; @@ -273,6 +374,7 @@ static int tpda_init_default_data(struct tpda_drvdata *drvdata) return atid; drvdata->atid = atid; + drvdata->freq_ts = true; return 0; } @@ -316,6 +418,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &tpda_cs_ops; desc.pdata = adev->dev.platform_data; desc.dev = &adev->dev; + desc.groups = tpda_attr_grps; desc.access = CSDEV_ACCESS_IOMEM(base); drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index c6af3d2da3ef..c93732e04af2 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CORESIGHT_CORESIGHT_TPDA_H @@ -8,6 +8,25 @@ #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) +#define TPDA_FPID_CR (0x084) + +/* Cross trigger FREQ packets timestamp bit */ +#define TPDA_CR_FREQTS BIT(2) +/* Cross trigger FREQ packet request bit */ +#define TPDA_CR_FRIE BIT(3) +/* Cross trigger FLAG packet request interface bit */ +#define TPDA_CR_FLRIE BIT(4) +/* Cross trigger synchronization bit */ +#define TPDA_CR_SRIE BIT(5) +/* Bits 6 ~ 12 is for atid value */ +#define TPDA_CR_ATID GENMASK(12, 6) +/* + * Channel mode bit of the packetization of CMB/MCB traffic + * 0 - raw channel mapping mode + * 1 - channel pair marking mode + */ +#define TPDA_CR_CMBCHANMODE BIT(20) + /* Aggregator port enable bit */ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port CMB data set element size bit */ @@ -17,9 +36,6 @@ #define TPDA_MAX_INPORTS 32 -/* Bits 6 ~ 12 is for atid value */ -#define TPDA_CR_ATID GENMASK(12, 6) - /** * struct tpda_drvdata - specifics associated to an TPDA component * @base: memory mapped base address for this component. @@ -29,6 +45,11 @@ * @enable: enable status of the component. * @dsb_esize Record the DSB element size. * @cmb_esize Record the CMB element size. + * @trig_async: Enable/disable cross trigger synchronization sequence interface. + * @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface. + * @trig_freq: Enable/disable cross trigger FREQ packet request interface. + * @freq_ts: Enable/disable the timestamp for all FREQ packets. + * @cmbchan_mode: Configure the CMB/MCMB channel mode. */ struct tpda_drvdata { void __iomem *base; @@ -38,6 +59,40 @@ struct tpda_drvdata { u8 atid; u32 dsb_esize; u32 cmb_esize; + bool trig_async; + bool trig_flag_ts; + bool trig_freq; + bool freq_ts; + bool cmbchan_mode; }; +/* Enumerate members of global control register(cr) */ +enum tpda_cr_mem { + FREQTS, + FRIE, + FLRIE, + SRIE, + CMBCHANMODE +}; + +/** + * struct tpda_trig_sysfs_attribute - Record the member variables of cross + * trigger register that need to be operated by sysfs file + * @attr: The device attribute + * @mem: The member in the control register data structure + */ +struct tpda_trig_sysfs_attribute { + struct device_attribute attr; + enum tpda_cr_mem mem; +}; + +#define tpda_trig_sysfs_rw(name, mem) \ + (&((struct tpda_trig_sysfs_attribute[]) { \ + { \ + __ATTR(name, 0644, tpda_trig_sysfs_show, \ + tpda_trig_sysfs_store), \ + mem, \ + } \ + })[0].attr.attr) + #endif /* _CORESIGHT_CORESIGHT_TPDA_H */ From 8e1c358a3b0e69eb527bb6723366b92e982235c3 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 23 Dec 2025 18:09:51 +0800 Subject: [PATCH 17/27] coresight: tpda: add global_flush_req sysfs node Setting the global_flush_req register to 1 initiates a flush request for all enabled TPDA input ports. The register remains set until the flush operation is complete. Signed-off-by: Jie Gan [ Fix kernel version in the Documentation ] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251223-add_sysfs_nodes_to_configure_tpda-v8-2-4c95db608b62@oss.qualcomm.com --- .../testing/sysfs-bus-coresight-devices-tpda | 8 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 45 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 2 + 3 files changed, 55 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda index 8519a08444ab..acd354d7bdfa 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -33,3 +33,11 @@ Contact: Jinlong Mao , Tao Zhang /global_flush_req +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set global (all ports) flush request bit. The bit remains set until a + global flush request sequence completes. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index 2186223ad33e..d24a9098f1b1 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -341,7 +341,52 @@ static ssize_t tpda_trig_sysfs_store(struct device *dev, return size; } +static ssize_t global_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val = readl_relaxed(drvdata->base + TPDA_CR); + /* read global_flush_req bit */ + val &= TPDA_CR_FLREQ; + + return sysfs_emit(buf, "%lu\n", val); +} + +static ssize_t global_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (!drvdata->csdev->refcnt || !val) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val = readl_relaxed(drvdata->base + TPDA_CR); + /* set global_flush_req bit */ + val |= TPDA_CR_FLREQ; + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_CR); + CS_LOCK(drvdata->base); + + return size; +} +static DEVICE_ATTR_RW(global_flush_req); + static struct attribute *tpda_attrs[] = { + &dev_attr_global_flush_req.attr, tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), tpda_trig_sysfs_rw(trig_freq_enable, FRIE), tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index c93732e04af2..1cc9253293ec 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,8 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) +/* Cross trigger global (all ports) flush request bit */ +#define TPDA_CR_FLREQ BIT(0) /* Cross trigger FREQ packets timestamp bit */ #define TPDA_CR_FREQTS BIT(2) /* Cross trigger FREQ packet request bit */ From 33f04ead7c498f29bca875783f13542e5ccd17ac Mon Sep 17 00:00:00 2001 From: Tao Zhang Date: Tue, 23 Dec 2025 18:09:52 +0800 Subject: [PATCH 18/27] coresight: tpda: add logic to configure TPDA_SYNCR register The TPDA_SYNC counter tracks the number of bytes transferred from the aggregator. When this count reaches the value programmed in the TPDA_SYNCR register, an ASYNC request is triggered, allowing userspace tools to accurately parse each valid packet. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan [ Fix kernel version in Documentation ] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251223-add_sysfs_nodes_to_configure_tpda-v8-3-4c95db608b62@oss.qualcomm.com --- .../testing/sysfs-bus-coresight-devices-tpda | 18 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 90 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 10 +++ 3 files changed, 118 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda index acd354d7bdfa..bd86e6fd961d 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -41,3 +41,21 @@ Contact: Jinlong Mao , Tao Zhang /syncr_mode +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set mode the of the syncr counter. + mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests + mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K + data by writing a value 13 to the COUNT[11:7] field. + +What: /sys/bus/coresight/devices//syncr_count +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Set value the of the syncr counter. + Range: 0-4095 diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index d24a9098f1b1..deb5a646a04c 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -163,6 +163,20 @@ static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) */ if (drvdata->trig_flag_ts) writel_relaxed(0x0, drvdata->base + TPDA_FPID_CR); + + /* Initialize with a value of 0 */ + val = 0; + if (drvdata->syncr_mode) + val |= TPDA_SYNCR_MODE_CTRL_MASK; + + if (drvdata->syncr_count > 0 && + drvdata->syncr_count < TPDA_SYNCR_COUNT_MASK) + val |= drvdata->syncr_count; + else + /* Program the count to its MAX value by default */ + val |= TPDA_SYNCR_COUNT_MASK; + + writel_relaxed(val, drvdata->base + TPDA_SYNCR); } static int tpda_enable_port(struct tpda_drvdata *drvdata, int port) @@ -385,8 +399,84 @@ static ssize_t global_flush_req_store(struct device *dev, } static DEVICE_ATTR_RW(global_flush_req); +static ssize_t syncr_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val, syncr_val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + syncr_val = readl_relaxed(drvdata->base + TPDA_SYNCR); + val = FIELD_GET(TPDA_SYNCR_MODE_CTRL_MASK, syncr_val); + + return sysfs_emit(buf, "%lu\n", val); +} + +static ssize_t syncr_mode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + /* set the mode when first enabling the device */ + drvdata->syncr_mode = !!val; + + return size; +} +static DEVICE_ATTR_RW(syncr_mode); + +static ssize_t syncr_count_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val = readl_relaxed(drvdata->base + TPDA_SYNCR); + val &= TPDA_SYNCR_COUNT_MASK; + + return sysfs_emit(buf, "%lu\n", val); +} + +static ssize_t syncr_count_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + if (val > TPDA_SYNCR_COUNT_MASK) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + drvdata->syncr_count = val; + + return size; +} +static DEVICE_ATTR_RW(syncr_count); + static struct attribute *tpda_attrs[] = { &dev_attr_global_flush_req.attr, + &dev_attr_syncr_mode.attr, + &dev_attr_syncr_count.attr, tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), tpda_trig_sysfs_rw(trig_freq_enable, FRIE), tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 1cc9253293ec..56d35697303a 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -9,6 +9,7 @@ #define TPDA_CR (0x000) #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) +#define TPDA_SYNCR (0x08C) /* Cross trigger global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) @@ -36,6 +37,11 @@ /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) +/* TPDA_SYNCR count mask */ +#define TPDA_SYNCR_COUNT_MASK GENMASK(11, 0) +/* TPDA_SYNCR mode control bit */ +#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12) + #define TPDA_MAX_INPORTS 32 /** @@ -52,6 +58,8 @@ * @trig_freq: Enable/disable cross trigger FREQ packet request interface. * @freq_ts: Enable/disable the timestamp for all FREQ packets. * @cmbchan_mode: Configure the CMB/MCMB channel mode. + * @syncr_mode: Setting the mode for counting packets. + * @syncr_count: Setting the value of the count. */ struct tpda_drvdata { void __iomem *base; @@ -66,6 +74,8 @@ struct tpda_drvdata { bool trig_freq; bool freq_ts; bool cmbchan_mode; + bool syncr_mode; + u32 syncr_count; }; /* Enumerate members of global control register(cr) */ From a089d585a7f4fa85b5e1d78c5308e27a0d875b17 Mon Sep 17 00:00:00 2001 From: Tao Zhang Date: Tue, 23 Dec 2025 18:09:53 +0800 Subject: [PATCH 19/27] coresight: tpda: add sysfs node to flush specific port Setting bit i in the TPDA_FLUSH_CR register initiates a flush request for port i, forcing the data to synchronize and be transmitted to the sink device. Signed-off-by: Tao Zhang Reviewed-by: James Clark Co-developed-by: Jie Gan Signed-off-by: Jie Gan [ Fix kernel version in Documentation ] Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251223-add_sysfs_nodes_to_configure_tpda-v8-4-4c95db608b62@oss.qualcomm.com --- .../testing/sysfs-bus-coresight-devices-tpda | 8 ++++ drivers/hwtracing/coresight/coresight-tpda.c | 40 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpda.h | 1 + 3 files changed, 49 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda index bd86e6fd961d..54f05964a360 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -59,3 +59,11 @@ Contact: Jinlong Mao , Tao Zhang /port_flush_req +Date: December 2025 +KernelVersion: 6.20 +Contact: Jinlong Mao , Tao Zhang , Jie Gan +Description: + (RW) Configure the bit i to requests a flush operation of port i on the TPDA. + The requested bit(s) remain set until the flush request completes. diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index deb5a646a04c..7055f8f13427 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -473,10 +473,50 @@ static ssize_t syncr_count_store(struct device *dev, } static DEVICE_ATTR_RW(syncr_count); +static ssize_t port_flush_req_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + + if (!drvdata->csdev->refcnt) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + val = readl_relaxed(drvdata->base + TPDA_FLUSH_CR); + + return sysfs_emit(buf, "0x%lx\n", val); +} + +static ssize_t port_flush_req_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(dev->parent); + u32 val; + + if (kstrtou32(buf, 0, &val)) + return -EINVAL; + + if (!drvdata->csdev->refcnt || !val) + return -EINVAL; + + guard(spinlock)(&drvdata->spinlock); + CS_UNLOCK(drvdata->base); + writel_relaxed(val, drvdata->base + TPDA_FLUSH_CR); + CS_LOCK(drvdata->base); + + return size; +} +static DEVICE_ATTR_RW(port_flush_req); + static struct attribute *tpda_attrs[] = { &dev_attr_global_flush_req.attr, &dev_attr_syncr_mode.attr, &dev_attr_syncr_count.attr, + &dev_attr_port_flush_req.attr, tpda_trig_sysfs_rw(freq_ts_enable, FREQTS), tpda_trig_sysfs_rw(trig_freq_enable, FRIE), tpda_trig_sysfs_rw(trig_flag_ts_enable, FLRIE), diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 56d35697303a..a090352009bb 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -10,6 +10,7 @@ #define TPDA_Pn_CR(n) (0x004 + (n * 4)) #define TPDA_FPID_CR (0x084) #define TPDA_SYNCR (0x08C) +#define TPDA_FLUSH_CR (0x090) /* Cross trigger global (all ports) flush request bit */ #define TPDA_CR_FLREQ BIT(0) From 98baf887b1e9ae69178b25ed49cda1a6f01905a3 Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Wed, 7 Jan 2026 11:26:23 +0000 Subject: [PATCH 20/27] coresight: tpda: Fix intendation for sysfs interface documentation linux-next merge complains about build break with make htmldocs : Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda:45: ERROR: Unexpected indentation. [docutils] Closes: https://lkml.kernel.org/r/20260106114933.638b073f@canb.auug.org.au Reported-by: Stephen Rothwell Cc: Stephen Rothwell Cc: Jie Gan Cc: Tao Zhang Signed-off-by: Suzuki K Poulose --- Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda index 54f05964a360..650431feae45 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpda @@ -50,7 +50,7 @@ Description: (RW) Set mode the of the syncr counter. mode 0 - COUNT[11:0] value represents the approximate number of bytes moved between two ASYNC packet requests mode 1 - the bits COUNT[11:7] are used as a power of 2. for example, we could insert an async packet every 8K - data by writing a value 13 to the COUNT[11:7] field. + data by writing a value 13 to the COUNT[11:7] field. What: /sys/bus/coresight/devices//syncr_count Date: December 2025 From 1feb0377b9b816f89a04fc381eb19fc6bac9f4a4 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Thu, 8 Jan 2026 16:24:27 +0100 Subject: [PATCH 21/27] coresight: etm3x: Fix cpulocked warning on cpuhp When changes [1] and [2] have been applied to the driver etm4x, the same modifications have been also collapsed in [3] and applied in one shot to the driver etm3x. While doing this, the driver etm3x has not been aligned to etm4x on the use of non cpuslocked version of cpuhp callback setup APIs. The current code triggers two run-time warnings when the kernel is compiled with CONFIG_PROVE_LOCKING=y. Use non cpuslocked version of cpuhp callback setup APIs in driver etm3x, aligning it to the driver etm4x. [1] commit 2d1a8bfb61ec ("coresight: etm4x: Fix etm4_count race by moving cpuhp callbacks to init") [2] commit 22a550a306ad ("coresight: etm4x: Allow etm4x to be built as a module") [3] commit 97fe626ce64c ("coresight: etm3x: Allow etm3x to be built as a module") Fixes: 97fe626ce64c ("coresight: etm3x: Allow etm3x to be built as a module") Signed-off-by: Antonio Borneo Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260108152427.357379-1-antonio.borneo@foss.st.com --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index 57e4a21c8fdd..a547a6d2e0bd 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -800,16 +800,16 @@ static int __init etm_hp_setup(void) { int ret; - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, - "arm/coresight:starting", - etm_starting_cpu, etm_dying_cpu); + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, + "arm/coresight:starting", + etm_starting_cpu, etm_dying_cpu); if (ret) return ret; - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, - "arm/coresight:online", - etm_online_cpu, NULL); + ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, + "arm/coresight:online", + etm_online_cpu, NULL); /* HP dyn state ID returned in ret on success */ if (ret > 0) { From 2b3625a83245e414a0a7abe3906a9972a40b1940 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 3 Dec 2025 20:43:07 -0800 Subject: [PATCH 22/27] dt-bindings: arm: qcom: Add Coresight Interconnect TNOC Add device tree binding for Qualcomm Coresight Interconnect Trace Network On Chip (ITNOC). This TNOC acts as a CoreSight graph link that forwards trace data from a subsystem to the Aggregator TNOC, without aggregation or ATID functionality. Signed-off-by: Yuanfang Zhang Reviewed-by: Rob Herring (Arm) Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251203-itnoc-v5-1-5b97c63f2268@oss.qualcomm.com --- .../bindings/arm/qcom,coresight-itnoc.yaml | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml new file mode 100644 index 000000000000..8936bb7c3e8e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-itnoc.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-itnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Interconnect Trace Network On Chip - ITNOC + +maintainers: + - Yuanfang Zhang + +description: + The Interconnect TNOC is a CoreSight graph link that forwards trace data + from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it + does not have aggregation and ATID functionality. + +properties: + $nodename: + pattern: "^itnoc(@[0-9a-f]+)?$" + + compatible: + const: qcom,coresight-itnoc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-9a-f]{1,2})?$': + description: Input connections from CoreSight Trace Bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: out connections to aggregator TNOC + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + itnoc@109ac000 { + compatible = "qcom,coresight-itnoc"; + reg = <0x109ac000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tn_ic_in_tpdm_dcc: endpoint { + remote-endpoint = <&tpdm_dcc_out_tn_ic>; + }; + }; + }; + + out-ports { + port { + tn_ic_out_tnoc_aggr: endpoint { + /* to Aggregator TNOC input */ + remote-endpoint = <&tn_ag_in_tn_ic>; + }; + }; + }; + }; +... From 5799dee92dc244d750043373bf2f634e13398d52 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 3 Dec 2025 20:43:08 -0800 Subject: [PATCH 23/27] coresight-tnoc: add platform driver to support Interconnect TNOC This patch adds platform driver support for the CoreSight Interconnect TNOC, Interconnect TNOC is a CoreSight link that forwards trace data from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it does not have aggregation and ATID functionality. Key changes: - Add platform driver `coresight-itnoc` with device tree match support. - Refactor probe logic into a common `_tnoc_probe()` function. - Conditionally initialize ATID only for AMBA-based TNOC blocks. Signed-off-by: Yuanfang Zhang Reviewed-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251203-itnoc-v5-2-5b97c63f2268@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-tnoc.c | 113 +++++++++++++++++-- 1 file changed, 102 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index ff9a0a9cfe96..affd8204b534 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -34,6 +34,7 @@ * @base: memory mapped base address for this component. * @dev: device node for trace_noc_drvdata. * @csdev: component vitals needed by the framework. + * @pclk: APB clock if present, otherwise NULL * @spinlock: serialize enable/disable operation. * @atid: id for the trace packet. */ @@ -41,8 +42,9 @@ struct trace_noc_drvdata { void __iomem *base; struct device *dev; struct coresight_device *csdev; + struct clk *pclk; spinlock_t spinlock; - u32 atid; + int atid; }; DEFINE_CORESIGHT_DEVLIST(trace_noc_devs, "traceNoc"); @@ -51,6 +53,12 @@ static void trace_noc_enable_hw(struct trace_noc_drvdata *drvdata) { u32 val; + /* No valid ATID, simply enable the unit */ + if (drvdata->atid == -EOPNOTSUPP) { + writel(TRACE_NOC_CTRL_PORTEN, drvdata->base + TRACE_NOC_CTRL); + return; + } + /* Set ATID */ writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD); @@ -124,6 +132,11 @@ static int trace_noc_init_default_data(struct trace_noc_drvdata *drvdata) { int atid; + if (!dev_is_amba(drvdata->dev)) { + drvdata->atid = -EOPNOTSUPP; + return 0; + } + atid = coresight_trace_id_get_system_id(); if (atid < 0) return atid; @@ -149,8 +162,21 @@ static struct attribute *coresight_tnoc_attrs[] = { NULL, }; +static umode_t trace_id_is_visible(struct kobject *kobj, + struct attribute *attr, int idx) +{ + struct device *dev = kobj_to_dev(kobj); + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + if (attr == &dev_attr_traceid.attr && drvdata->atid < 0) + return 0; + + return attr->mode; +} + static const struct attribute_group coresight_tnoc_group = { .attrs = coresight_tnoc_attrs, + .is_visible = trace_id_is_visible, }; static const struct attribute_group *coresight_tnoc_groups[] = { @@ -158,9 +184,8 @@ static const struct attribute_group *coresight_tnoc_groups[] = { NULL, }; -static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) +static int _tnoc_probe(struct device *dev, struct resource *res) { - struct device *dev = &adev->dev; struct coresight_platform_data *pdata; struct trace_noc_drvdata *drvdata; struct coresight_desc desc = { 0 }; @@ -173,16 +198,20 @@ static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) pdata = coresight_get_platform_data(dev); if (IS_ERR(pdata)) return PTR_ERR(pdata); - adev->dev.platform_data = pdata; + dev->platform_data = pdata; drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; - drvdata->dev = &adev->dev; + drvdata->dev = dev; dev_set_drvdata(dev, drvdata); - drvdata->base = devm_ioremap_resource(dev, &adev->res); + ret = coresight_get_enable_clocks(dev, &drvdata->pclk, NULL); + if (ret) + return ret; + + drvdata->base = devm_ioremap_resource(dev, res); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); @@ -195,20 +224,31 @@ static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) desc.ops = &trace_noc_cs_ops; desc.type = CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.pdata = adev->dev.platform_data; - desc.dev = &adev->dev; + desc.pdata = pdata; + desc.dev = dev; desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); desc.groups = coresight_tnoc_groups; drvdata->csdev = coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { - coresight_trace_id_put_system_id(drvdata->atid); + if (drvdata->atid > 0) + coresight_trace_id_put_system_id(drvdata->atid); return PTR_ERR(drvdata->csdev); } - pm_runtime_put(&adev->dev); return 0; } +static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + + ret = _tnoc_probe(&adev->dev, &adev->res); + if (!ret) + pm_runtime_put(&adev->dev); + + return ret; +} + static void trace_noc_remove(struct amba_device *adev) { struct trace_noc_drvdata *drvdata = dev_get_drvdata(&adev->dev); @@ -240,7 +280,58 @@ static struct amba_driver trace_noc_driver = { .id_table = trace_noc_ids, }; -module_amba_driver(trace_noc_driver); +static int itnoc_probe(struct platform_device *pdev) +{ + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + int ret; + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + ret = _tnoc_probe(&pdev->dev, res); + pm_runtime_put(&pdev->dev); + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static void itnoc_remove(struct platform_device *pdev) +{ + struct trace_noc_drvdata *drvdata = platform_get_drvdata(pdev); + + coresight_unregister(drvdata->csdev); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id itnoc_of_match[] = { + { .compatible = "qcom,coresight-itnoc" }, + {} +}; +MODULE_DEVICE_TABLE(of, itnoc_of_match); + +static struct platform_driver itnoc_driver = { + .probe = itnoc_probe, + .remove = itnoc_remove, + .driver = { + .name = "coresight-itnoc", + .of_match_table = itnoc_of_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init tnoc_init(void) +{ + return coresight_init_driver("tnoc", &trace_noc_driver, &itnoc_driver, THIS_MODULE); +} + +static void __exit tnoc_exit(void) +{ + coresight_remove_driver(&trace_noc_driver, &itnoc_driver); +} +module_init(tnoc_init); +module_exit(tnoc_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Trace NOC driver"); From 4d9024d14d1bacb097f33ef7d3ed1696d6a46c88 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 3 Dec 2025 20:43:09 -0800 Subject: [PATCH 24/27] coresight-tnoc: Add runtime PM support for Interconnect TNOC This patch adds runtime power management support for platform-based CoreSight Interconnect TNOC (ITNOC) devices. It introduces suspend and resume callbacks to manage the APB clock (`pclk`) during device runtime transitions. Signed-off-by: Yuanfang Zhang Reviewed-by: Leo Yan Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251203-itnoc-v5-3-5b97c63f2268@oss.qualcomm.com --- drivers/hwtracing/coresight/coresight-tnoc.c | 23 ++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c index affd8204b534..1128612e70a7 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -305,6 +305,28 @@ static void itnoc_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); } +#ifdef CONFIG_PM +static int itnoc_runtime_suspend(struct device *dev) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev); + + clk_disable_unprepare(drvdata->pclk); + + return 0; +} + +static int itnoc_runtime_resume(struct device *dev) +{ + struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev); + + return clk_prepare_enable(drvdata->pclk); +} +#endif + +static const struct dev_pm_ops itnoc_dev_pm_ops = { + SET_RUNTIME_PM_OPS(itnoc_runtime_suspend, itnoc_runtime_resume, NULL) +}; + static const struct of_device_id itnoc_of_match[] = { { .compatible = "qcom,coresight-itnoc" }, {} @@ -318,6 +340,7 @@ static struct platform_driver itnoc_driver = { .name = "coresight-itnoc", .of_match_table = itnoc_of_match, .suppress_bind_attrs = true, + .pm = &itnoc_dev_pm_ops, }, }; From 5da8c55dd879347db64a1d28e66f6d7f62652373 Mon Sep 17 00:00:00 2001 From: Yicong Yang Date: Wed, 21 Jan 2026 18:15:41 +0800 Subject: [PATCH 25/27] coresight: tmc: Add missing doc including reading and etr_mode of struct tmc_drvdata tmc_drvdata::reading is used to indicate whether a reading process is performed through /dev/xyz.tmc. tmc_drvdata::etr_mode is used to store the Coresight TMC-ETR buffer mode selected by the user. Document them. Reviewed-by: James Clark Signed-off-by: Yicong Yang Reviewed-by: Leo Yan Signed-off-by: Junhao He Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260121101543.2017014-2-wangyushan12@huawei.com --- drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 95473d131032..319a354ede9f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -221,6 +221,7 @@ struct tmc_resrv_buf { * @pid: Process ID of the process that owns the session that is using * this component. For example this would be the pid of the Perf * process. + * @reading: buffer's in the reading through "/dev/xyz.tmc" entry * @stop_on_flush: Stop on flush trigger user configuration. * @buf: Snapshot of the trace data for ETF/ETB. * @etr_buf: details of buffer used in TMC-ETR @@ -233,6 +234,7 @@ struct tmc_resrv_buf { * @trigger_cntr: amount of words to store after a trigger. * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the * device configuration register (DEVID) + * @etr_mode: User preferred mode of the ETR device, default auto mode. * @idr: Holds etr_bufs allocated for this ETR. * @idr_mutex: Access serialisation for idr. * @sysfs_buf: SYSFS buffer for ETR. From e6e43e82c79c97917cbe356c07e8a6f3f982ab53 Mon Sep 17 00:00:00 2001 From: Yicong Yang Date: Wed, 21 Jan 2026 18:15:42 +0800 Subject: [PATCH 26/27] coresight: tmc-etr: Fix race condition between sysfs and perf mode When trying to run perf and sysfs mode simultaneously, the WARN_ON() in tmc_etr_enable_hw() is triggered sometimes: WARNING: CPU: 42 PID: 3911571 at drivers/hwtracing/coresight/coresight-tmc-etr.c:1060 tmc_etr_enable_hw+0xc0/0xd8 [coresight_tmc] [..snip..] Call trace: tmc_etr_enable_hw+0xc0/0xd8 [coresight_tmc] (P) tmc_enable_etr_sink+0x11c/0x250 [coresight_tmc] (L) tmc_enable_etr_sink+0x11c/0x250 [coresight_tmc] coresight_enable_path+0x1c8/0x218 [coresight] coresight_enable_sysfs+0xa4/0x228 [coresight] enable_source_store+0x58/0xa8 [coresight] dev_attr_store+0x20/0x40 sysfs_kf_write+0x4c/0x68 kernfs_fop_write_iter+0x120/0x1b8 vfs_write+0x2c8/0x388 ksys_write+0x74/0x108 __arm64_sys_write+0x24/0x38 el0_svc_common.constprop.0+0x64/0x148 do_el0_svc+0x24/0x38 el0_svc+0x3c/0x130 el0t_64_sync_handler+0xc8/0xd0 el0t_64_sync+0x1ac/0x1b0 ---[ end trace 0000000000000000 ]--- Since the enablement of sysfs mode is separeted into two critical regions, one for sysfs buffer allocation and another for hardware enablement, it's possible to race with the perf mode. Fix this by double check whether the perf mode's been used before enabling the hardware in sysfs mode. mode: [sysfs mode] [perf mode] tmc_etr_get_sysfs_buffer() spin_lock(&drvdata->spinlock) [sysfs buffer allocation] spin_unlock(&drvdata->spinlock) spin_lock(&drvdata->spinlock) tmc_etr_enable_hw() drvdata->etr_buf = etr_perf->etr_buf spin_unlock(&drvdata->spinlock) spin_lock(&drvdata->spinlock) tmc_etr_enable_hw() WARN_ON(drvdata->etr_buf) // WARN sicne etr_buf initialized at the perf side spin_unlock(&drvdata->spinlock) With this fix, we retain the check for CS_MODE_PERF in get_etr_sysfs_buf. This ensures we verify whether the perf mode's already running before we actually allocate the buffer. Then we can save the time of allocating/freeing the sysfs buffer if race with the perf mode. Fixes: 296b01fd106e ("coresight: Refactor out buffer allocation function for ETR") Signed-off-by: Yicong Yang Signed-off-by: Junhao He Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260121101543.2017014-3-wangyushan12@huawei.com --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index e0d83ee01b77..fc0a946053dd 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1306,6 +1306,19 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) raw_spin_lock_irqsave(&drvdata->spinlock, flags); + /* + * Since the sysfs buffer allocation and the hardware enablement is not + * in the same critical region, it's possible to race with the perf. + */ + if (coresight_get_mode(csdev) == CS_MODE_PERF) { + drvdata->sysfs_buf = NULL; + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + /* Free allocated memory out side of the spinlock */ + tmc_etr_free_sysfs_buf(sysfs_buf); + return -EBUSY; + } + /* * In sysFS mode we can have multiple writers per sink. Since this * sink is already enabled no memory is needed and the HW need not be From eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d Mon Sep 17 00:00:00 2001 From: Yicong Yang Date: Wed, 21 Jan 2026 18:15:43 +0800 Subject: [PATCH 27/27] coresight: tmc: Decouple the perf buffer allocation from sysfs mode Currently the perf buffer allocation follows the below logic: - if the required AUX buffer size if larger, allocate the buffer with the required size - otherwise allocate the size reference to the sysfs buffer size This is not useful as we only collect to one AUX data, so just try to allocate the buffer match the AUX buffer size. Suggested-by: Suzuki K Poulose Link: https://lore.kernel.org/linux-arm-kernel/df8967cd-2157-46a2-97d9-a1aea883cf63@arm.com/ Signed-off-by: Yicong Yang Signed-off-by: Junhao He Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260121101543.2017014-4-wangyushan12@huawei.com --- .../hwtracing/coresight/coresight-tmc-etr.c | 30 ++++++------------- 1 file changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index fc0a946053dd..cee82e52c4ea 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1367,9 +1367,7 @@ EXPORT_SYMBOL_GPL(tmc_etr_get_buffer); /* * alloc_etr_buf: Allocate ETR buffer for use by perf. - * The size of the hardware buffer is dependent on the size configured - * via sysfs and the perf ring buffer size. We prefer to allocate the - * largest possible size, scaling down the size by half until it + * Allocate the largest possible size, scaling down the size by half until it * reaches a minimum limit (1M), beyond which we give up. */ static struct etr_buf * @@ -1378,36 +1376,26 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, { int node; struct etr_buf *etr_buf; - unsigned long size; + ssize_t size; node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); - /* - * Try to match the perf ring buffer size if it is larger - * than the size requested via sysfs. - */ - if ((nr_pages << PAGE_SHIFT) > drvdata->size) { - etr_buf = tmc_alloc_etr_buf(drvdata, ((ssize_t)nr_pages << PAGE_SHIFT), - 0, node, NULL); - if (!IS_ERR(etr_buf)) - goto done; - } + + /* Use the minimum limit if the required size is smaller */ + size = nr_pages << PAGE_SHIFT; + size = max_t(ssize_t, size, TMC_ETR_PERF_MIN_BUF_SIZE); /* - * Else switch to configured size for this ETR - * and scale down until we hit the minimum limit. + * Try to allocate the required size for this ETR, if failed scale + * down until we hit the minimum limit. */ - size = drvdata->size; do { etr_buf = tmc_alloc_etr_buf(drvdata, size, 0, node, NULL); if (!IS_ERR(etr_buf)) - goto done; + return etr_buf; size /= 2; } while (size >= TMC_ETR_PERF_MIN_BUF_SIZE); return ERR_PTR(-ENOMEM); - -done: - return etr_buf; } static struct etr_buf *