torvalds/linux
3
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-03-22 07:27:12 +08:00
Code Issues Packages Projects Releases Wiki Activity

drm/amd: Pass adev to amdgpu_gfx_parse_disable_cu()

Browse Source 
In order for messages to be attribute to the correct device
amdgpu_gfx_parse_disable_cu() needs to know what device is being
operated on.  Pass the argument in.

Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mario Limonciello (AMD)
2025-12-14 19:12:22 -06:00
committed by Alex Deucher
parent e6c7ebeaba
commit 9edf6c09c5
11 changed files with 14 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
View File

@@ -100,6 +100,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
/**
* amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
*
* @adev: amdgpu device pointer
* @mask: array in which the per-shader array disable masks will be stored
* @max_se: number of SEs
* @max_sh: number of SHs
@@ -107,7 +108,8 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
* The bitmask of CUs to be disabled in the shader array determined by se and
* sh is stored in mask[se * max_sh + sh].
*/
void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh)
void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask,
unsigned int max_se, unsigned int max_sh)
{
unsigned int se, sh, cu;
const char *p;

4
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
View File

@@ -569,8 +569,8 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
return (u32)((1ULL << bit_width) - 1);
}
void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
unsigned max_sh);
void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask,
unsigned int max_se, unsigned int max_sh);
int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id);

2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@@ -10114,7 +10114,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
if (!adev || !cu_info)
return -EINVAL;
amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@@ -7482,7 +7482,7 @@ static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
if (!adev || !cu_info)
return -EINVAL;
amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

2
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
View File

@@ -5728,7 +5728,7 @@ static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
if (!adev || !cu_info)
return -EINVAL;
amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

2
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
View File

@@ -3933,7 +3933,7 @@ static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev,
return -EINVAL;
}
amdgpu_gfx_parse_disable_cu(disable_masks,
amdgpu_gfx_parse_disable_cu(adev, disable_masks,
adev->gfx.config.max_shader_engines,
adev->gfx.config.max_sh_per_se);

2
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View File

@@ -3555,7 +3555,7 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
memset(cu_info, 0, sizeof(*cu_info));
amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@@ -5063,7 +5063,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
memset(cu_info, 0, sizeof(*cu_info));
amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@@ -7084,7 +7084,7 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
else
ao_cu_num = adev->gfx.config.max_cu_per_sh;
amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2);
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@@ -7762,7 +7762,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
adev->gfx.config.max_sh_per_se > 16)
return -EINVAL;
amdgpu_gfx_parse_disable_cu(disable_masks,
amdgpu_gfx_parse_disable_cu(adev, disable_masks,
adev->gfx.config.max_shader_engines,
adev->gfx.config.max_sh_per_se);

2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
View File

@@ -4903,7 +4903,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
adev->gfx.config.max_sh_per_se > 16)
return -EINVAL;
amdgpu_gfx_parse_disable_cu(disable_masks,
amdgpu_gfx_parse_disable_cu(adev, disable_masks,
adev->gfx.config.max_shader_engines,
adev->gfx.config.max_sh_per_se);