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CRIS: Add more delays in DDR setup
Also, make DDR latency configurable. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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2d0503d1a6
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@ -33,6 +33,10 @@ config ETRAX_DDR2_CONFIG
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hex "DDR2 config"
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hex "DDR2 config"
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default "0"
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default "0"
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config ETRAX_DDR2_LATENCY
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hex "DDR2 latency"
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default "0"
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config ETRAX_PIO_CE0_CFG
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config ETRAX_PIO_CE0_CFG
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hex "PIO CE0 configuration"
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hex "PIO CE0 configuration"
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default "0"
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default "0"
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@ -24,11 +24,21 @@
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;; Refer to ddr2 MDS for initialization sequence
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;; Refer to ddr2 MDS for initialization sequence
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; 2. Wait 200us
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move.d 10000, $r2
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1: bne 1b
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subq 1, $r2
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; Start clock
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; Start clock
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
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move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
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move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
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move.d $r1, [$r0]
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move.d $r1, [$r0]
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; 2. Wait 200us
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move.d 10000, $r2
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1: bne 1b
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subq 1, $r2
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; Reset phy and start calibration
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; Reset phy and start calibration
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
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move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
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move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
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@ -52,6 +62,10 @@ do_cmd:
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lslq 16, $r1
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lslq 16, $r1
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or.d $r3, $r1
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or.d $r3, $r1
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move.d $r1, [$r0]
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move.d $r1, [$r0]
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; 2. Wait 200us
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move.d 10000, $r4
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1: bne 1b
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subq 1, $r4
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cmp.d sdram_commands_end, $r2
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cmp.d sdram_commands_end, $r2
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blo command_loop
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blo command_loop
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nop
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nop
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@ -63,7 +77,7 @@ do_cmd:
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; Set latency
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; Set latency
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
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move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
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move.d 0x13, $r1
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move.d CONFIG_ETRAX_DDR2_LATENCY, $r1
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move.d $r1, [$r0]
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move.d $r1, [$r0]
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; Set configuration
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; Set configuration
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@ -31,6 +31,8 @@
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; Register values
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; Register values
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.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
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.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
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.dword CONFIG_ETRAX_DDR2_CONFIG
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.dword CONFIG_ETRAX_DDR2_CONFIG
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.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency)
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.dword CONFIG_ETRAX_DDR2_LATENCY
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.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
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.dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
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.dword CONFIG_ETRAX_DDR2_TIMING
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.dword CONFIG_ETRAX_DDR2_TIMING
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.dword CONFIG_ETRAX_DDR2_MRS
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.dword CONFIG_ETRAX_DDR2_MRS
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