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mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2025-09-04 20:19:47 +08:00

spi: Fixes for v6.15

A fairly small pile of fixes, plus one new compatible string addition to
 the Synopsis driver for a new platform.  The most notable thing is the
 fix for divide by zeros in spi-mem if an operation has no dummy bytes.
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Merge tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
 "A fairly small pile of fixes, plus one new compatible string addition
  to the Synopsis driver for a new platform.

  The most notable thing is the fix for divide by zeros in spi-mem if an
  operation has no dummy bytes"

* tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: tegra114: Don't fail set_cs_timing when delays are zero
  spi: spi-qpic-snand: fix NAND_READ_LOCATION_2 register handling
  spi: spi-mem: Add fix to avoid divide error
  spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC
  spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry
  spi: spi-qpic-snand: propagate errors from qcom_spi_block_erase()
  spi: stm32-ospi: Fix an error handling path in stm32_ospi_probe()
This commit is contained in:
Linus Torvalds 2025-05-02 16:33:50 -07:00
commit 95d3481af6
5 changed files with 21 additions and 19 deletions

View File

@ -56,19 +56,18 @@ properties:
enum:
- snps,dw-apb-ssi
- snps,dwc-ssi-1.01a
- description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
items:
- enum:
- mscc,ocelot-spi
- mscc,jaguar2-spi
- const: snps,dw-apb-ssi
- description: Microchip Sparx5 SoC SPI Controller
const: microchip,sparx5-spi
- description: Amazon Alpine SPI Controller
const: amazon,alpine-dw-apb-ssi
- description: Renesas RZ/N1 SPI Controller
- description: Vendor controllers which use snps,dw-apb-ssi as fallback
items:
- const: renesas,rzn1-spi
- enum:
- mscc,ocelot-spi
- mscc,jaguar2-spi
- renesas,rzn1-spi
- sophgo,sg2042-spi
- thead,th1520-spi
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
@ -88,10 +87,6 @@ properties:
- renesas,r9a06g032-spi # RZ/N1D
- renesas,r9a06g033-spi # RZ/N1S
- const: renesas,rzn1-spi # RZ/N1
- description: T-HEAD TH1520 SoC SPI Controller
items:
- const: thead,th1520-spi
- const: snps,dw-apb-ssi
reg:
minItems: 1

View File

@ -596,7 +596,11 @@ u64 spi_mem_calc_op_duration(struct spi_mem_op *op)
ns_per_cycles = 1000000000 / op->max_freq;
ncycles += ((op->cmd.nbytes * 8) / op->cmd.buswidth) / (op->cmd.dtr ? 2 : 1);
ncycles += ((op->addr.nbytes * 8) / op->addr.buswidth) / (op->addr.dtr ? 2 : 1);
ncycles += ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dummy.dtr ? 2 : 1);
/* Dummy bytes are optional for some SPI flash memory operations */
if (op->dummy.nbytes)
ncycles += ((op->dummy.nbytes * 8) / op->dummy.buswidth) / (op->dummy.dtr ? 2 : 1);
ncycles += ((op->data.nbytes * 8) / op->data.buswidth) / (op->data.dtr ? 2 : 1);
return ncycles * ns_per_cycles;

View File

@ -142,7 +142,7 @@ static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
else if (reg == NAND_READ_LOCATION_1)
snandc->regs->read_location1 = locreg_val;
else if (reg == NAND_READ_LOCATION_2)
snandc->regs->read_location1 = locreg_val;
snandc->regs->read_location2 = locreg_val;
else if (reg == NAND_READ_LOCATION_3)
snandc->regs->read_location3 = locreg_val;
}
@ -1307,8 +1307,7 @@ static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
snandc->qspi->cmd = cpu_to_le32(cmd);
qcom_spi_block_erase(snandc);
return 0;
return qcom_spi_block_erase(snandc);
default:
break;
}

View File

@ -960,6 +960,10 @@ err_pm_resume:
err_pm_enable:
pm_runtime_force_suspend(ospi->dev);
mutex_destroy(&ospi->lock);
if (ospi->dma_chtx)
dma_release_channel(ospi->dma_chtx);
if (ospi->dma_chrx)
dma_release_channel(ospi->dma_chrx);
return ret;
}

View File

@ -728,9 +728,9 @@ static int tegra_spi_set_hw_cs_timing(struct spi_device *spi)
u32 inactive_cycles;
u8 cs_state;
if (setup->unit != SPI_DELAY_UNIT_SCK ||
hold->unit != SPI_DELAY_UNIT_SCK ||
inactive->unit != SPI_DELAY_UNIT_SCK) {
if ((setup->unit && setup->unit != SPI_DELAY_UNIT_SCK) ||
(hold->unit && hold->unit != SPI_DELAY_UNIT_SCK) ||
(inactive->unit && inactive->unit != SPI_DELAY_UNIT_SCK)) {
dev_err(&spi->dev,
"Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n",
SPI_DELAY_UNIT_SCK);