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drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

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Starting from Xe3p, there are two different copies of some of the GAM
registers:  the traditional MCR variant at their old locations, and a
new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
these registers directly, but we need to instruct the GuC on which set
it should use.  Since the new, unicast registers are preferred (since
they avoid the need for unnecessary MCR synchronization), set a new GuC
feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
new helper function, xe_guc_using_main_gamctrl_queues(), is added for
use in the 3 independent places that need to handle configuration of the
new reporting queues.

The mmio write to enable the main gamctl is only done during the general
GuC upload.  The gamctrl registers are not accessed by the GuC during
hwconfig load.

Last, the ADS blob for communicating the queue addresses contains both a
DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
when using the MAIN_GAMCTRL queues.

Bspec: 76445, 73540
Signed-off-by: Brian Welty <brian.welty@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251019-xe3p-gamctrl-v1-1-ad66d3c1908f@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Brian Welty
2025-10-19 19:05:46 -07:00
committed by Lucas De Marchi
parent d104d7ea86
commit 94edd65186
5 changed files with 37 additions and 1 deletions
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27
drivers/gpu/drm/xe/xe_guc.c
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@@ -91,6 +91,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev)))
flags |= GUC_CTL_ENABLE_PSMI_LOGGING;
if (xe_guc_using_main_gamctrl_queues(guc))
flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
return flags;
}
@@ -1255,8 +1258,13 @@ int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
int xe_guc_upload(struct xe_guc *guc)
{
struct xe_gt *gt = guc_to_gt(guc);
xe_guc_ads_populate(&guc->ads);
if (xe_guc_using_main_gamctrl_queues(guc))
xe_mmio_write32(&gt->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT);
return __xe_guc_upload(guc);
}
@@ -1657,6 +1665,25 @@ void xe_guc_declare_wedged(struct xe_guc *guc)
xe_guc_submit_wedge(guc);
}
/**
* xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use.
* @guc: The GuC object
*
* For Xe3p and beyond, we want to program the hardware to use the
* "Main GAMCTRL queue" rather than the legacy queue before we upload
* the GuC firmware. This will allow the GuC to use a new set of
* registers for pagefault handling and avoid some unnecessary
* complications with MCR register range handling.
*
* Return: true if can use new main gamctrl queues.
*/
bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc)
{
struct xe_gt *gt = guc_to_gt(guc);
return GT_VER(gt) >= 35;
}
#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
#include "tests/xe_guc_g2g_test.c"
#endif