torvalds/linux
3
0
Fork 0
mirror of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-03-22 07:27:12 +08:00
Code Issues Packages Projects Releases Wiki Activity

spi: geni-qcom: Check DMA interrupts early in ISR

Browse Source 
The current interrupt handler only checks the GENI main IRQ status
(m_irq) before deciding to return IRQ_NONE. This can lead to spurious
IRQ_NONE returns when DMA interrupts are pending but m_irq is zero.

Move the DMA TX/RX status register reads to the beginning of the ISR,
right after reading m_irq. Update the early return condition to check
all three status registers (m_irq, dma_tx_status, dma_rx_status) before
returning IRQ_NONE.

Signed-off-by: Praveen Talari <praveen.talari@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260313-spi-geni-qcom-fix-dma-irq-handling-v1-1-0bd122589e02@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Praveen Talari
2026-03-13 21:49:01 +05:30
committed by Mark Brown
parent dee0774bbb
commit 8c89a077ca
1 changed files with 5 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/spi/spi-geni-qcom.c
View File

@@ -906,10 +906,13 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
struct spi_controller *spi = data; struct spi_controller *spi = data;
struct spi_geni_master *mas = spi_controller_get_devdata(spi); struct spi_geni_master *mas = spi_controller_get_devdata(spi);
struct geni_se *se = &mas->se; struct geni_se *se = &mas->se;
u32 m_irq; u32 m_irq, dma_tx_status, dma_rx_status;
m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
if (!m_irq) dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
if (!m_irq && !dma_tx_status && !dma_rx_status)
return IRQ_NONE; return IRQ_NONE;
if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN | if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
@@ -957,8 +960,6 @@ static irqreturn_t geni_spi_isr(int irq, void *data)
} }
} else if (mas->cur_xfer_mode == GENI_SE_DMA) { } else if (mas->cur_xfer_mode == GENI_SE_DMA) {
const struct spi_transfer *xfer = mas->cur_xfer; const struct spi_transfer *xfer = mas->cur_xfer;
u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
if (dma_tx_status) if (dma_tx_status)
writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);