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phy-for-6.17

Browse Source 
- New Support
   - Qualcomm Milos Synopsys eUSB2 PHY, SM8750 QMP phy support,
     M31 eUSB2 PHY driver
   - Samsung Exynos990 usbdrd phy, Exynos7870 MIPI phy support
   - Renesas RZ/V2N usb2-phy support
 
 - Updates
   - Bulk Yaml binding conversion By Rob H (too many to be listed)
   - cadence: Sierra PCIe, USB PHY multilink configuration support
   - Qualcomm refactoring of UFS PHY reset and UFS driver support for phy
     calibrate API
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Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
 "New Support:

   - Qualcomm Milos Synopsys eUSB2 PHY, SM8750 QMP phy support, M31
     eUSB2 PHY driver

   - Samsung Exynos990 usbdrd phy, Exynos7870 MIPI phy support

   - Renesas RZ/V2N usb2-phy support

  Updates:

   - Bulk Yaml binding conversion By Rob H (too many to be listed)

   - cadence: Sierra PCIe, USB PHY multilink configuration support

   - Qualcomm refactoring of UFS PHY reset and UFS driver support for
     phy calibrate API"

* tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (74 commits)
  phy: qcom: phy-qcom-m31: Update IPQ5332 M31 USB phy initialization sequence
  dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
  dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
  dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
  dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
  phy: exynos-mipi-video: correct cam0 sysreg property name for exynos7870
  phy: qcom: phy-qcom-snps-eusb2: Update init sequence per HPG 1.0.2
  phy: qcom: phy-qcom-snps-eusb2: Add missing write from init sequence
  dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
  dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
  phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal
  phy: rockchip-pcie: Enable all four lanes if required
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
  phy: qcom: qmp-combo: Add missing PLL (VCO) configuration on SM8750
  phy: qcom: m31-eusb2: drop registration printk
  phy: qcom: m31-eusb2: fix match data santity check
  phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775P
  phy: qualcomm: phy-qcom-eusb2-repeater: Don't zero-out registers
  dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
  phy: mediatek: tphy: Cleanup and document slew calibration
  ...
This commit is contained in:
Linus Torvalds 2025-08-01 12:31:50 -07:00
commit 8582976acc
91 changed files with 3264 additions and 1128 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
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@ -19,7 +19,7 @@ which are described in the following files:
- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml
- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml
- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
- Documentation/devicetree/bindings/phy/motorola,cpcap-usb-phy.yaml
- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
- Documentation/devicetree/bindings/rtc/cpcap-rtc.txt
- Documentation/devicetree/bindings/leds/leds-cpcap.txt

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/apm,xgene-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene 15Gbps Multi-purpose PHY
maintainers:
- Khuong Dinh <khuong@os.amperecomputing.com>
description:
PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
PHY (pair of lanes) has its own node.
properties:
compatible:
items:
- const: apm,xgene-phy
reg:
maxItems: 1
'#phy-cells':
description:
Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
const: 1
clocks:
maxItems: 1
apm,tx-eye-tuning:
description:
Manual control to fine tune the capture of the serial bit lines from the
automatic calibrated position. Two set of 3-tuple setting for each
supported link speed on the host. Range from 0 to 127 in unit of one bit
period.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
minimum: 0
maximum: 127
default: 10
apm,tx-eye-direction:
description:
Eye tuning manual control direction. 0 means sample data earlier than the
nominal sampling point. 1 means sample data later than the nominal
sampling point. Two set of 3-tuple setting for each supported link speed
on the host.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
enum: [0, 1]
default: 0
apm,tx-boost-gain:
description:
Frequency boost AC (LSB 3-bit) and DC (2-bit) gain control. Two set of
3-tuple setting for each supported link speed on the host. Range is
between 0 to 31 in unit of dB. Default is 3.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
minimum: 0
maximum: 31
apm,tx-amplitude:
description:
Amplitude control. Two set of 3-tuple setting for each supported link
speed on the host. Range is between 0 to 199500 in unit of uV.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
minimum: 0
maximum: 199500
default: 199500
apm,tx-pre-cursor1:
description:
1st pre-cursor emphasis taps control. Two set of 3-tuple setting for
each supported link speed on the host. Range is 0 to 273000 in unit of
uV.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
minimum: 0
maximum: 273000
default: 0
apm,tx-pre-cursor2:
description:
2nd pre-cursor emphasis taps control. Two set of 3-tuple setting for
each supported link speed on the host. Range is 0 to 127400 in unit uV.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
minimum: 0
maximum: 127400
default: 0
apm,tx-post-cursor:
description: |
Post-cursor emphasis taps control. Two set of 3-tuple setting for Gen1,
Gen2, and Gen3 link speeds. Range is between 0 to 31 in unit of 18.2mV.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 2
maxItems: 2
items:
minItems: 3
maxItems: 3
items:
minimum: 0
maximum: 31
default: 0xf
apm,tx-speed:
description: >
Tx operating speed. One set of 3-tuple for each supported link speed on
the host:
0 = 1-2Gbps
1 = 2-4Gbps (1st tuple default)
2 = 4-8Gbps
3 = 8-15Gbps (2nd tuple default)
4 = 2.5-4Gbps
5 = 4-5Gbps
6 = 5-6Gbps
7 = 6-16Gbps (3rd tuple default).
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
maximum: 7
additionalProperties: false
examples:
- |
phy@1f21a000 {
compatible = "apm,xgene-phy";
reg = <0x1f21a000 0x100>;
#phy-cells = <1>;
};

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@ -1,76 +0,0 @@
* APM X-Gene 15Gbps Multi-purpose PHY nodes
PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
PHY (pair of lanes) has its own node.
Required properties:
- compatible : Shall be "apm,xgene-phy".
- reg : PHY memory resource is the SDS PHY access resource.
- #phy-cells : Shall be 1 as it expects one argument for setting
the mode of the PHY. Possible values are 0 (SATA),
1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
Optional properties:
- status : Shall be "ok" if enabled or "disabled" if disabled.
Default is "ok".
- clocks : Reference to the clock entry.
- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
bit lines from the automatic calibrated position.
Two set of 3-tuple setting for each (up to 3)
supported link speed on the host. Range from 0 to
127 in unit of one bit period. Default is 10.
- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
data earlier than the nominal sampling point. 1 means
sample data later than the nominal sampling point.
Two set of 3-tuple setting for each (up to 3)
supported link speed on the host. Default is 0.
- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
gain control. Two set of 3-tuple setting for each
(up to 3) supported link speed on the host. Range is
between 0 to 31 in unit of dB. Default is 3.
- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
each (up to 3) supported link speed on the host.
Range is between 0 to 199500 in unit of uV.
Default is 199500 uV.
- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
3-tuple setting for each (up to 3) supported link
speed on the host. Range is 0 to 273000 in unit of
uV. Default is 0.
- apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of
3-tuple setting for each (up to 3) supported link
speed on the host. Range is 0 to 127400 in unit uV.
Default is 0x0.
- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
3-tuple setting for Gen1, Gen2, and Gen3. Range is
between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
- apm,tx-speed : Tx operating speed. One set of 3-tuple for each
supported link speed on the host.
0 = 1-2Gbps
1 = 2-4Gbps (1st tuple default)
2 = 4-8Gbps
3 = 8-15Gbps (2nd tuple default)
4 = 2.5-4Gbps
5 = 4-5Gbps
6 = 5-6Gbps
7 = 6-16Gbps (3rd tuple default)
NOTE: PHY override parameters are board specific setting.
Example:
phy1: phy@1f21a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f21a000 0x0 0x100>;
#phy-cells = <1>;
};
phy2: phy@1f22a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
};
phy3: phy@1f23a000 {
compatible = "apm,xgene-phy";
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
};

36
Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
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@ -1,36 +0,0 @@
Berlin SATA PHY
---------------
Required properties:
- compatible: should be one of
"marvell,berlin2-sata-phy"
"marvell,berlin2q-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- phy-cells: from the generic PHY bindings, must be 1
- reg: address and length of the register
- clocks: reference to the clock entry
Sub-nodes:
Each PHY should be represented as a sub-node.
Sub-nodes required properties:
- reg: the PHY number
Example:
sata_phy: phy@f7e900a0 {
compatible = "marvell,berlin2q-sata-phy";
reg = <0xf7e900a0 0x200>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
sata-phy@0 {
reg = <0>;
};
sata-phy@1 {
reg = <1>;
};
};

16
Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
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@ -1,16 +0,0 @@
* Marvell Berlin USB PHY
Required properties:
- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
- reg: base address and length of the registers
- #phys-cells: should be 0
- resets: reference to the reset controller
Example:
usb-phy@f774000 {
compatible = "marvell,berlin2-usb-phy";
reg = <0xf774000 0x128>;
#phy-cells = <0>;
resets = <&chip 0x104 14>;
};

30
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.txt
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@ -1,30 +0,0 @@
BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
Required properties:
- compatible: brcm,ns2-drd-phy
- reg: offset and length of the NS2 PHY related registers.
- reg-names
The below registers must be provided.
icfg - for DRD ICFG configurations
rst-ctrl - for DRD IDM reset
crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
usb2-strap - for port over current polarity reversal
- #phy-cells: Must be 0. No args required.
- vbus-gpios: vbus gpio binding
- id-gpios: id gpio binding
Refer to phy/phy-bindings.txt for the generic PHY binding properties
Example:
usbdrd_phy: phy@66000960 {
#phy-cells = <0>;
compatible = "brcm,ns2-drd-phy";
reg = <0x66000960 0x24>,
<0x67012800 0x4>,
<0x6501d148 0x4>,
<0x664d0700 0x4>;
reg-names = "icfg", "rst-ctrl",
"crmu-ctrl", "usb2-strap";
id-gpios = <&gpio_g 30 0>;
vbus-gpios = <&gpio_g 31 0>;
};

62
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.yaml Normal file
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@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar2 USB2 Dual Role Device PHY
maintainers:
- Florian Fainelli <florian.fainelli@broadcom.com>
- Hauke Mehrtens <hauke@hauke-m.de>
- Rafał Miłecki <zajec5@gmail.com>
properties:
compatible:
const: brcm,ns2-drd-phy
reg:
items:
- description: DRD ICFG configurations
- description: DRD IDM reset
- description: CRMU core vdd, PHY and PHY PLL reset
- description: Port over current polarity reversal
reg-names:
items:
- const: icfg
- const: rst-ctrl
- const: crmu-ctrl
- const: usb2-strap
'#phy-cells':
const: 0
id-gpios:
maxItems: 1
description: ID GPIO line
vbus-gpios:
maxItems: 1
description: VBUS GPIO line
required:
- '#phy-cells'
- compatible
- reg
- reg-names
- id-gpios
- vbus-gpios
additionalProperties: false
examples:
- |
phy@66000960 {
#phy-cells = <0>;
compatible = "brcm,ns2-drd-phy";
reg = <0x66000960 0x24>, <0x67012800 0x4>, <0x6501d148 0x4>, <0x664d0700 0x4>;
reg-names = "icfg", "rst-ctrl", "crmu-ctrl", "usb2-strap";
id-gpios = <&gpio_g 30 0>;
vbus-gpios = <&gpio_g 31 0>;
};

41
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.txt
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@ -1,41 +0,0 @@
Broadcom Stingray PCIe PHY
Required properties:
- compatible: must be "brcm,sr-pcie-phy"
- reg: base address and length of the PCIe SS register space
- brcm,sr-cdru: phandle to the CDRU syscon node
- brcm,sr-mhb: phandle to the MHB syscon node
- #phy-cells: Must be 1, denotes the PHY index
For PAXB based root complex, one can have a configuration of up to 8 PHYs
PHY index goes from 0 to 7
For the internal PAXC based root complex, PHY index is always 8
Example:
mhb: syscon@60401000 {
compatible = "brcm,sr-mhb", "syscon";
reg = <0 0x60401000 0 0x38c>;
};
cdru: syscon@6641d000 {
compatible = "brcm,sr-cdru", "syscon";
reg = <0 0x6641d000 0 0x400>;
};
pcie_phy: phy@40000000 {
compatible = "brcm,sr-pcie-phy";
reg = <0 0x40000000 0 0x800>;
brcm,sr-cdru = <&cdru>;
brcm,sr-mhb = <&mhb>;
#phy-cells = <1>;
};
/* users of the PCIe PHY */
pcie0: pcie@48000000 {
...
...
phys = <&pcie_phy 0>;
phy-names = "pcie-phy";
};

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Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/brcm,sr-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Stingray PCIe PHY
maintainers:
- Ray Jui <ray.jui@broadcom.com>
description: >
For PAXB based root complex, one can have a configuration of up to 8 PHYs.
PHY index goes from 0 to 7.
For the internal PAXC based root complex, PHY index is always 8.
properties:
compatible:
const: brcm,sr-pcie-phy
reg:
maxItems: 1
'#phy-cells':
const: 1
brcm,sr-cdru:
description: phandle to the CDRU syscon node
$ref: /schemas/types.yaml#/definitions/phandle
brcm,sr-mhb:
description: phandle to the MHB syscon node
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: false
examples:
- |
phy@40000000 {
compatible = "brcm,sr-pcie-phy";
reg = <0x40000000 0x800>;
brcm,sr-cdru = <&cdru>;
brcm,sr-mhb = <&mhb>;
#phy-cells = <1>;
};

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Documentation/devicetree/bindings/phy/brcm,sr-usb-combo-phy.yaml Normal file
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@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/brcm,sr-usb-combo-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Stingray USB PHY
maintainers:
- Ray Jui <rjui@broadcom.com>
- Scott Branden <sbranden@broadcom.com>
properties:
compatible:
enum:
- brcm,sr-usb-combo-phy
- brcm,sr-usb-hs-phy
reg:
maxItems: 1
'#phy-cells':
description: PHY cell count indicating PHY type
enum: [ 0, 1 ]
required:
- compatible
- reg
- '#phy-cells'
allOf:
- if:
properties:
compatible:
contains:
const: brcm,sr-usb-combo-phy
then:
properties:
'#phy-cells':
const: 1
- if:
properties:
compatible:
contains:
const: brcm,sr-usb-hs-phy
then:
properties:
'#phy-cells':
const: 0
additionalProperties: false
examples:
- |
usb-phy@0 {
compatible = "brcm,sr-usb-combo-phy";
reg = <0x00000000 0x100>;
#phy-cells = <1>;
};
- |
usb-phy@20000 {
compatible = "brcm,sr-usb-hs-phy";
reg = <0x00020000 0x100>;
#phy-cells = <0>;
};

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Documentation/devicetree/bindings/phy/brcm,stingray-usb-phy.txt
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@ -1,32 +0,0 @@
Broadcom Stingray USB PHY
Required properties:
- compatible : should be one of the listed compatibles
- "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
- "brcm,sr-usb-hs-phy" is a single HS PHY.
- reg: offset and length of the PHY blocks registers
- #phy-cells:
- Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
- Must be 0 for brcm,sr-usb-hs-phy.
Refer to phy/phy-bindings.txt for the generic PHY binding properties
Example:
usbphy0: usb-phy@0 {
compatible = "brcm,sr-usb-combo-phy";
reg = <0x00000000 0x100>;
#phy-cells = <1>;
};
usbphy1: usb-phy@10000 {
compatible = "brcm,sr-usb-combo-phy";
reg = <0x00010000 0x100>,
#phy-cells = <1>;
};
usbphy2: usb-phy@20000 {
compatible = "brcm,sr-usb-hs-phy";
reg = <0x00020000 0x100>,
#phy-cells = <0>;
};

24
Documentation/devicetree/bindings/phy/dm816x-phy.txt
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@ -1,24 +0,0 @@
Device tree binding documentation for am816x USB PHY
=========================
Required properties:
- compatible : should be "ti,dm816x-usb-phy"
- reg : offset and length of the PHY register set.
- reg-names : name for the phy registers
- clocks : phandle to the clock
- clock-names : name of the clock
- syscon: phandle for the syscon node to access misc registers
- #phy-cells : from the generic PHY bindings, must be 1
- syscon: phandle for the syscon node to access misc registers
Example:
usb_phy0: usb-phy@20 {
compatible = "ti,dm8168-usb-phy";
reg = <0x20 0x8>;
reg-names = "phy";
clocks = <&main_fapll 6>;
clock-names = "refclk";
#phy-cells = <0>;
syscon = <&scm_conf>;
};

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Documentation/devicetree/bindings/phy/hisilicon,hi6220-usb-phy.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/hisilicon,hi6220-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon hi6220 USB PHY
maintainers:
- Zhangfei Gao <zhangfei.gao@linaro.org>
properties:
compatible:
const: hisilicon,hi6220-usb-phy
'#phy-cells':
const: 0
phy-supply:
description: PHY power supply.
hisilicon,peripheral-syscon:
description: Phandle to the system controller for PHY control.
$ref: /schemas/types.yaml#/definitions/phandle
additionalProperties: false
examples:
- |
usbphy {
compatible = "hisilicon,hi6220-usb-phy";
#phy-cells = <0>;
phy-supply = <&fixed_5v_hub>;
hisilicon,peripheral-syscon = <&sys_ctrl>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/hisilicon,hix5hd2-sata-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon hix5hd2 SATA PHY
maintainers:
- Jiancheng Xue <xuejiancheng@huawei.com>
properties:
compatible:
const: hisilicon,hix5hd2-sata-phy
reg:
maxItems: 1
'#phy-cells':
const: 0
hisilicon,peripheral-syscon:
description: Phandle of syscon used to control peripheral
$ref: /schemas/types.yaml#/definitions/phandle
hisilicon,power-reg:
description: Offset and bit number within peripheral-syscon register controlling SATA power supply
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: Offset within peripheral-syscon register
- description: Bit number controlling SATA power supply
required:
- compatible
- reg
- '#phy-cells'
additionalProperties: false
examples:
- |
phy@f9900000 {
compatible = "hisilicon,hix5hd2-sata-phy";
reg = <0xf9900000 0x10000>;
#phy-cells = <0>;
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
hisilicon,power-reg = <0x8 10>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/hisilicon,inno-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon INNO USB2 PHY
maintainers:
- Pengcheng Li <lpc.li@hisilicon.com>
description:
The INNO USB2 PHY device should be a child node of peripheral controller that
contains the PHY configuration register, and each device supports up to 2 PHY
ports which are represented as child nodes of INNO USB2 PHY device.
properties:
compatible:
enum:
- hisilicon,hi3798cv200-usb2-phy
- hisilicon,hi3798mv100-usb2-phy
- hisilicon,inno-usb2-phy
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^phy@[0-1]$":
description: PHY port subnode
type: object
additionalProperties: false
properties:
reg:
maximum: 1
"#phy-cells":
const: 0
resets:
maxItems: 1
required:
- reg
- "#phy-cells"
- resets
required:
- compatible
- reg
- clocks
- resets
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/histb-clock.h>
usb2-phy@120 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x120 0x4>;
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
resets = <&crg 0xbc 4>;
#address-cells = <1>;
#size-cells = <0>;
phy@0 {
reg = <0>;
#phy-cells = <0>;
resets = <&crg 0xbc 8>;
};
phy@1 {
reg = <1>;
#phy-cells = <0>;
resets = <&crg 0xbc 9>;
};
};

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Hisilicon hix5hd2 SATA PHY
-----------------------
Required properties:
- compatible: should be "hisilicon,hix5hd2-sata-phy"
- reg: offset and length of the PHY registers
- #phy-cells: must be 0
Refer to phy/phy-bindings.txt for the generic PHY binding properties
Optional Properties:
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
- hisilicon,power-reg: offset and bit number within peripheral-syscon,
register of controlling sata power supply.
Example:
sata_phy: phy@f9900000 {
compatible = "hisilicon,hix5hd2-sata-phy";
reg = <0xf9900000 0x10000>;
#phy-cells = <0>;
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
hisilicon,power-reg = <0x8 10>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/img,pistachio-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Pistachio USB PHY
maintainers:
- Andrew Bresticker <abrestic@chromium.org>
properties:
compatible:
const: img,pistachio-usb-phy
clocks:
maxItems: 1
clock-names:
items:
- const: usb_phy
'#phy-cells':
const: 0
phy-supply:
description: USB VBUS supply. Must supply 5.0V.
img,refclk:
description:
Reference clock source for the USB PHY. See
<dt-bindings/phy/phy-pistachio-usb.h> for valid values.
$ref: /schemas/types.yaml#/definitions/uint32
img,cr-top:
description: CR_TOP syscon phandle.
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- clocks
- clock-names
- '#phy-cells'
- img,refclk
- img,cr-top
additionalProperties: false
examples:
- |
#include <dt-bindings/phy/phy-pistachio-usb.h>
#include <dt-bindings/clock/pistachio-clk.h>
usb-phy {
compatible = "img,pistachio-usb-phy";
clocks = <&clk_core CLK_USB_PHY>;
clock-names = "usb_phy";
#phy-cells = <0>;
phy-supply = <&usb_vbus>;
img,refclk = <REFCLK_CLK_CORE>;
img,cr-top = <&cr_top>;
};

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TI Keystone USB PHY
Required properties:
- compatible: should be "ti,keystone-usbphy".
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property.
- reg : Address and length of the usb phy control register set.
The main purpose of this PHY driver is to enable the USB PHY reference clock
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
phy node in the USB Glue layer driver node.
usb_phy: usb_phy@2620738 {
compatible = "ti,keystone-usbphy";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2620738 32>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/lantiq,ase-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lantiq XWAY SoC RCU USB 1.1/2.0 PHY
maintainers:
- Hauke Mehrtens <hauke@hauke-m.de>
description:
This node has to be a sub node of the Lantiq RCU block.
properties:
compatible:
items:
- enum:
- lantiq,ase-usb2-phy
- lantiq,danube-usb2-phy
- lantiq,xrx100-usb2-phy
- lantiq,xrx200-usb2-phy
- lantiq,xrx300-usb2-phy
reg:
items:
- description: Offset of the USB PHY configuration register
- description: Offset of the USB Analog configuration register
clocks:
maxItems: 1
clock-names:
items:
- const: phy
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
items:
- enum: [ phy, ctrl ]
- const: ctrl
'#phy-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- '#phy-cells'
additionalProperties: false
examples:
- |
usb2-phy@18 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x18 4>, <0x38 4>;
clocks = <&pmu 1>;
clock-names = "phy";
resets = <&reset1 4 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
#phy-cells = <0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,armada-375-usb-cluster.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Armada 375 USB Cluster
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description:
Control register for the Armada 375 USB cluster, managing USB2 and USB3 features.
properties:
compatible:
const: marvell,armada-375-usb-cluster
reg:
maxItems: 1
'#phy-cells':
description: Number of PHY cells in specifier. 1 for USB2, 2 for USB3.
const: 1
required:
- compatible
- reg
- '#phy-cells'
additionalProperties: false
examples:
- |
usbcluster: usb-cluster@18400 {
compatible = "marvell,armada-375-usb-cluster";
reg = <0x18400 0x4>;
#phy-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,armada-380-comphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 38x COMPHY controller
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description:
This comphy controller can be found on Marvell Armada 38x. It provides a
number of shared PHYs used by various interfaces (network, sata, usb,
PCIe...).
properties:
compatible:
items:
- const: marvell,armada-380-comphy
reg:
items:
- description: COMPHY register location and length
- description: Configuration register location and length
reg-names:
items:
- const: comphy
- const: conf
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
'^phy@[0-5]$':
description: A COMPHY lane
type: object
additionalProperties: false
properties:
reg:
maximum: 1
'#phy-cells':
description: Input port index for the PHY lane
const: 1
required:
- reg
- '#phy-cells'
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
comphy: phy@18300 {
compatible = "marvell,armada-380-comphy";
reg = <0x18300 0x100>, <0x18460 4>;
reg-names = "comphy", "conf";
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,berlin2-sata-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin SATA PHY
maintainers:
- Antoine Tenart <atenart@kernel.org>
properties:
compatible:
enum:
- marvell,berlin2-sata-phy
- marvell,berlin2q-sata-phy
reg:
maxItems: 1
clocks:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
'#phy-cells':
const: 1
patternProperties:
'^sata-phy@[0-1]$':
description: A SATA PHY sub-node.
type: object
additionalProperties: false
properties:
reg:
maximum: 1
description: PHY index number.
required:
- reg
required:
- compatible
- reg
- clocks
- '#address-cells'
- '#size-cells'
- '#phy-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/berlin2q.h>
phy@f7e900a0 {
compatible = "marvell,berlin2q-sata-phy";
reg = <0xf7e900a0 0x200>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
sata-phy@0 {
reg = <0>;
};
sata-phy@1 {
reg = <1>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,berlin2-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin USB PHY
maintainers:
- Antoine Tenart <atenart@kernel.org>
properties:
compatible:
enum:
- marvell,berlin2-usb-phy
- marvell,berlin2cd-usb-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
resets:
maxItems: 1
required:
- compatible
- reg
- "#phy-cells"
- resets
additionalProperties: false
examples:
- |
usb-phy@f774000 {
compatible = "marvell,berlin2-usb-phy";
reg = <0xf774000 0x128>;
#phy-cells = <0>;
resets = <&chip 0x104 14>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU COMPHY Controller
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
description: >
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 7k/8k (on the CP110)
* Armada 3700
It provides a number of shared PHYs used by various interfaces (network, SATA,
USB, PCIe...).
properties:
compatible:
enum:
- marvell,comphy-cp110
- marvell,comphy-a3700
reg:
minItems: 1
items:
- description: Generic COMPHY registers
- description: Lane 1 (PCIe/GbE) registers (Armada 3700)
- description: Lane 0 (USB3/GbE) registers (Armada 3700)
- description: Lane 2 (SATA/USB3) registers (Armada 3700)
reg-names:
minItems: 1
items:
- const: comphy
- const: lane1_pcie_gbe
- const: lane0_usb3_gbe
- const: lane2_sata_usb3
'#address-cells':
const: 1
'#size-cells':
const: 0
clocks:
maxItems: 3
description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
clock-names:
items:
- const: mg_clk
- const: mg_core_clk
- const: axi_clk
marvell,system-controller:
description: Phandle to the Marvell system controller (CP110 only)
$ref: /schemas/types.yaml#/definitions/phandle
patternProperties:
'^phy@[0-2]$':
description: A COMPHY lane child node
type: object
additionalProperties: false
properties:
reg:
description: COMPHY lane number
'#phy-cells':
const: 1
required:
- reg
- '#phy-cells'
required:
- compatible
- reg
additionalProperties: false
allOf:
- if:
properties:
compatible:
const: marvell,comphy-a3700
then:
properties:
clocks: false
clock-names: false
required:
- reg-names
else:
required:
- marvell,system-controller
examples:
- |
phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
marvell,system-controller = <&syscon0>;
phy@0 {
reg = <0>;
#phy-cells = <1>;
};
phy@1 {
reg = <1>;
#phy-cells = <1>;
};
};
- |
phy@18300 {
compatible = "marvell,comphy-a3700";
reg = <0x18300 0x300>,
<0x1F000 0x400>,
<0x5C000 0x400>,
<0xe0178 0x8>;
reg-names = "comphy",
"lane1_pcie_gbe",
"lane0_usb3_gbe",
"lane2_sata_usb3";
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,mmp2-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MMP2/PXA USB PHY
maintainers:
- Lubomir Rintel <lkundrak@v3.sk>
properties:
compatible:
enum:
- marvell,mmp2-usb-phy
- marvell,pxa910-usb-phy
- marvell,pxa168-usb-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
required:
- compatible
- "#phy-cells"
additionalProperties: false
examples:
- |
usbphy@d4207000 {
compatible = "marvell,mmp2-usb-phy";
reg = <0xd4207000 0x40>;
#phy-cells = <0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/marvell,mvebu-sata-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU SATA PHY
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
const: marvell,mvebu-sata-phy
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: sata
'#phy-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- '#phy-cells'
additionalProperties: false
examples:
- |
sata-phy@84000 {
compatible = "marvell,mvebu-sata-phy";
reg = <0x84000 0x0334>;
clocks = <&gate_clk 15>;
clock-names = "sata";
#phy-cells = <0>;
};

5
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@ -72,11 +72,6 @@ allOf:
contains:
const: fsl,imx8qxp-mipi-dphy
then:
properties:
assigned-clocks: false
assigned-clock-parents: false
assigned-clock-rates: false
required:
- fsl,syscon

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/motorola,cpcap-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Motorola CPCAP PMIC USB PHY
maintainers:
- Tony Lindgren <tony@atomide.com>
properties:
compatible:
enum:
- motorola,cpcap-usb-phy
- motorola,mapphone-cpcap-usb-phy
'#phy-cells':
const: 0
interrupts:
description: CPCAP PMIC interrupts used by the USB PHY
items:
- description: id_ground interrupt
- description: id_float interrupt
- description: se0conn interrupt
- description: vbusvld interrupt
- description: sessvld interrupt
- description: sessend interrupt
- description: se1 interrupt
- description: dm interrupt
- description: dp interrupt
interrupt-names:
description: Interrupt names
items:
- const: id_ground
- const: id_float
- const: se0conn
- const: vbusvld
- const: sessvld
- const: sessend
- const: se1
- const: dm
- const: dp
io-channels:
description: IIO ADC channels used by the USB PHY
items:
- description: vbus channel
- description: id channel
io-channel-names:
items:
- const: vbus
- const: id
vusb-supply: true
pinctrl-names:
items:
- const: default
- const: ulpi
- const: utmi
- const: uart
mode-gpios:
description: Optional GPIOs for configuring alternate modes
items:
- description: "mode selection GPIO #0"
- description: "mode selection GPIO #1"
required:
- compatible
- '#phy-cells'
- interrupts-extended
- interrupt-names
- io-channels
- io-channel-names
- vusb-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
phy {
compatible = "motorola,mapphone-cpcap-usb-phy";
#phy-cells = <0>;
interrupts-extended = <
&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
&cpcap 48 1
>;
interrupt-names = "id_ground", "id_float", "se0conn", "vbusvld",
"sessvld", "sessend", "se1", "dm", "dp";
io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
io-channel-names = "vbus", "id";
vusb-supply = <&vusb>;
pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
pinctrl-1 = <&usb_ulpi_pins>;
pinctrl-2 = <&usb_utmi_pins>;
pinctrl-3 = <&uart3_pins>;
pinctrl-names = "default", "ulpi", "utmi", "uart";
mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, <&gpio1 0 GPIO_ACTIVE_HIGH>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/motorola,mapphone-mdm6600.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Motorola Mapphone MDM6600 USB PHY
maintainers:
- Tony Lindgren <tony@atomide.com>
properties:
compatible:
items:
- const: motorola,mapphone-mdm6600
enable-gpios:
description: GPIO to enable the USB PHY
maxItems: 1
power-gpios:
description: GPIO to power on the device
maxItems: 1
reset-gpios:
description: GPIO to reset the device
maxItems: 1
motorola,mode-gpios:
description: Two GPIOs to configure MDM6600 USB start-up mode for normal mode versus USB flashing mode
items:
- description: normal mode select GPIO
- description: USB flashing mode select GPIO
motorola,cmd-gpios:
description: Three GPIOs to control the power state of the MDM6600
items:
- description: power state control GPIO 0
- description: power state control GPIO 1
- description: power state control GPIO 2
motorola,status-gpios:
description: Three GPIOs to read the power state of the MDM6600
items:
- description: power state read GPIO 0
- description: power state read GPIO 1
- description: power state read GPIO 2
'#phy-cells':
const: 0
required:
- compatible
- enable-gpios
- power-gpios
- reset-gpios
- motorola,mode-gpios
- motorola,cmd-gpios
- motorola,status-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
usb-phy {
compatible = "motorola,mapphone-mdm6600";
enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
<&gpio5 21 GPIO_ACTIVE_HIGH>;
motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
<&gpio4 8 GPIO_ACTIVE_HIGH>,
<&gpio5 14 GPIO_ACTIVE_HIGH>;
motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
<&gpio2 21 GPIO_ACTIVE_HIGH>,
<&gpio2 23 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};

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mvebu armada 38x comphy driver
------------------------------
This comphy controller can be found on Marvell Armada 38x. It provides a
number of shared PHYs used by various interfaces (network, sata, usb,
PCIe...).
Required properties:
- compatible: should be "marvell,armada-380-comphy"
- reg: should contain the comphy register location and length.
- #address-cells: should be 1.
- #size-cells: should be 0.
Optional properties:
- reg-names: must be "comphy" as the first name, and "conf".
- reg: must contain the comphy register location and length as the first
pair, followed by an optional configuration register address and
length pair.
A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
- reg: comphy lane number.
- #phy-cells : from the generic phy bindings, must be 1. Defines the
input port to use for a given comphy lane.
Example:
comphy: phy@18300 {
compatible = "marvell,armada-380-comphy";
reg-names = "comphy", "conf";
reg = <0x18300 0x100>, <0x18460 4>;
#address-cells = <1>;
#size-cells = <0>;
cpm_comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
cpm_comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
};

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* Atheros AR71XX/9XXX USB PHY
Required properties:
- compatible: "qca,ar7100-usb-phy"
- #phys-cells: should be 0
- reset-names: "phy"[, "suspend-override"]
- resets: references to the reset controllers
Example:
usb-phy {
compatible = "qca,ar7100-usb-phy";
reset-names = "phy", "suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;
};

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Motorola CPCAP PMIC USB PHY binding
Required properties:
compatible: Shall be either "motorola,cpcap-usb-phy" or
"motorola,mapphone-cpcap-usb-phy"
#phy-cells: Shall be 0
interrupts: CPCAP PMIC interrupts used by the USB PHY
interrupt-names: Interrupt names
io-channels: IIO ADC channels used by the USB PHY
io-channel-names: IIO ADC channel names
vusb-supply: Regulator for the PHY
Optional properties:
pinctrl: Optional alternate pin modes for the PHY
pinctrl-names: Names for optional pin modes
mode-gpios: Optional GPIOs for configuring alternate modes
Example:
cpcap_usb2_phy: phy {
compatible = "motorola,mapphone-cpcap-usb-phy";
pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
pinctrl-1 = <&usb_ulpi_pins>;
pinctrl-2 = <&usb_utmi_pins>;
pinctrl-3 = <&uart3_pins>;
pinctrl-names = "default", "ulpi", "utmi", "uart";
#phy-cells = <0>;
interrupts-extended = <
&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
&cpcap 48 1
>;
interrupt-names =
"id_ground", "id_float", "se0conn", "vbusvld",
"sessvld", "sessend", "se1", "dm", "dp";
mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH
&gpio1 0 GPIO_ACTIVE_HIGH>;
io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
io-channel-names = "vbus", "id";
vusb-supply = <&vusb>;
};

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TI DA8xx/OMAP-L1xx/AM18xx USB PHY
Required properties:
- compatible: must be "ti,da830-usb-phy".
- #phy-cells: must be 1.
This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
controllers on DA8xx SoCs. Consumers of this device should use index 0 for
the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
to access the CFGCHIP2 register.
Example:
cfgchip: cfgchip@1417c {
compatible = "ti,da830-cfgchip", "syscon";
reg = <0x1417c 0x14>;
};
usb_phy: usb-phy {
compatible = "ti,da830-usb-phy";
#phy-cells = <1>;
};
usb20: usb@200000 {
compatible = "ti,da830-musb";
reg = <0x200000 0x1000>;
interrupts = <58>;
phys = <&usb_phy 0>;
phy-names = "usb-phy";
};
usb11: usb@225000 {
compatible = "ti,da830-ohci";
reg = <0x225000 0x1000>;
interrupts = <59>;
phys = <&usb_phy 1>;
phy-names = "usb-phy";
};

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Hisilicon hi6220 usb PHY
-----------------------
Required properties:
- compatible: should be "hisilicon,hi6220-usb-phy"
- #phy-cells: must be 0
- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
Refer to phy/phy-bindings.txt for the generic PHY binding properties
Example:
usb_phy: usbphy {
compatible = "hisilicon,hi6220-usb-phy";
#phy-cells = <0>;
phy-supply = <&fixed_5v_hub>;
hisilicon,peripheral-syscon = <&sys_ctrl>;
};

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Device tree bindings for HiSilicon INNO USB2 PHY
Required properties:
- compatible: Should be one of the following strings:
"hisilicon,inno-usb2-phy",
"hisilicon,hi3798cv200-usb2-phy".
- reg: Should be the address space for PHY configuration register in peripheral
controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
reference clock.
- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
signal.
- #address-cells: Must be 1.
- #size-cells: Must be 0.
The INNO USB2 PHY device should be a child node of peripheral controller that
contains the PHY configuration register, and each device supports up to 2 PHY
ports which are represented as child nodes of INNO USB2 PHY device.
Required properties for PHY port node:
- reg: The PHY port instance number.
- #phy-cells: Defined by generic PHY bindings. Must be 0.
- resets: The phandle and reset specifier pair for PHY port reset signal.
Refer to phy/phy-bindings.txt for the generic PHY binding properties
Example:
perictrl: peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
usb2_phy1: usb2-phy@120 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x120 0x4>;
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
resets = <&crg 0xbc 4>;
#address-cells = <1>;
#size-cells = <0>;
usb2_phy1_port0: phy@0 {
reg = <0>;
#phy-cells = <0>;
resets = <&crg 0xbc 8>;
};
usb2_phy1_port1: phy@1 {
reg = <1>;
#phy-cells = <0>;
resets = <&crg 0xbc 9>;
};
};
usb2_phy2: usb2-phy@124 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x124 0x4>;
clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
resets = <&crg 0xbc 6>;
#address-cells = <1>;
#size-cells = <0>;
usb2_phy2_port0: phy@0 {
reg = <0>;
#phy-cells = <0>;
resets = <&crg 0xbc 10>;
};
};
};

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Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
===========================================
This binding describes the USB PHY hardware provided by the RCU module on the
Lantiq XWAY SoCs.
This node has to be a sub node of the Lantiq RCU block.
-------------------------------------------------------------------------------
Required properties (controller (parent) node):
- compatible : Should be one of
"lantiq,ase-usb2-phy"
"lantiq,danube-usb2-phy"
"lantiq,xrx100-usb2-phy"
"lantiq,xrx200-usb2-phy"
"lantiq,xrx300-usb2-phy"
- reg : Defines the following sets of registers in the parent
syscon device
- Offset of the USB PHY configuration register
- Offset of the USB Analog configuration
register (only for xrx200 and xrx200)
- clocks : References to the (PMU) "phy" clk gate.
- clock-names : Must be "phy"
- resets : References to the RCU USB configuration reset bits.
- reset-names : Must be one of the following:
"phy" (optional)
"ctrl" (shared)
-------------------------------------------------------------------------------
Example for the USB PHYs on an xRX200 SoC:
usb_phy0: usb2-phy@18 {
compatible = "lantiq,xrx200-usb2-phy";
reg = <0x18 4>, <0x38 4>;
clocks = <&pmu PMU_GATE_USB0_PHY>;
clock-names = "phy";
resets = <&reset1 4 4>, <&reset0 4 4>;
reset-names = "phy", "ctrl";
#phy-cells = <0>;
};

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Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY
Required properties:
- compatible Must be "motorola,mapphone-mdm6600"
- enable-gpios GPIO to enable the USB PHY
- power-gpios GPIO to power on the device
- reset-gpios GPIO to reset the device
- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for
normal mode versus USB flashing mode
- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600
- motorola,status-gpios Three GPIOs to read the power state of the MDM6600
Example:
usb-phy {
compatible = "motorola,mapphone-mdm6600";
enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
<&gpio5 21 GPIO_ACTIVE_HIGH>;
motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
<&gpio4 8 GPIO_ACTIVE_HIGH>,
<&gpio5 14 GPIO_ACTIVE_HIGH>;
motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
<&gpio2 21 GPIO_ACTIVE_HIGH>,
<&gpio2 23 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};

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MVEBU comphy drivers
--------------------
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 7k/8k (on the CP110)
* Armada 3700
It provides a number of shared PHYs used by various interfaces (network, SATA,
USB, PCIe...).
Required properties:
- compatible: should be one of:
* "marvell,comphy-cp110" for Armada 7k/8k
* "marvell,comphy-a3700" for Armada 3700
- reg: should contain the COMPHY register(s) location(s) and length(s).
* 1 entry for Armada 7k/8k
* 4 entries for Armada 3700 along with the corresponding reg-names
properties, memory areas are:
* Generic COMPHY registers
* Lane 1 (PCIe/GbE)
* Lane 0 (USB3/GbE)
* Lane 2 (SATA/USB3)
- marvell,system-controller: should contain a phandle to the system
controller node (only for Armada 7k/8k)
- #address-cells: should be 1.
- #size-cells: should be 0.
Optional properlties:
- clocks: pointers to the reference clocks for this device (CP110 only),
consequently: MG clock, MG Core clock, AXI clock.
- clock-names: names of used clocks for CP110 only, must be :
"mg_clk", "mg_core_clk" and "axi_clk".
A sub-node is required for each comphy lane provided by the comphy.
Required properties (child nodes):
- reg: COMPHY lane number.
- #phy-cells : from the generic PHY bindings, must be 1. Defines the
input port to use for a given comphy lane.
Examples:
CP11X_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
<&CP11X_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
};
comphy: phy@18300 {
compatible = "marvell,comphy-a3700";
reg = <0x18300 0x300>,
<0x1F000 0x400>,
<0x5C000 0x400>,
<0xe0178 0x8>;
reg-names = "comphy",
"lane1_pcie_gbe",
"lane0_usb3_gbe",
"lane2_sata_usb3";
#address-cells = <1>;
#size-cells = <0>;
comphy0: phy@0 {
reg = <0>;
#phy-cells = <1>;
};
comphy1: phy@1 {
reg = <1>;
#phy-cells = <1>;
};
comphy2: phy@2 {
reg = <2>;
#phy-cells = <1>;
};
};

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* Marvell MVEBU SATA PHY
Power control for the SATA phy found on Marvell MVEBU SoCs.
This document extends the binding described in phy-bindings.txt
Required properties :
- reg : Offset and length of the register set for the SATA device
- compatible : Should be "marvell,mvebu-sata-phy"
- clocks : phandle of clock and specifier that supplies the device
- clock-names : Should be "sata"
Example:
sata-phy@84000 {
compatible = "marvell,mvebu-sata-phy";
reg = <0x84000 0x0334>;
clocks = <&gate_clk 15>;
clock-names = "sata";
#phy-cells = <0>;
};
Armada 375 USB cluster
----------------------
Armada 375 comes with an USB2 host and device controller and an USB3
controller. The USB cluster control register allows to manage common
features of both USB controllers.
Required properties:
- compatible: "marvell,armada-375-usb-cluster"
- reg: Should contain usb cluster register location and length.
- #phy-cells : from the generic phy bindings, must be 1. Possible
values are 1 (USB2), 2 (USB3).
Example:
usbcluster: usb-cluster@18400 {
compatible = "marvell,armada-375-usb-cluster";
reg = <0x18400 0x4>;
#phy-cells = <1>
};

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Marvell PXA USB PHY
-------------------
Required properties:
- compatible: one of: "marvell,mmp2-usb-phy", "marvell,pxa910-usb-phy",
"marvell,pxa168-usb-phy",
- #phy-cells: must be 0
Example:
usb-phy: usbphy@d4207000 {
compatible = "marvell,mmp2-usb-phy";
reg = <0xd4207000 0x40>;
#phy-cells = <0>;
status = "okay";
};
This document explains the device tree binding. For general
information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst

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IMG Pistachio USB PHY
=====================
Required properties:
--------------------
- compatible: Must be "img,pistachio-usb-phy".
- #phy-cells: Must be 0. See ./phy-bindings.txt for details.
- clocks: Must contain an entry for each entry in clock-names.
See ../clock/clock-bindings.txt for details.
- clock-names: Must include "usb_phy".
- img,cr-top: Must contain a phandle to the CR_TOP syscon node.
- img,refclk: Indicates the reference clock source for the USB PHY.
See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
Optional properties:
--------------------
- phy-supply: USB VBUS supply. Must supply 5.0V.
Example:
--------
usb_phy: usb-phy {
compatible = "img,pistachio-usb-phy";
clocks = <&clk_core CLK_USB_PHY>;
clock-names = "usb_phy";
phy-supply = <&usb_vbus>;
img,refclk = <REFCLK_CLK_CORE>;
img,cr-top = <&cr_top>;
#phy-cells = <0>;
};

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@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qca,ar7100-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atheros AR71XX/9XXX USB PHY
maintainers:
- Alban Bedel <albeu@free.fr>
properties:
compatible:
items:
- const: qca,ar7100-usb-phy
reset-names:
description: Names of reset lines in order.
minItems: 1
items:
- const: phy
- const: suspend-override
resets:
description: References to the reset controllers.
minItems: 1
items:
- description: Reset controller for phy
- description: Reset controller for suspend-override
'#phy-cells':
const: 0
required:
- compatible
- reset-names
- resets
- '#phy-cells'
additionalProperties: false
examples:
- |
usb-phy {
compatible = "qca,ar7100-usb-phy";
reset-names = "phy", "suspend-override";
resets = <&rst 4>, <&rst 3>;
#phy-cells = <0>;
};

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@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,m31-eusb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm M31 eUSB2 phy
maintainers:
- Wesley Cheng <quic_wcheng@quicinc.com>
description:
M31 based eUSB2 controller, which supports LS/FS/HS usb connectivity
on Qualcomm chipsets. It is paired with a eUSB2 repeater.
properties:
compatible:
items:
- enum:
- qcom,sm8750-m31-eusb2-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
clocks:
items:
- description: reference clock
clock-names:
items:
- const: ref
resets:
maxItems: 1
phys:
maxItems: 1
description:
Phandle to eUSB2 repeater
vdd-supply:
description:
Phandle to 0.88V regulator supply to PHY digital circuit.
vdda12-supply:
description:
Phandle to 1.2V regulator supply to PHY refclk pll block.
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- resets
- vdd-supply
- vdda12-supply
additionalProperties: false
examples:
- |
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8750-m31-eusb2-phy";
reg = <0x88e3000 0x29c>;
clocks = <&tcsrcc_usb2_clkref_en>;
clock-names = "ref";
resets = <&gcc_qusb2phy_prim_bcr>;
#phy-cells = <0>;
vdd-supply = <&vreg_l2d_0p88>;
vdda12-supply = <&vreg_l3g_1p2>;
};

2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
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@ -145,6 +145,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,sar2130p-qmp-gen3x2-pcie-phy
- qcom,sc8180x-qmp-pcie-phy
- qcom,sdm845-qhp-pcie-phy
@ -175,7 +176,6 @@ allOf:
compatible:
contains:
enum:
- qcom,qcs615-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy

2
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@ -29,6 +29,7 @@ properties:
- qcom,sm8450-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
- qcom,sm8650-qmp-usb3-dp-phy
- qcom,sm8750-qmp-usb3-dp-phy
- qcom,x1e80100-qmp-usb3-dp-phy
reg:
@ -133,6 +134,7 @@ allOf:
- qcom,sm6350-qmp-usb3-dp-phy
- qcom,sm8550-qmp-usb3-dp-phy
- qcom,sm8650-qmp-usb3-dp-phy
- qcom,sm8750-qmp-usb3-dp-phy
- qcom,x1e80100-qmp-usb3-dp-phy
then:
required:

1
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@ -17,6 +17,7 @@ properties:
oneOf:
- items:
- enum:
- qcom,milos-snps-eusb2-phy
- qcom,sar2130p-snps-eusb2-phy
- qcom,sdx75-snps-eusb2-phy
- qcom,sm8650-snps-eusb2-phy

3
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@ -39,21 +39,18 @@ properties:
description: High-Speed disconnect threshold
minimum: 0
maximum: 7
default: 0
qcom,tune-usb2-amplitude:
$ref: /schemas/types.yaml#/definitions/uint8
description: High-Speed transmit amplitude
minimum: 0
maximum: 15
default: 8
qcom,tune-usb2-preem:
$ref: /schemas/types.yaml#/definitions/uint8
description: High-Speed TX pre-emphasis tuning
minimum: 0
maximum: 7
default: 5
required:
- compatible

4
Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
View File

@ -40,6 +40,10 @@ properties:
- renesas,usb2-phy-r9a07g054 # RZ/V2L
- const: renesas,rzg2l-usb2-phy
- items:
- const: renesas,usb2-phy-r9a09g056 # RZ/V2N
- const: renesas,usb2-phy-r9a09g057
reg:
maxItems: 1

29
Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
View File

@ -29,6 +29,7 @@ properties:
- samsung,s5pv210-mipi-video-phy
- samsung,exynos5420-mipi-video-phy
- samsung,exynos5433-mipi-video-phy
- samsung,exynos7870-mipi-video-phy
"#phy-cells":
const: 1
@ -46,19 +47,20 @@ properties:
deprecated: true
description:
Phandle to PMU system controller interface, valid for
samsung,exynos5433-mipi-video-phy (if not a child of PMU).
samsung,exynos5433-mipi-video-phy and samsung,exynos7870-mipi-video-phy
(if not a child of PMU).
samsung,disp-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface, valid for
samsung,exynos5433-mipi-video-phy.
samsung,exynos5433-mipi-video-phy and samsung,exynos7870-mipi-video-phy.
samsung,cam0-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to CAM0 system controller interface, valid for
samsung,exynos5433-mipi-video-phy.
samsung,exynos5433-mipi-video-phy and samsung,exynos7870-mipi-video-phy.
samsung,cam1-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
@ -84,7 +86,13 @@ allOf:
samsung,disp-sysreg: false
samsung,cam0-sysreg: false
samsung,cam1-sysreg: false
else:
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-mipi-video-phy
then:
properties:
syscon: false
required:
@ -92,6 +100,19 @@ allOf:
- samsung,cam0-sysreg
- samsung,cam1-sysreg
- if:
properties:
compatible:
contains:
const: samsung,exynos7870-mipi-video-phy
then:
properties:
syscon: false
samsung,cam1-sysreg: false
required:
- samsung,disp-sysreg
- samsung,cam0-sysreg
additionalProperties: false
examples:

2
Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
View File

@ -33,6 +33,7 @@ properties:
- samsung,exynos7-usbdrd-phy
- samsung,exynos7870-usbdrd-phy
- samsung,exynos850-usbdrd-phy
- samsung,exynos990-usbdrd-phy
clocks:
minItems: 1
@ -217,6 +218,7 @@ allOf:
- samsung,exynos5420-usbdrd-phy
- samsung,exynos7870-usbdrd-phy
- samsung,exynos850-usbdrd-phy
- samsung,exynos990-usbdrd-phy
then:
properties:
clocks:

53
Documentation/devicetree/bindings/phy/st,spear1310-miphy.yaml Normal file
View File

@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/st,spear1310-miphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ST SPEAr miphy
maintainers:
- Pratyush Anand <pratyush.anand@gmail.com>
description:
ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
properties:
compatible:
enum:
- st,spear1310-miphy
- st,spear1340-miphy
reg:
maxItems: 1
misc:
description: Phandle for the syscon node to access misc registers.
$ref: /schemas/types.yaml#/definitions/phandle
'#phy-cells':
description: >
Cell[0] indicates interface type: 0 = SATA, 1 = PCIe.
const: 1
phy-id:
description: Instance id of the phy. Required when multiple PHYs are present.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- misc
- '#phy-cells'
additionalProperties: false
examples:
- |
miphy@1000 {
compatible = "st,spear1310-miphy";
reg = <0x1000 0x100>;
misc = <&syscon>;
#phy-cells = <1>;
phy-id = <0>;
};

15
Documentation/devicetree/bindings/phy/st-spear-miphy.txt
View File

@ -1,15 +0,0 @@
ST SPEAr miphy DT details
=========================
ST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA.
Required properties:
- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy"
- reg : offset and length of the PHY register set.
- misc: phandle for the syscon node to access misc registers
- #phy-cells : from the generic PHY bindings, must be 1.
- cell[1]: 0 if phy used for SATA, 1 for PCIe.
Optional properties:
- phy-id: Instance id of the phy. Only required when there are multiple phys
present on a implementation.

53
Documentation/devicetree/bindings/phy/ti,da830-usb-phy.yaml Normal file
View File

@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ti,da830-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DA8xx/OMAP-L1xx/AM18xx USB PHY
maintainers:
- David Lechner <david@lechnology.com>
description: >
This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
controllers on DA8xx SoCs.
It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
to access the CFGCHIP2 register.
properties:
compatible:
items:
- const: ti,da830-usb-phy
'#phy-cells':
const: 1
description:
Consumers of this device should use index 0 for the USB 2.0 phy device and
index 1 for the USB 1.1 phy device.
clocks:
maxItems: 2
clock-names:
items:
- const: usb0_clk48
- const: usb1_clk48
required:
- compatible
- '#phy-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
usb-phy {
compatible = "ti,da830-usb-phy";
#phy-cells = <1>;
clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
clock-names = "usb0_clk48", "usb1_clk48";
};

58
Documentation/devicetree/bindings/phy/ti,dm8168-usb-phy.yaml Normal file
View File

@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ti,dm8168-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI DM8168 USB PHY
maintainers:
- Tony Lindgren <tony@atomide.com>
properties:
compatible:
const: ti,dm8168-usb-phy
reg:
maxItems: 1
reg-names:
items:
- const: phy
clocks:
maxItems: 1
clock-names:
items:
- const: refclk
'#phy-cells':
const: 0
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle for the syscon node to access misc registers.
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- '#phy-cells'
- syscon
additionalProperties: false
examples:
- |
usb-phy@20 {
compatible = "ti,dm8168-usb-phy";
reg = <0x20 0x8>;
reg-names = "phy";
clocks = <&main_fapll 6>;
clock-names = "refclk";
#phy-cells = <0>;
syscon = <&scm_conf>;
};

37
Documentation/devicetree/bindings/phy/ti,keystone-usbphy.yaml Normal file
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/ti,keystone-usbphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Keystone USB PHY
maintainers:
- Nishanth Menon <nm@ti.com>
- Santosh Shilimkar <ssantosh@kernel.org>
description:
The main purpose of this PHY driver is to enable the USB PHY reference clock
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
phy node in the USB Glue layer driver node.
properties:
compatible:
const: ti,keystone-usbphy
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
usb-phy@2620738 {
compatible = "ti,keystone-usbphy";
reg = <0x2620738 32>;
};

3
Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
View File

@ -32,6 +32,7 @@ properties:
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
- qcom,ipq9574-dwc3
- qcom,milos-dwc3
- qcom,msm8953-dwc3
- qcom,msm8994-dwc3
- qcom,msm8996-dwc3
@ -338,6 +339,7 @@ allOf:
compatible:
contains:
enum:
- qcom,milos-dwc3
- qcom,qcm2290-dwc3
- qcom,qcs615-dwc3
- qcom,sar2130p-dwc3
@ -453,6 +455,7 @@ allOf:
compatible:
contains:
enum:
- qcom,milos-dwc3
- qcom,x1e80100-dwc3
then:
properties:

4
MAINTAINERS
View File

@ -3918,7 +3918,7 @@ M: Alban Bedel <albeu@free.fr>
S: Maintained
W: https://github.com/AlbanBedel/linux
T: git https://github.com/AlbanBedel/linux.git
F: Documentation/devicetree/bindings/phy/phy-ath79-usb.txt
F: Documentation/devicetree/bindings/phy/qca,ar7100-usb-phy.yaml
F: drivers/phy/qualcomm/phy-ath79-usb.c
ATHEROS ATH GENERIC UTILITIES
@ -14700,7 +14700,7 @@ MARVELL ARMADA 3700 PHY DRIVERS
M: Miquel Raynal <miquel.raynal@bootlin.com>
S: Maintained
F: Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml
F: Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt
F: Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
F: drivers/phy/marvell/phy-mvebu-a3700-comphy.c
F: drivers/phy/marvell/phy-mvebu-a3700-utmi.c

2
drivers/phy/broadcom/phy-bcm-ns2-pcie.c
View File

@ -61,8 +61,6 @@ static int ns2_pci_phy_probe(struct mdio_device *mdiodev)
return PTR_ERR(provider);
}
dev_info(dev, "%s PHY registered\n", dev_name(dev));
return 0;
}

1
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
View File

@ -395,7 +395,6 @@ static int ns2_drd_phy_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, driver);
dev_info(dev, "Registered NS2 DRD Phy device\n");
queue_delayed_work(system_power_efficient_wq, &driver->wq_extcon,
driver->debounce_jiffies);

2
drivers/phy/broadcom/phy-bcm-sr-pcie.c
View File

@ -277,8 +277,6 @@ static int sr_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(provider);
}
dev_info(dev, "Stingray PCIe PHY driver initialized\n");
return 0;
}

2
drivers/phy/broadcom/phy-brcm-sata.c
View File

@ -832,7 +832,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
return PTR_ERR(provider);
}
dev_info(dev, "registered %d port(s)\n", count);
dev_dbg(dev, "registered %d port(s)\n", count);
return 0;
}

180
drivers/phy/cadence/phy-cadence-sierra.c
View File

@ -58,8 +58,11 @@
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG 0xC3
#define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG 0xC5
#define SIERRA_CMN_PLLLC1_MODE_PREG 0xC8
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG 0xC9
#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
#define SIERRA_CMN_PLLLC1_CLK0_PREG 0xCE
#define SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG 0xCF
#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
@ -1541,6 +1544,137 @@ static void cdns_sierra_phy_remove(struct platform_device *pdev)
cdns_sierra_clk_unregister(phy);
}
/* USB refclk 100MHz, 20b, SuperSpeed opt2, ext ssc, PLL LC1, multilink */
static const struct cdns_reg_pairs usb_100_ext_ssc_plllc1_cmn_regs[] = {
{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
{0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE1_PREG},
{0x2086, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},
{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE1_PREG},
{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
{0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
};
/* USB refclk 100MHz, 20b, SuperSpeed opt2, int ssc, PLL LC1, multilink */
static const struct cdns_reg_pairs usb_100_int_ssc_plllc1_cmn_regs[] = {
{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},
{0x000E, SIERRA_CMN_PLLLC1_MODE_PREG},
{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG}
};
static const struct cdns_reg_pairs usb_100_ml_ln_regs[] = {
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
{0x000F, SIERRA_DET_STANDEC_B_PREG},
{0x55A5, SIERRA_DET_STANDEC_C_PREG},
{0x69AD, SIERRA_DET_STANDEC_D_PREG},
{0x0241, SIERRA_DET_STANDEC_E_PREG},
{0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
{0x001D, SIERRA_PSM_A3IN_TMR_PREG},
{0x0004, SIERRA_PSC_LN_A3_PREG},
{0x0004, SIERRA_PSC_LN_IDLE_PREG},
{0x001F, SIERRA_PSC_TX_A0_PREG},
{0x0007, SIERRA_PSC_TX_A1_PREG},
{0x0003, SIERRA_PSC_TX_A2_PREG},
{0x0003, SIERRA_PSC_TX_A3_PREG},
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
{0x0619, SIERRA_PSC_RX_A1_PREG},
{0x0003, SIERRA_PSC_RX_A2_PREG},
{0x0001, SIERRA_PSC_RX_A3_PREG},
{0x0606, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},
{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
{0x5211, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
{0x023F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
{0x8452, SIERRA_CTLELUT_CTRL_PREG},
{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
{0x0002, SIERRA_DEQ_PHALIGN_CTRL},
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
{0xA9A9, SIERRA_DEQ_VGATUNE_CTRL_PREG},
{0x0014, SIERRA_DEQ_GLUT0},
{0x0014, SIERRA_DEQ_GLUT1},
{0x0014, SIERRA_DEQ_GLUT2},
{0x0014, SIERRA_DEQ_GLUT3},
{0x0014, SIERRA_DEQ_GLUT4},
{0x0014, SIERRA_DEQ_GLUT5},
{0x0014, SIERRA_DEQ_GLUT6},
{0x0014, SIERRA_DEQ_GLUT7},
{0x0014, SIERRA_DEQ_GLUT8},
{0x0014, SIERRA_DEQ_GLUT9},
{0x0014, SIERRA_DEQ_GLUT10},
{0x0014, SIERRA_DEQ_GLUT11},
{0x0014, SIERRA_DEQ_GLUT12},
{0x0014, SIERRA_DEQ_GLUT13},
{0x0014, SIERRA_DEQ_GLUT14},
{0x0014, SIERRA_DEQ_GLUT15},
{0x0014, SIERRA_DEQ_GLUT16},
{0x0BAE, SIERRA_DEQ_ALUT0},
{0x0AEB, SIERRA_DEQ_ALUT1},
{0x0A28, SIERRA_DEQ_ALUT2},
{0x0965, SIERRA_DEQ_ALUT3},
{0x08A2, SIERRA_DEQ_ALUT4},
{0x07DF, SIERRA_DEQ_ALUT5},
{0x071C, SIERRA_DEQ_ALUT6},
{0x0659, SIERRA_DEQ_ALUT7},
{0x0596, SIERRA_DEQ_ALUT8},
{0x0514, SIERRA_DEQ_ALUT9},
{0x0492, SIERRA_DEQ_ALUT10},
{0x0410, SIERRA_DEQ_ALUT11},
{0x038E, SIERRA_DEQ_ALUT12},
{0x030C, SIERRA_DEQ_ALUT13},
{0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
{0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
{0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
{0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
{0x0033, SIERRA_DEQ_PICTRL_PREG},
{0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
{0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
{0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
{0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
{0x000F, SIERRA_LFPSFILT_NS_PREG},
{0x0009, SIERRA_LFPSFILT_RD_PREG},
{0x0001, SIERRA_LFPSFILT_MP_PREG},
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
{0x8009, SIERRA_SDFILT_L2H_PREG},
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
{0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
};
static const struct cdns_sierra_vals usb_100_ext_ssc_plllc1_cmn_vals = {
.reg_pairs = usb_100_ext_ssc_plllc1_cmn_regs,
.num_regs = ARRAY_SIZE(usb_100_ext_ssc_plllc1_cmn_regs),
};
static const struct cdns_sierra_vals usb_100_int_ssc_plllc1_cmn_vals = {
.reg_pairs = usb_100_int_ssc_plllc1_cmn_regs,
.num_regs = ARRAY_SIZE(usb_100_int_ssc_plllc1_cmn_regs),
};
static const struct cdns_sierra_vals usb_100_ml_ln_vals = {
.reg_pairs = usb_100_ml_ln_regs,
.num_regs = ARRAY_SIZE(usb_100_ml_ln_regs),
};
/* SGMII PHY PMA lane configuration */
static const struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {
{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
@ -2513,6 +2647,11 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
[TYPE_USB] = {
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
},
},
.pma_cmn_vals = {
@ -2532,11 +2671,20 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
},
[TYPE_USB] = {
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
},
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
},
[TYPE_PCIE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals,
[INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals,
},
},
[TYPE_SGMII] = {
[TYPE_NONE] = {
@ -2573,11 +2721,20 @@ static const struct cdns_sierra_data cdns_map_sierra = {
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
},
[TYPE_USB] = {
[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,
[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,
[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,
},
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
},
[TYPE_PCIE] = {
[EXTERNAL_SSC] = &usb_100_ml_ln_vals,
[INTERNAL_SSC] = &usb_100_ml_ln_vals,
},
},
[TYPE_SGMII] = {
[TYPE_NONE] = {
@ -2620,6 +2777,11 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
[TYPE_USB] = {
[NO_SSC] = &pcie_phy_pcs_cmn_vals,
[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
},
},
},
.phy_pma_ln_vals = {
@ -2655,11 +2817,20 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
},
[TYPE_USB] = {
[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,
[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,
[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,
},
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
},
[TYPE_PCIE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_plllc1_cmn_vals,
[INTERNAL_SSC] = &usb_100_int_ssc_plllc1_cmn_vals,
},
},
[TYPE_SGMII] = {
[TYPE_PCIE] = {
@ -2693,11 +2864,20 @@ static const struct cdns_sierra_data cdns_ti_map_sierra = {
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
},
[TYPE_USB] = {
[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,
[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,
[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,
},
},
[TYPE_USB] = {
[TYPE_NONE] = {
[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
},
[TYPE_PCIE] = {
[EXTERNAL_SSC] = &usb_100_ml_ln_vals,
[INTERNAL_SSC] = &usb_100_ml_ln_vals,
},
},
[TYPE_SGMII] = {
[TYPE_PCIE] = {

288
drivers/phy/cadence/phy-cadence-torrent.c
View File

@ -197,6 +197,7 @@
#define RX_SDCAL1_INIT_TMR 0x004CU
#define RX_SDCAL1_ITER_TMR 0x004DU
#define RX_CDRLF_CNFG 0x0080U
#define RX_CDRLF_CNFG2 0x0081U
#define RX_CDRLF_CNFG3 0x0082U
#define RX_SIGDET_HL_FILT_TMR 0x0090U
#define RX_REE_GCSM1_CTRL 0x0108U
@ -204,6 +205,8 @@
#define RX_REE_GCSM1_EQENM_PH2 0x010AU
#define RX_REE_GCSM2_CTRL 0x0110U
#define RX_REE_PERGCSM_CTRL 0x0118U
#define RX_REE_PEAK_UTHR 0x0142U
#define RX_REE_PEAK_LTHR 0x0143U
#define RX_REE_ATTEN_THR 0x0149U
#define RX_REE_TAP1_CLIP 0x0171U
#define RX_REE_TAP2TON_CLIP 0x0172U
@ -212,6 +215,7 @@
#define RX_DIAG_DFE_CTRL 0x01E0U
#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
#define RX_DIAG_REE_DAC_CTRL 0x01E4U
#define RX_DIAG_NQST_CTRL 0x01E5U
#define RX_DIAG_SIGDET_TUNE 0x01E8U
#define RX_DIAG_PI_RATE 0x01F4U
@ -295,6 +299,7 @@ enum cdns_torrent_phy_type {
TYPE_QSGMII,
TYPE_USB,
TYPE_USXGMII,
TYPE_PCIE_ML,
};
enum cdns_torrent_ref_clk {
@ -693,6 +698,7 @@ static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type
case TYPE_DP:
return "DisplayPort";
case TYPE_PCIE:
case TYPE_PCIE_ML:
return "PCIe";
case TYPE_SGMII:
return "SGMII";
@ -2478,6 +2484,7 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
enum cdns_torrent_ssc_mode ssc;
struct regmap *regmap;
u32 num_regs, num_protocols, protocol;
u32 num_pcie_links = 0;
num_protocols = hweight32(cdns_phy->protocol_bitmask);
/* Maximum 2 protocols are supported */
@ -2510,6 +2517,44 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
phy_t1 = fns(cdns_phy->protocol_bitmask, 0);
phy_t2 = fns(cdns_phy->protocol_bitmask, 1);
/*
* PCIe Multilink configuration can be supported along with a
* non-PCIe protocol. The existing limitation associated with
* the standalone PCIe Multilink configuration still remains,
* implying that there can be only two links (subnodes) of the
* PHY type PCIe which constitute the PCIe Multilink.
*
* Such configurations are handled by introducing a new protocol
* namely TYPE_PCIE_ML. Both of the PCIe links which have the
* protocol as TYPE_PCIE shall be treated as though the protocol
* corresponding to them is TYPE_PCIE_ML only for the sake of
* configuring the SERDES.
*
* PCIe Multilink configuration can be identified by checking if
* there are exactly two links with phy_type set to TYPE_PCIE.
* phy_t1 and phy_t2 are modified in such cases to support the
* PCIe Multilink configuration with a non-PCIe protocol.
*/
for (node = 0; node < cdns_phy->nsubnodes; node++) {
if (cdns_phy->phys[node].phy_type == TYPE_PCIE)
num_pcie_links++;
}
if (num_pcie_links > 2) {
dev_err(dev, "cannot support PCIe Multilink with %u PCIe links\n",
num_pcie_links);
return -EINVAL;
} else if (num_pcie_links == 2) {
phy_t1 = TYPE_PCIE_ML;
for (node = 0; node < cdns_phy->nsubnodes; node++) {
if (cdns_phy->phys[node].phy_type == TYPE_PCIE) {
cdns_phy->phys[node].phy_type = TYPE_PCIE_ML;
continue;
}
phy_t2 = cdns_phy->phys[node].phy_type;
}
}
}
/**
@ -2676,6 +2721,11 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
}
}
/* Restore TYPE_PCIE_ML to TYPE_PCIE to be compatible with suspend-resume */
for (node = 0; node < cdns_phy->nsubnodes; node++)
if (cdns_phy->phys[node].phy_type == TYPE_PCIE_ML)
cdns_phy->phys[node].phy_type = TYPE_PCIE;
/* Take the PHY out of reset */
ret = reset_control_deassert(cdns_phy->phy_rst);
if (ret)
@ -3088,15 +3138,14 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
}
if (cdns_phy->nsubnodes > 1)
dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
cdns_phy->phys[0].num_lanes,
cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
cdns_phy->phys[1].num_lanes);
dev_dbg(dev, "Multi link configuration:\n");
else
dev_dbg(dev, "Single link: %s (%d lanes)",
cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
cdns_phy->phys[0].num_lanes);
dev_dbg(dev, "Single link configuration:\n");
for (i = 0; i < cdns_phy->nsubnodes; i++)
dev_dbg(dev, "%s (%d lanes)",
cdns_torrent_get_phy_type(cdns_phy->phys[i].phy_type),
cdns_phy->phys[i].num_lanes);
return 0;
@ -3131,6 +3180,132 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
cdns_torrent_clk_cleanup(cdns_phy);
}
/* Multilink PCIe and USB Same SSC link configuration */
static const struct cdns_reg_pairs ml_pcie_usb_link_cmn_regs[] = {
{0x0002, PHY_PLL_CFG},
{0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
};
static const struct cdns_reg_pairs ml_pcie_usb_xcvr_diag_ln_regs[] = {
{0x0100, XCVR_DIAG_HSCLK_SEL},
{0x0013, XCVR_DIAG_HSCLK_DIV},
{0x0812, XCVR_DIAG_PLLDRC_CTRL}
};
static const struct cdns_reg_pairs usb_ml_pcie_xcvr_diag_ln_regs[] = {
{0x0041, XCVR_DIAG_PLLDRC_CTRL},
};
static const struct cdns_torrent_vals ml_pcie_usb_link_cmn_vals = {
.reg_pairs = ml_pcie_usb_link_cmn_regs,
.num_regs = ARRAY_SIZE(ml_pcie_usb_link_cmn_regs),
};
static const struct cdns_torrent_vals ml_pcie_usb_xcvr_diag_ln_vals = {
.reg_pairs = ml_pcie_usb_xcvr_diag_ln_regs,
.num_regs = ARRAY_SIZE(ml_pcie_usb_xcvr_diag_ln_regs),
};
static const struct cdns_torrent_vals usb_ml_pcie_xcvr_diag_ln_vals = {
.reg_pairs = usb_ml_pcie_xcvr_diag_ln_regs,
.num_regs = ARRAY_SIZE(usb_ml_pcie_xcvr_diag_ln_regs),
};
/* Multi link PCIe configuration */
static const struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
{0x0002, PHY_PLL_CFG},
{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
};
static const struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
{0x0100, XCVR_DIAG_HSCLK_SEL},
{0x0001, XCVR_DIAG_HSCLK_DIV},
{0x0812, XCVR_DIAG_PLLDRC_CTRL}
};
static const struct cdns_torrent_vals ml_pcie_link_cmn_vals = {
.reg_pairs = ml_pcie_link_cmn_regs,
.num_regs = ARRAY_SIZE(ml_pcie_link_cmn_regs),
};
static const struct cdns_torrent_vals ml_pcie_xcvr_diag_ln_vals = {
.reg_pairs = ml_pcie_xcvr_diag_ln_regs,
.num_regs = ARRAY_SIZE(ml_pcie_xcvr_diag_ln_regs),
};
/* Multi link PCIe, 100 MHz Ref clk, no SSC */
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_cmn_regs[] = {
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
{0x0003, CMN_PLL1_VCOCAL_TCTRL}
};
static const struct cdns_reg_pairs ml_pcie_100_no_ssc_rx_ln_regs[] = {
{0x0019, RX_REE_TAP1_CLIP},
{0x0019, RX_REE_TAP2TON_CLIP},
{0x0008, RX_REE_PEAK_UTHR},
{0x018E, RX_CDRLF_CNFG},
{0x2E33, RX_CDRLF_CNFG2},
{0x0001, RX_DIAG_ACYA},
{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},
{0x0002, RX_DIAG_DFE_AMP_TUNE_3},
{0x0005, RX_DIAG_REE_DAC_CTRL}
};
static const struct cdns_torrent_vals ml_pcie_100_no_ssc_cmn_vals = {
.reg_pairs = ml_pcie_100_no_ssc_cmn_regs,
.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_cmn_regs),
};
static const struct cdns_torrent_vals ml_pcie_100_no_ssc_rx_ln_vals = {
.reg_pairs = ml_pcie_100_no_ssc_rx_ln_regs,
.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_rx_ln_regs),
};
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
static const struct cdns_reg_pairs ml_pcie_100_int_ssc_cmn_regs[] = {
{0x0004, CMN_PLL0_DSM_DIAG_M0},
{0x0004, CMN_PLL1_DSM_DIAG_M0},
{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
{0x0064, CMN_PLL0_INTDIV_M0},
{0x0050, CMN_PLL1_INTDIV_M0},
{0x0002, CMN_PLL0_FRACDIVH_M0},
{0x0002, CMN_PLL1_FRACDIVH_M0},
{0x0044, CMN_PLL0_HIGH_THR_M0},
{0x0036, CMN_PLL1_HIGH_THR_M0},
{0x0002, CMN_PDIAG_PLL0_CTRL_M0},
{0x0002, CMN_PDIAG_PLL1_CTRL_M0},
{0x0001, CMN_PLL0_SS_CTRL1_M0},
{0x0001, CMN_PLL1_SS_CTRL1_M0},
{0x011B, CMN_PLL0_SS_CTRL2_M0},
{0x011B, CMN_PLL1_SS_CTRL2_M0},
{0x006E, CMN_PLL0_SS_CTRL3_M0},
{0x0058, CMN_PLL1_SS_CTRL3_M0},
{0x000E, CMN_PLL0_SS_CTRL4_M0},
{0x0012, CMN_PLL1_SS_CTRL4_M0},
{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
{0x0003, CMN_PLL0_VCOCAL_TCTRL},
{0x0003, CMN_PLL1_VCOCAL_TCTRL},
{0x00C7, CMN_PLL0_LOCK_REFCNT_START},
{0x00C7, CMN_PLL1_LOCK_REFCNT_START},
{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
{0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
};
static const struct cdns_torrent_vals ml_pcie_100_int_ssc_cmn_vals = {
.reg_pairs = ml_pcie_100_int_ssc_cmn_regs,
.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_cmn_regs),
};
/* SGMII and QSGMII link configuration */
static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = {
{0x0002, PHY_PLL_CFG}
@ -4042,6 +4217,8 @@ static const struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
{0x0C02, RX_REE_ATTEN_THR},
{0x0330, RX_REE_SMGM_CTRL1},
{0x0300, RX_REE_SMGM_CTRL2},
{0x0000, RX_REE_PEAK_UTHR},
{0x01F5, RX_REE_PEAK_LTHR},
{0x0019, RX_REE_TAP1_CLIP},
{0x0019, RX_REE_TAP2TON_CLIP},
{0x1004, RX_DIAG_SIGDET_TUNE},
@ -4531,7 +4708,7 @@ static const struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
.num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
};
/* Multi link PCIe, 100 MHz Ref clk, internal SSC */
/* For PCIe (with some other protocol), 100 MHz Ref clk, internal SSC */
static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
{0x0004, CMN_PLL0_DSM_DIAG_M0},
{0x0004, CMN_PLL0_DSM_DIAG_M1},
@ -4670,12 +4847,15 @@ static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_QSGMII), &sgmii_qsgmii_link_cmn_vals},
@ -4690,6 +4870,7 @@ static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &ml_pcie_usb_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},
@ -4706,12 +4887,15 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_QSGMII), &sgmii_qsgmii_xcvr_diag_ln_vals},
@ -4726,6 +4910,7 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &usb_ml_pcie_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},
@ -4739,6 +4924,7 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
static const struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &usb_phy_pcs_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals},
@ -4756,6 +4942,10 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
@ -4770,6 +4960,10 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
@ -4802,6 +4996,10 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
@ -4838,6 +5036,10 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
@ -4852,6 +5054,10 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},
@ -4884,6 +5090,10 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
@ -4920,6 +5130,10 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
@ -4934,6 +5148,10 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
@ -4966,6 +5184,10 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
@ -5038,6 +5260,10 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
@ -5052,6 +5278,10 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
@ -5084,6 +5314,10 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
@ -5154,6 +5388,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},
@ -5168,6 +5406,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},
@ -5200,6 +5442,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},
@ -5236,6 +5482,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},
@ -5250,6 +5500,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},
@ -5282,6 +5536,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},
@ -5318,6 +5576,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
@ -5332,6 +5594,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},
@ -5364,6 +5630,10 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},

1
drivers/phy/marvell/phy-pxa-usb.c
View File

@ -325,7 +325,6 @@ static int pxa_usb_phy_probe(struct platform_device *pdev)
phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-otg");
}
dev_info(dev, "Marvell PXA USB PHY");
return 0;
}

65
drivers/phy/mediatek/phy-mtk-tphy.c
View File

@ -210,8 +210,6 @@
#define P2F_USB_FM_VALID BIT(0)
#define P2F_RG_FRCK_EN BIT(8)
#define U3P_REF_CLK 26 /* MHZ */
#define U3P_SLEW_RATE_COEF 28
#define U3P_SR_COEF_DIVISOR 1000
#define U3P_FM_DET_CYCLE_CNT 1024
@ -277,20 +275,24 @@ enum mtk_phy_version {
MTK_PHY_V3,
};
/**
* mtk_phy_pdata - SoC specific platform data
* @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT6795/8173 only)
* @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from
* fractional mode to integer to output 26MHz for U2PHY
* @sw_efuse_supported: Switches off eFuse auto-load from PHY and applies values
* read from different nvmem (usually different eFuse array)
* that is pointed at in the device tree node for this PHY
* @slew_ref_clk_mhz: Default reference clock (in MHz) for slew rate calibration
* @slew_rate_coefficient: Coefficient for slew rate calibration
* @version: PHY IP Version
*/
struct mtk_phy_pdata {
/* avoid RX sensitivity level degradation only for mt8173 */
bool avoid_rx_sen_degradation;
/*
* workaround only for mt8195, HW fix it for others of V3,
* u2phy should use integer mode instead of fractional mode of
* 48M PLL, fix it by switching PLL to 26M from default 48M
*/
bool sw_pll_48m_to_26m;
/*
* Some SoCs (e.g. mt8195) drop a bit when use auto load efuse,
* support sw way, also support it for v2/v3 optionally.
*/
bool sw_efuse_supported;
u8 slew_ref_clock_mhz;
u8 slew_rate_coefficient;
enum mtk_phy_version version;
};
@ -686,12 +688,14 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
int fm_out;
u32 tmp;
/* HW V3 doesn't support slew rate cal anymore */
if (tphy->pdata->version == MTK_PHY_V3)
return;
/* use force value */
if (instance->eye_src)
/*
* If a fixed HS slew rate (EYE) value was supplied, don't run the
* calibration sequence and prefer using that value instead; also,
* if there is no reference clock for slew calibration or there is
* no slew coefficient, this means that the slew rate calibration
* sequence is not supported.
*/
if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef)
return;
/* enable USB ring oscillator */
@ -1516,12 +1520,16 @@ static const struct phy_ops mtk_tphy_ops = {
static const struct mtk_phy_pdata tphy_v1_pdata = {
.avoid_rx_sen_degradation = false,
.slew_ref_clock_mhz = 26,
.slew_rate_coefficient = 28,
.version = MTK_PHY_V1,
};
static const struct mtk_phy_pdata tphy_v2_pdata = {
.avoid_rx_sen_degradation = false,
.sw_efuse_supported = true,
.slew_ref_clock_mhz = 26,
.slew_rate_coefficient = 28,
.version = MTK_PHY_V2,
};
@ -1532,6 +1540,8 @@ static const struct mtk_phy_pdata tphy_v3_pdata = {
static const struct mtk_phy_pdata mt8173_pdata = {
.avoid_rx_sen_degradation = true,
.slew_ref_clock_mhz = 26,
.slew_rate_coefficient = 28,
.version = MTK_PHY_V1,
};
@ -1561,7 +1571,7 @@ static int mtk_tphy_probe(struct platform_device *pdev)
struct resource *sif_res;
struct mtk_tphy *tphy;
struct resource res;
int port;
int port, ret;
tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
if (!tphy)
@ -1591,15 +1601,14 @@ static int mtk_tphy_probe(struct platform_device *pdev)
}
}
if (tphy->pdata->version < MTK_PHY_V3) {
tphy->src_ref_clk = U3P_REF_CLK;
tphy->src_coef = U3P_SLEW_RATE_COEF;
/* update parameters of slew rate calibrate if exist */
device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
&tphy->src_ref_clk);
device_property_read_u32(dev, "mediatek,src-coef",
&tphy->src_coef);
}
/* Optional properties for slew calibration variation */
ret = device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", &tphy->src_ref_clk);
if (ret)
tphy->src_ref_clk = tphy->pdata->slew_ref_clock_mhz;
ret = device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
if (ret)
tphy->src_coef = tphy->pdata->slew_rate_coefficient;
port = 0;
for_each_child_of_node_scoped(np, child_np) {

46
drivers/phy/phy-snps-eusb2.c
View File

@ -256,7 +256,7 @@ static int exynos_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy)
}
if (!config) {
dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
dev_err(&phy->phy->dev, "unsupported ref_clk_freq: %lu\n", ref_clk_freq);
return -EINVAL;
}
@ -293,7 +293,7 @@ static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy)
}
if (!config) {
dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
dev_err(&phy->phy->dev, "unsupported ref_clk_freq: %lu\n", ref_clk_freq);
return -EINVAL;
}
@ -392,7 +392,7 @@ static int qcom_snps_eusb2_hsphy_init(struct phy *p)
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_1,
PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x0));
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_4,
PHY_CFG_PLL_INT_CNTRL_MASK,
@ -437,6 +437,9 @@ static int qcom_snps_eusb2_hsphy_init(struct phy *p)
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL2,
USB2_SUSPEND_N_SEL, 0);
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG0,
CMN_CTRL_OVERRIDE_EN, 0);
return 0;
}
@ -461,39 +464,40 @@ static int snps_eusb2_hsphy_init(struct phy *p)
ret = phy_init(phy->repeater);
if (ret) {
dev_err(&p->dev, "repeater init failed. %d\n", ret);
dev_err(&p->dev, "repeater init failed: %d\n", ret);
goto disable_vreg;
}
ret = clk_bulk_prepare_enable(phy->data->num_clks, phy->clks);
if (ret) {
dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
goto disable_vreg;
dev_err(&p->dev, "failed to enable ref clock: %d\n", ret);
goto exit_repeater;
}
ret = reset_control_assert(phy->phy_reset);
if (ret) {
dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
goto disable_ref_clk;
dev_err(&p->dev, "failed to assert phy_reset: %d\n", ret);
goto disable_clks;
}
usleep_range(100, 150);
ret = reset_control_deassert(phy->phy_reset);
if (ret) {
dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
goto disable_ref_clk;
dev_err(&p->dev, "failed to de-assert phy_reset: %d\n", ret);
goto disable_clks;
}
ret = phy->data->phy_init(p);
if (ret)
goto disable_ref_clk;
goto disable_clks;
return 0;
disable_ref_clk:
disable_clks:
clk_bulk_disable_unprepare(phy->data->num_clks, phy->clks);
exit_repeater:
phy_exit(phy->repeater);
disable_vreg:
regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
@ -504,7 +508,7 @@ static int snps_eusb2_hsphy_exit(struct phy *p)
{
struct snps_eusb2_hsphy *phy = phy_get_drvdata(p);
clk_disable_unprepare(phy->ref_clk);
clk_bulk_disable_unprepare(phy->data->num_clks, phy->clks);
regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
@ -551,7 +555,7 @@ static int snps_eusb2_hsphy_probe(struct platform_device *pdev)
if (!phy->clks)
return -ENOMEM;
for (int i = 0; i < phy->data->num_clks; ++i)
for (i = 0; i < phy->data->num_clks; ++i)
phy->clks[i].id = phy->data->clk_names[i];
ret = devm_clk_bulk_get(dev, phy->data->num_clks, phy->clks);
@ -560,7 +564,7 @@ static int snps_eusb2_hsphy_probe(struct platform_device *pdev)
"failed to get phy clock(s)\n");
phy->ref_clk = NULL;
for (int i = 0; i < phy->data->num_clks; ++i) {
for (i = 0; i < phy->data->num_clks; ++i) {
if (!strcmp(phy->clks[i].id, "ref")) {
phy->ref_clk = phy->clks[i].clk;
break;
@ -582,14 +586,14 @@ static int snps_eusb2_hsphy_probe(struct platform_device *pdev)
return dev_err_probe(dev, ret,
"failed to get regulator supplies\n");
phy->repeater = devm_of_phy_optional_get(dev, np, 0);
phy->repeater = devm_of_phy_optional_get(dev, np, NULL);
if (IS_ERR(phy->repeater))
return dev_err_probe(dev, PTR_ERR(phy->repeater),
"failed to get repeater\n");
generic_phy = devm_phy_create(dev, NULL, &snps_eusb2_hsphy_ops);
if (IS_ERR(generic_phy)) {
dev_err(dev, "failed to create phy %d\n", ret);
dev_err(dev, "failed to create phy: %d\n", ret);
return PTR_ERR(generic_phy);
}
@ -600,8 +604,6 @@ static int snps_eusb2_hsphy_probe(struct platform_device *pdev)
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
dev_info(dev, "Registered Snps-eUSB2 phy\n");
return 0;
}
@ -612,7 +614,9 @@ static const struct of_device_id snps_eusb2_hsphy_of_match_table[] = {
}, {
.compatible = "samsung,exynos2200-eusb2-phy",
.data = &exynos2200_snps_eusb2_phy,
}, { },
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, snps_eusb2_hsphy_of_match_table);

16
drivers/phy/qualcomm/Kconfig
View File

@ -126,12 +126,12 @@ config PHY_QCOM_QUSB2
USB IPs on MSM SOCs.
config PHY_QCOM_EUSB2_REPEATER
tristate "Qualcomm SNPS eUSB2 Repeater Driver"
tristate "Qualcomm PMIC eUSB2 Repeater Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
select GENERIC_PHY
help
Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
PMICs. The repeater is paired with a Synopsys eUSB2 Phy
Enable support for the USB high-speed eUSB2 repeater on Qualcomm
PMICs. The repeater is paired with a Synopsys or M31 eUSB2 Phy
on Qualcomm SOCs.
config PHY_QCOM_M31_USB
@ -158,6 +158,16 @@ config PHY_QCOM_UNIPHY_PCIE_28LP
handles PHY initialization, clock management required after
resetting the hardware and power management.
config PHY_QCOM_M31_EUSB
tristate "Qualcomm M31 eUSB2 PHY driver support"
depends on USB && (ARCH_QCOM || COMPILE_TEST)
select GENERIC_PHY
help
Enable this to support M31 EUSB2 PHY transceivers on Qualcomm
chips with DWC3 USB core. It supports initializing and cleaning
up of the associated USB repeater that is paired with the eUSB2
PHY.
config PHY_QCOM_USB_HS
tristate "Qualcomm USB HS PHY module"
depends on USB_ULPI_BUS

1
drivers/phy/qualcomm/Makefile
View File

@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o
obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o
obj-$(CONFIG_PHY_QCOM_M31_EUSB) += phy-qcom-m31-eusb2.o
obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o

85
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
View File

@ -37,32 +37,13 @@
#define EUSB2_TUNE_EUSB_EQU 0x5A
#define EUSB2_TUNE_EUSB_HS_COMP_CUR 0x5B
enum eusb2_reg_layout {
TUNE_EUSB_HS_COMP_CUR,
TUNE_EUSB_EQU,
TUNE_EUSB_SLEW,
TUNE_USB2_HS_COMP_CUR,
TUNE_USB2_PREEM,
TUNE_USB2_EQU,
TUNE_USB2_SLEW,
TUNE_SQUELCH_U,
TUNE_HSDISC,
TUNE_RES_FSDIF,
TUNE_IUSB2,
TUNE_USB2_CROSSOVER,
NUM_TUNE_FIELDS,
FORCE_VAL_5 = NUM_TUNE_FIELDS,
FORCE_EN_5,
EN_CTL1,
RPTR_STATUS,
LAYOUT_SIZE,
struct eusb2_repeater_init_tbl_reg {
unsigned int reg;
unsigned int value;
};
struct eusb2_repeater_cfg {
const u32 *init_tbl;
const struct eusb2_repeater_init_tbl_reg *init_tbl;
int init_tbl_num;
const char * const *vreg_list;
int num_vregs;
@ -82,16 +63,16 @@ static const char * const pm8550b_vreg_l[] = {
"vdd18", "vdd3",
};
static const u32 pm8550b_init_tbl[NUM_TUNE_FIELDS] = {
[TUNE_IUSB2] = 0x8,
[TUNE_SQUELCH_U] = 0x3,
[TUNE_USB2_PREEM] = 0x5,
static const struct eusb2_repeater_init_tbl_reg pm8550b_init_tbl[] = {
{ EUSB2_TUNE_IUSB2, 0x8 },
{ EUSB2_TUNE_SQUELCH_U, 0x3 },
{ EUSB2_TUNE_USB2_PREEM, 0x5 },
};
static const u32 smb2360_init_tbl[NUM_TUNE_FIELDS] = {
[TUNE_IUSB2] = 0x5,
[TUNE_SQUELCH_U] = 0x3,
[TUNE_USB2_PREEM] = 0x2,
static const struct eusb2_repeater_init_tbl_reg smb2360_init_tbl[] = {
{ EUSB2_TUNE_IUSB2, 0x5 },
{ EUSB2_TUNE_SQUELCH_U, 0x3 },
{ EUSB2_TUNE_USB2_PREEM, 0x2 },
};
static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
@ -129,17 +110,10 @@ static int eusb2_repeater_init(struct phy *phy)
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
struct device_node *np = rptr->dev->of_node;
struct regmap *regmap = rptr->regmap;
const u32 *init_tbl = rptr->cfg->init_tbl;
u8 tune_usb2_preem = init_tbl[TUNE_USB2_PREEM];
u8 tune_hsdisc = init_tbl[TUNE_HSDISC];
u8 tune_iusb2 = init_tbl[TUNE_IUSB2];
u32 base = rptr->base;
u32 val;
u32 poll_val;
int ret;
of_property_read_u8(np, "qcom,tune-usb2-amplitude", &tune_iusb2);
of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &tune_hsdisc);
of_property_read_u8(np, "qcom,tune-usb2-preem", &tune_usb2_preem);
u8 val;
ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
if (ret)
@ -147,21 +121,24 @@ static int eusb2_repeater_init(struct phy *phy)
regmap_write(regmap, base + EUSB2_EN_CTL1, EUSB2_RPTR_EN);
regmap_write(regmap, base + EUSB2_TUNE_EUSB_HS_COMP_CUR, init_tbl[TUNE_EUSB_HS_COMP_CUR]);
regmap_write(regmap, base + EUSB2_TUNE_EUSB_EQU, init_tbl[TUNE_EUSB_EQU]);
regmap_write(regmap, base + EUSB2_TUNE_EUSB_SLEW, init_tbl[TUNE_EUSB_SLEW]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_HS_COMP_CUR, init_tbl[TUNE_USB2_HS_COMP_CUR]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_EQU, init_tbl[TUNE_USB2_EQU]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_SLEW, init_tbl[TUNE_USB2_SLEW]);
regmap_write(regmap, base + EUSB2_TUNE_SQUELCH_U, init_tbl[TUNE_SQUELCH_U]);
regmap_write(regmap, base + EUSB2_TUNE_RES_FSDIF, init_tbl[TUNE_RES_FSDIF]);
regmap_write(regmap, base + EUSB2_TUNE_USB2_CROSSOVER, init_tbl[TUNE_USB2_CROSSOVER]);
/* Write registers from init table */
for (int i = 0; i < rptr->cfg->init_tbl_num; i++)
regmap_write(regmap, base + rptr->cfg->init_tbl[i].reg,
rptr->cfg->init_tbl[i].value);
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, tune_usb2_preem);
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, tune_hsdisc);
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, tune_iusb2);
/* Override registers from devicetree values */
if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &val))
regmap_write(regmap, base + EUSB2_TUNE_USB2_PREEM, val);
ret = regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, val, val & RPTR_OK, 10, 5);
if (!of_property_read_u8(np, "qcom,tune-usb2-disc-thres", &val))
regmap_write(regmap, base + EUSB2_TUNE_HSDISC, val);
if (!of_property_read_u8(np, "qcom,tune-usb2-preem", &val))
regmap_write(regmap, base + EUSB2_TUNE_IUSB2, val);
/* Wait for status OK */
ret = regmap_read_poll_timeout(regmap, base + EUSB2_RPTR_STATUS, poll_val,
poll_val & RPTR_OK, 10, 5);
if (ret)
dev_err(rptr->dev, "initialization timed-out\n");
@ -264,8 +241,6 @@ static int eusb2_repeater_probe(struct platform_device *pdev)
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
dev_info(dev, "Registered Qcom-eUSB2 repeater\n");
return 0;
}

324
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c Normal file
View File

@ -0,0 +1,324 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#define USB_PHY_UTMI_CTRL0 (0x3c)
#define SLEEPM BIT(0)
#define USB_PHY_UTMI_CTRL5 (0x50)
#define POR BIT(1)
#define USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
#define SIDDQ_SEL BIT(1)
#define SIDDQ BIT(2)
#define FSEL GENMASK(6, 4)
#define FSEL_38_4_MHZ_VAL (0x6)
#define USB_PHY_HS_PHY_CTRL2 (0x64)
#define USB2_SUSPEND_N BIT(2)
#define USB2_SUSPEND_N_SEL BIT(3)
#define USB_PHY_CFG0 (0x94)
#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
#define USB_PHY_CFG1 (0x154)
#define PLL_EN BIT(0)
#define USB_PHY_FSEL_SEL (0xb8)
#define FSEL_SEL BIT(0)
#define USB_PHY_XCFGI_39_32 (0x16c)
#define HSTX_PE GENMASK(3, 2)
#define USB_PHY_XCFGI_71_64 (0x17c)
#define HSTX_SWING GENMASK(3, 0)
#define USB_PHY_XCFGI_31_24 (0x168)
#define HSTX_SLEW GENMASK(2, 0)
#define USB_PHY_XCFGI_7_0 (0x15c)
#define PLL_LOCK_TIME GENMASK(1, 0)
#define M31_EUSB_PHY_INIT_CFG(o, b, v) \
{ \
.off = o, \
.mask = b, \
.val = v, \
}
struct m31_phy_tbl_entry {
u32 off;
u32 mask;
u32 val;
};
struct m31_eusb2_priv_data {
const struct m31_phy_tbl_entry *setup_seq;
unsigned int setup_seq_nregs;
const struct m31_phy_tbl_entry *override_seq;
unsigned int override_seq_nregs;
const struct m31_phy_tbl_entry *reset_seq;
unsigned int reset_seq_nregs;
unsigned int fsel;
};
static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = {
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG1, PLL_EN, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_FSEL_SEL, FSEL_SEL, 1),
};
static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = {
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0),
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7),
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0),
M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_7_0, PLL_LOCK_TIME, 0),
};
static const struct m31_phy_tbl_entry m31_eusb_phy_reset_tbl[] = {
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL0, SLEEPM, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ_SEL, 1),
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL_COMMON0, SIDDQ, 0),
M31_EUSB_PHY_INIT_CFG(USB_PHY_UTMI_CTRL5, POR, 0),
M31_EUSB_PHY_INIT_CFG(USB_PHY_HS_PHY_CTRL2, USB2_SUSPEND_N_SEL, 0),
M31_EUSB_PHY_INIT_CFG(USB_PHY_CFG0, UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0),
};
static const struct regulator_bulk_data m31_eusb_phy_vregs[] = {
{ .supply = "vdd" },
{ .supply = "vdda12" },
};
#define M31_EUSB_NUM_VREGS ARRAY_SIZE(m31_eusb_phy_vregs)
struct m31eusb2_phy {
struct phy *phy;
void __iomem *base;
const struct m31_eusb2_priv_data *data;
enum phy_mode mode;
struct regulator_bulk_data *vregs;
struct clk *clk;
struct reset_control *reset;
struct phy *repeater;
};
static int m31eusb2_phy_write_readback(void __iomem *base, u32 offset,
const u32 mask, u32 val)
{
u32 write_val;
u32 tmp;
tmp = readl(base + offset);
tmp &= ~mask;
write_val = tmp | val;
writel(write_val, base + offset);
tmp = readl(base + offset);
tmp &= mask;
if (tmp != val) {
pr_err("write: %x to offset: %x FAILED\n", val, offset);
return -EINVAL;
}
return 0;
}
static int m31eusb2_phy_write_sequence(struct m31eusb2_phy *phy,
const struct m31_phy_tbl_entry *tbl,
int num)
{
int i;
int ret;
for (i = 0 ; i < num; i++, tbl++) {
dev_dbg(&phy->phy->dev, "Offset:%x BitMask:%x Value:%x",
tbl->off, tbl->mask, tbl->val);
ret = m31eusb2_phy_write_readback(phy->base,
tbl->off, tbl->mask,
tbl->val << __ffs(tbl->mask));
if (ret < 0)
return ret;
}
return 0;
}
static int m31eusb2_phy_set_mode(struct phy *uphy, enum phy_mode mode, int submode)
{
struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
phy->mode = mode;
return phy_set_mode_ext(phy->repeater, mode, submode);
}
static int m31eusb2_phy_init(struct phy *uphy)
{
struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
const struct m31_eusb2_priv_data *data = phy->data;
int ret;
ret = regulator_bulk_enable(M31_EUSB_NUM_VREGS, phy->vregs);
if (ret) {
dev_err(&uphy->dev, "failed to enable regulator, %d\n", ret);
return ret;
}
ret = phy_init(phy->repeater);
if (ret) {
dev_err(&uphy->dev, "repeater init failed. %d\n", ret);
goto disable_vreg;
}
ret = clk_prepare_enable(phy->clk);
if (ret) {
dev_err(&uphy->dev, "failed to enable cfg ahb clock, %d\n", ret);
goto disable_repeater;
}
/* Perform phy reset */
reset_control_assert(phy->reset);
udelay(5);
reset_control_deassert(phy->reset);
m31eusb2_phy_write_sequence(phy, data->setup_seq, data->setup_seq_nregs);
m31eusb2_phy_write_readback(phy->base,
USB_PHY_HS_PHY_CTRL_COMMON0, FSEL,
FIELD_PREP(FSEL, data->fsel));
m31eusb2_phy_write_sequence(phy, data->override_seq, data->override_seq_nregs);
m31eusb2_phy_write_sequence(phy, data->reset_seq, data->reset_seq_nregs);
return 0;
disable_repeater:
phy_exit(phy->repeater);
disable_vreg:
regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
return 0;
}
static int m31eusb2_phy_exit(struct phy *uphy)
{
struct m31eusb2_phy *phy = phy_get_drvdata(uphy);
clk_disable_unprepare(phy->clk);
regulator_bulk_disable(M31_EUSB_NUM_VREGS, phy->vregs);
phy_exit(phy->repeater);
return 0;
}
static const struct phy_ops m31eusb2_phy_gen_ops = {
.init = m31eusb2_phy_init,
.exit = m31eusb2_phy_exit,
.set_mode = m31eusb2_phy_set_mode,
.owner = THIS_MODULE,
};
static int m31eusb2_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
const struct m31_eusb2_priv_data *data;
struct device *dev = &pdev->dev;
struct m31eusb2_phy *phy;
int ret;
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
if (!phy)
return -ENOMEM;
data = device_get_match_data(dev);
if (!data)
return -EINVAL;
phy->data = data;
phy->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(phy->base))
return PTR_ERR(phy->base);
phy->reset = devm_reset_control_get_exclusive(dev, NULL);
if (IS_ERR(phy->reset))
return PTR_ERR(phy->reset);
phy->clk = devm_clk_get(dev, NULL);
if (IS_ERR(phy->clk))
return dev_err_probe(dev, PTR_ERR(phy->clk),
"failed to get clk\n");
phy->phy = devm_phy_create(dev, NULL, &m31eusb2_phy_gen_ops);
if (IS_ERR(phy->phy))
return dev_err_probe(dev, PTR_ERR(phy->phy),
"failed to create phy\n");
ret = devm_regulator_bulk_get_const(dev, M31_EUSB_NUM_VREGS,
m31_eusb_phy_vregs, &phy->vregs);
if (ret)
return dev_err_probe(dev, ret,
"failed to get regulator supplies\n");
phy_set_drvdata(phy->phy, phy);
phy->repeater = devm_of_phy_get_by_index(dev, dev->of_node, 0);
if (IS_ERR(phy->repeater))
return dev_err_probe(dev, PTR_ERR(phy->repeater),
"failed to get repeater\n");
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
return PTR_ERR_OR_ZERO(phy_provider);
}
static const struct m31_eusb2_priv_data m31_eusb_v1_data = {
.setup_seq = m31_eusb2_setup_tbl,
.setup_seq_nregs = ARRAY_SIZE(m31_eusb2_setup_tbl),
.override_seq = m31_eusb_phy_override_tbl,
.override_seq_nregs = ARRAY_SIZE(m31_eusb_phy_override_tbl),
.reset_seq = m31_eusb_phy_reset_tbl,
.reset_seq_nregs = ARRAY_SIZE(m31_eusb_phy_reset_tbl),
.fsel = FSEL_38_4_MHZ_VAL,
};
static const struct of_device_id m31eusb2_phy_id_table[] = {
{ .compatible = "qcom,sm8750-m31-eusb2-phy", .data = &m31_eusb_v1_data },
{ },
};
MODULE_DEVICE_TABLE(of, m31eusb2_phy_id_table);
static struct platform_driver m31eusb2_phy_driver = {
.probe = m31eusb2_phy_probe,
.driver = {
.name = "qcom-m31eusb2-phy",
.of_match_table = m31eusb2_phy_id_table,
},
};
module_platform_driver(m31eusb2_phy_driver);
MODULE_AUTHOR("Wesley Cheng <quic_wcheng@quicinc.com>");
MODULE_DESCRIPTION("eUSB2 Qualcomm M31 HSPHY driver");
MODULE_LICENSE("GPL");

16
drivers/phy/qualcomm/phy-qcom-m31.c
View File

@ -58,14 +58,16 @@
#define USB2_0_TX_ENABLE BIT(2)
#define USB2PHY_USB_PHY_M31_XCFGI_4 0xc8
#define HSTX_SLEW_RATE_565PS GENMASK(1, 0)
#define HSTX_SLEW_RATE_400PS GENMASK(2, 0)
#define PLL_CHARGING_PUMP_CURRENT_35UA GENMASK(4, 3)
#define ODT_VALUE_38_02_OHM GENMASK(7, 6)
#define USB2PHY_USB_PHY_M31_XCFGI_5 0xcc
#define ODT_VALUE_45_02_OHM BIT(2)
#define HSTX_PRE_EMPHASIS_LEVEL_0_55MA BIT(0)
#define USB2PHY_USB_PHY_M31_XCFGI_9 0xdc
#define HSTX_CURRENT_17_1MA_385MV BIT(1)
#define USB2PHY_USB_PHY_M31_XCFGI_11 0xe4
#define XCFG_COARSE_TUNE_NUM BIT(1)
#define XCFG_FINE_TUNE_NUM BIT(3)
@ -164,7 +166,7 @@ static struct m31_phy_regs m31_ipq5332_regs[] = {
},
{
USB2PHY_USB_PHY_M31_XCFGI_4,
HSTX_SLEW_RATE_565PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
HSTX_SLEW_RATE_400PS | PLL_CHARGING_PUMP_CURRENT_35UA | ODT_VALUE_38_02_OHM,
0
},
{
@ -174,9 +176,13 @@ static struct m31_phy_regs m31_ipq5332_regs[] = {
},
{
USB2PHY_USB_PHY_M31_XCFGI_5,
ODT_VALUE_45_02_OHM | HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
HSTX_PRE_EMPHASIS_LEVEL_0_55MA,
4
},
{
USB2PHY_USB_PHY_M31_XCFGI_9,
HSTX_CURRENT_17_1MA_385MV,
},
{
USB_PHY_UTMI_CTRL5,
0x0,
@ -305,8 +311,6 @@ static int m31usb_phy_probe(struct platform_device *pdev)
phy_set_drvdata(qphy->phy, qphy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (!IS_ERR(phy_provider))
dev_info(dev, "Registered M31 USB phy\n");
return PTR_ERR_OR_ZERO(phy_provider);
}

224
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
View File

@ -32,6 +32,7 @@
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-usb-v5.h"
#include "phy-qcom-qmp-pcs-usb-v6.h"
#include "phy-qcom-qmp-pcs-usb-v8.h"
#include "phy-qcom-qmp-dp-com-v3.h"
@ -212,6 +213,31 @@ static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
};
static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET,
[QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL,
[QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1,
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL,
/* In PCS_USB */
[QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL,
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR,
[QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL,
[QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS,
[QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS,
[QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,
[QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
[QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
[QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV,
[QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL,
[QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL,
[QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN,
[QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
};
static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@ -1471,6 +1497,139 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
};
static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c),
};
static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f),
QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12),
QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1),
QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2),
};
static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08),
};
static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10),
};
static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40),
QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00),
};
static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
@ -1781,6 +1940,22 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
.dp_dp_phy = 0x2200,
};
static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
.com = 0x0000,
.txa = 0x1400,
.rxa = 0x1600,
.txb = 0x1800,
.rxb = 0x1a00,
.usb3_serdes = 0x1000,
.usb3_pcs_misc = 0x1c00,
.usb3_pcs = 0x1e00,
.usb3_pcs_usb = 0x2100,
.dp_serdes = 0x3000,
.dp_txa = 0x3400,
.dp_txb = 0x3800,
.dp_dp_phy = 0x3c00,
};
static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {
.offsets = &qmp_combo_offsets_v3,
@ -2280,6 +2455,51 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = {
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
};
static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = {
.offsets = &qmp_combo_offsets_v8,
.serdes_tbl = sm8750_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl),
.tx_tbl = sm8750_usb3_tx_tbl,
.tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl),
.rx_tbl = sm8750_usb3_rx_tbl,
.rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl),
.pcs_tbl = sm8750_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl),
.pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl,
.pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl),
.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
.dp_tx_tbl = qmp_v6_dp_tx_tbl,
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
.swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
.dp_aux_init = qmp_v4_dp_aux_init,
.configure_dp_tx = qmp_v4_configure_dp_tx,
.configure_dp_phy = qmp_v4_configure_dp_phy,
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
.regs = qmp_v8_usb3phy_regs_layout,
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
};
static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
@ -3915,6 +4135,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
.compatible = "qcom,sm8650-qmp-usb3-dp-phy",
.data = &sm8650_usb3dpphy_cfg,
},
{
.compatible = "qcom,sm8750-qmp-usb3-dp-phy",
.data = &sm8750_usb3dpphy_cfg,
},
{
.compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
.data = &x1e80100_usb3dpphy_cfg,

89
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
View File

@ -2639,29 +2639,29 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[]
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xe4),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xe4),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xed),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe5),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x8d),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
@ -2680,12 +2680,12 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
};
@ -2699,6 +2699,8 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME, 0x27),
QMP_PHY_INIT_CFG(QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME, 0x27),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
@ -2711,11 +2713,19 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_alt_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1, 0xff),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2, 0x89),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1, 0x00),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2, 0x50),
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2, 0x00),
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
@ -2739,27 +2749,27 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xb3),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xe4),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xe6),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xd6),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7e),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
@ -2767,14 +2777,7 @@ static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x06),
};
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
@ -3191,6 +3194,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
.rx = 0x0200,
.tx2 = 0x0800,
.rx2 = 0x0a00,
.ln_shrd = 0x0e00,
};
static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
@ -3398,8 +3402,8 @@ static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = {
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
.rx = qcs8300_qmp_gen4x2_pcie_rx_alt_tbl,
.rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x2_pcie_rx_alt_tbl),
.pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
},
@ -4067,12 +4071,15 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
.rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
.rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
.pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
.pcs_lane1 = sdx65_qmp_pcie_pcs_lane1_tbl,
.pcs_lane1_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_lane1_tbl),
.ln_shrd = sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl,
.ln_shrd_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ln_shrd_tbl),
},
.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
@ -4112,8 +4119,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
.tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
.rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
.rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
.pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl),
.pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl,
.pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl),
.pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
.pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
},

2
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
View File

@ -13,6 +13,8 @@
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
#define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME 0x0f0
#define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME 0x0f4
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c

38
drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h Normal file
View File

@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_PCS_USB_V8_H_
#define QCOM_PHY_QMP_PCS_USB_V8_H_
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1 0x00
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS 0x04
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL 0x08
#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2 0x0c
#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x10
#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR 0x14
#define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL 0x18
#define QPHY_V8_PCS_USB_LFPS_TX_ECSTART 0x1c
#define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL 0x20
#define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START 0x24
#define QPHY_V8_PCS_USB_LFPS_CONFIG1 0x28
#define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME 0x2c
#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME 0x30
#define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME 0x34
#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2 0x38
#define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2 0x3c
#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L 0x40
#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H 0x44
#define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD 0x48
#define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY 0x4c
#define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH 0x50
#define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL 0x54
#define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL 0x58
#define QPHY_V8_PCS_USB_TEST_CONTROL 0x5c
#define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL 0x60
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2 0x64
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3 0x68
#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4 0x6c
#endif

4
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h
View File

@ -8,8 +8,12 @@
#define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
#define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1 0x0c4
#define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2 0x0c8
#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1 0x1b8
#define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2 0x1bc
#define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4

32
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h Normal file
View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_PCS_V8_H_
#define QCOM_PHY_QMP_PCS_V8_H_
/* Only for QMP V8 PHY - USB/PCIe PCS registers */
#define QPHY_V8_PCS_SW_RESET 0x000
#define QPHY_V8_PCS_PCS_STATUS1 0x014
#define QPHY_V8_PCS_POWER_DOWN_CONTROL 0x040
#define QPHY_V8_PCS_START_CONTROL 0x044
#define QPHY_V8_PCS_POWER_STATE_CONFIG1 0x090
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1 0x0c4
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2 0x0c8
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3 0x0cc
#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6 0x0d8
#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1 0x0dc
#define QPHY_V8_PCS_RX_SIGDET_LVL 0x188
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
#define QPHY_V8_PCS_RATE_SLEW_CNTRL1 0x198
#define QPHY_V8_PCS_CDR_RESET_TIME 0x1b0
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1 0x1c0
#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2 0x1c4
#define QPHY_V8_PCS_PCS_TX_RX_CONFIG 0x1d0
#define QPHY_V8_PCS_EQ_CONFIG1 0x1dc
#define QPHY_V8_PCS_EQ_CONFIG2 0x1e0
#define QPHY_V8_PCS_EQ_CONFIG5 0x1ec
#endif

64
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h Normal file
View File

@ -0,0 +1,64 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
/* Only for QMP V8 PHY - QSERDES COM registers */
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004
#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008
#define QSERDES_V8_COM_CP_CTRL_MODE1 0x010
#define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014
#define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018
#define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c
#define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020
#define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024
#define QSERDES_V8_COM_DEC_START_MODE1 0x028
#define QSERDES_V8_COM_DEC_START_MSB_MODE1 0x02c
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1 0x030
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1 0x034
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1 0x038
#define QSERDES_V8_COM_HSCLK_SEL_1 0x03c
#define QSERDES_V8_COM_VCO_TUNE1_MODE1 0x048
#define QSERDES_V8_COM_VCO_TUNE2_MODE1 0x04c
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x050
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x054
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058
#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c
#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060
#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064
#define QSERDES_V8_COM_CP_CTRL_MODE0 0x070
#define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074
#define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078
#define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080
#define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084
#define QSERDES_V8_COM_DEC_START_MODE0 0x088
#define QSERDES_V8_COM_DEC_START_MSB_MODE0 0x08c
#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090
#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094
#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098
#define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8
#define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac
#define QSERDES_V8_COM_BG_TIMER 0x0bc
#define QSERDES_V8_COM_SSC_EN_CENTER 0x0c0
#define QSERDES_V8_COM_SSC_PER1 0x0cc
#define QSERDES_V8_COM_SSC_PER2 0x0d0
#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc
#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8
#define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V8_COM_RESETSM_CNTRL 0x118
#define QSERDES_V8_COM_LOCK_CMP_CFG 0x124
#define QSERDES_V8_COM_VCO_TUNE_MAP 0x140
#define QSERDES_V8_COM_CORE_CLK_EN 0x170
#define QSERDES_V8_COM_CMN_CONFIG_1 0x174
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
#define QSERDES_V8_COM_ADDITIONAL_MISC 0x1b4
#define QSERDES_V8_COM_CMN_STATUS 0x2c8
#define QSERDES_V8_COM_C_READY_STATUS 0x2f0
#endif

11
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v5.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2025, The Linux Foundation. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V5_H_
#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V5_H_
#define QSERDES_v5_LN_SHRD_UCDR_PI_CTRL2 0x04c
#endif

68
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h Normal file
View File

@ -0,0 +1,68 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
#define QSERDES_V8_TX_TX_EMP_POST1_LVL 0x00c
#define QSERDES_V8_TX_TX_DRV_LVL 0x014
#define QSERDES_V8_TX_RES_CODE_LANE_TX 0x034
#define QSERDES_V8_TX_RES_CODE_LANE_RX 0x038
#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX 0x040
#define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN 0x054
#define QSERDES_V8_TX_HIGHZ_DRVR_EN 0x058
#define QSERDES_V8_TX_TX_POL_INV 0x05c
#define QSERDES_V8_TX_LANE_MODE_1 0x084
#define QSERDES_V8_TX_LANE_MODE_2 0x088
#define QSERDES_V8_TX_LANE_MODE_3 0x08c
#define QSERDES_V8_TX_LANE_MODE_4 0x090
#define QSERDES_V8_TX_LANE_MODE_5 0x094
#define QSERDES_V8_TX_RCV_DETECT_LVL_2 0x0a4
#define QSERDES_V8_TX_PI_QEC_CTRL 0x0e4
#define QSERDES_V8_RX_UCDR_FO_GAIN 0x008
#define QSERDES_V8_RX_UCDR_SO_GAIN 0x014
#define QSERDES_V8_RX_UCDR_SVS_FO_GAIN 0x020
#define QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
#define QSERDES_V8_RX_UCDR_PI_CONTROLS 0x044
#define QSERDES_V8_RX_UCDR_SB2_THRESH1 0x04c
#define QSERDES_V8_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V8_RX_UCDR_SB2_GAIN1 0x054
#define QSERDES_V8_RX_UCDR_SB2_GAIN2 0x058
#define QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE 0x060
#define QSERDES_V8_RX_VGA_CAL_CNTRL1 0x0d4
#define QSERDES_V8_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V8_RX_GM_CAL 0x0dc
#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
#define QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
#define QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
#define QSERDES_V8_RX_SIGDET_ENABLES 0x118
#define QSERDES_V8_RX_SIGDET_CNTRL 0x11c
#define QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL 0x124
#define QSERDES_V8_RX_RX_MODE_00_LOW 0x15c
#define QSERDES_V8_RX_RX_MODE_00_HIGH 0x160
#define QSERDES_V8_RX_RX_MODE_00_HIGH2 0x164
#define QSERDES_V8_RX_RX_MODE_00_HIGH3 0x168
#define QSERDES_V8_RX_RX_MODE_00_HIGH4 0x16c
#define QSERDES_V8_RX_RX_MODE_01_LOW 0x170
#define QSERDES_V8_RX_RX_MODE_01_HIGH 0x174
#define QSERDES_V8_RX_RX_MODE_01_HIGH2 0x178
#define QSERDES_V8_RX_RX_MODE_01_HIGH3 0x17c
#define QSERDES_V8_RX_RX_MODE_01_HIGH4 0x180
#define QSERDES_V8_RX_DFE_EN_TIMER 0x1a0
#define QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
#define QSERDES_V8_RX_DCC_CTRL1 0x1a8
#define QSERDES_V8_RX_VTH_CODE 0x1b0
#define QSERDES_V8_RX_SIGDET_CAL_CTRL1 0x1e4
#define QSERDES_V8_RX_SIGDET_CAL_TRIM 0x1f8
#endif

141
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
View File

@ -1758,8 +1758,9 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
static int qmp_ufs_power_on(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
void __iomem *pcs = qmp->pcs;
int ret;
@ -1775,70 +1776,14 @@ static int qmp_ufs_com_init(struct qmp_ufs *qmp)
goto err_disable_regulators;
qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
return 0;
err_disable_regulators:
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
return ret;
}
static int qmp_ufs_com_exit(struct qmp_ufs *qmp)
{
const struct qmp_phy_cfg *cfg = qmp->cfg;
reset_control_assert(qmp->ufs_reset);
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
return 0;
}
static int qmp_ufs_init(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
int ret;
dev_vdbg(qmp->dev, "Initializing QMP phy\n");
if (cfg->no_pcs_sw_reset) {
/*
* Get UFS reset, which is delayed until now to avoid a
* circular dependency where UFS needs its PHY, but the PHY
* needs this UFS reset.
*/
if (!qmp->ufs_reset) {
qmp->ufs_reset =
devm_reset_control_get_exclusive(qmp->dev,
"ufsphy");
if (IS_ERR(qmp->ufs_reset)) {
ret = PTR_ERR(qmp->ufs_reset);
dev_err(qmp->dev,
"failed to get UFS reset: %d\n",
ret);
qmp->ufs_reset = NULL;
return ret;
}
}
ret = reset_control_assert(qmp->ufs_reset);
if (ret)
return ret;
}
ret = qmp_ufs_com_init(qmp);
if (ret)
return ret;
return 0;
}
static int qmp_ufs_power_on(struct phy *phy)
static int qmp_ufs_phy_calibrate(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
@ -1847,6 +1792,10 @@ static int qmp_ufs_power_on(struct phy *phy)
unsigned int val;
int ret;
ret = reset_control_assert(qmp->ufs_reset);
if (ret)
return ret;
qmp_ufs_init_registers(qmp, cfg);
ret = reset_control_deassert(qmp->ufs_reset);
@ -1876,54 +1825,17 @@ static int qmp_ufs_power_off(struct phy *phy)
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
/* PHY reset */
if (!cfg->no_pcs_sw_reset)
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
/* stop SerDes */
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
/* Put PHY into POWER DOWN state: active low */
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
SW_PWRDN);
return 0;
}
clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
static int qmp_ufs_exit(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
qmp_ufs_com_exit(qmp);
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
return 0;
}
static int qmp_ufs_enable(struct phy *phy)
{
int ret;
ret = qmp_ufs_init(phy);
if (ret)
return ret;
ret = qmp_ufs_power_on(phy);
if (ret)
qmp_ufs_exit(phy);
return ret;
}
static int qmp_ufs_disable(struct phy *phy)
{
int ret;
ret = qmp_ufs_power_off(phy);
if (ret)
return ret;
return qmp_ufs_exit(phy);
}
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
@ -1940,9 +1852,40 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
return 0;
}
static int qmp_ufs_phy_init(struct phy *phy)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
int ret;
if (!cfg->no_pcs_sw_reset)
return 0;
/*
* Get UFS reset, which is delayed until now to avoid a
* circular dependency where UFS needs its PHY, but the PHY
* needs this UFS reset.
*/
if (!qmp->ufs_reset) {
qmp->ufs_reset =
devm_reset_control_get_exclusive(qmp->dev, "ufsphy");
if (IS_ERR(qmp->ufs_reset)) {
ret = PTR_ERR(qmp->ufs_reset);
dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret);
qmp->ufs_reset = NULL;
return ret;
}
}
return 0;
}
static const struct phy_ops qcom_qmp_ufs_phy_ops = {
.power_on = qmp_ufs_enable,
.power_off = qmp_ufs_disable,
.init = qmp_ufs_phy_init,
.power_on = qmp_ufs_power_on,
.power_off = qmp_ufs_power_off,
.calibrate = qmp_ufs_phy_calibrate,
.set_mode = qmp_ufs_set_mode,
.owner = THIS_MODULE,
};

6
drivers/phy/qualcomm/phy-qcom-qmp.h
View File

@ -25,11 +25,15 @@
#include "phy-qcom-qmp-qserdes-txrx-v6.h"
#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
#include "phy-qcom-qmp-qserdes-ln-shrd-v5.h"
#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
#include "phy-qcom-qmp-qserdes-com-v7.h"
#include "phy-qcom-qmp-qserdes-txrx-v7.h"
#include "phy-qcom-qmp-qserdes-com-v8.h"
#include "phy-qcom-qmp-qserdes-txrx-v8.h"
#include "phy-qcom-qmp-qserdes-pll.h"
#include "phy-qcom-qmp-pcs-v2.h"
@ -52,6 +56,8 @@
#include "phy-qcom-qmp-pcs-v7.h"
#include "phy-qcom-qmp-pcs-v8.h"
/* QPHY_SW_RESET bit */
#define SW_RESET BIT(0)
/* QPHY_POWER_DOWN_CONTROL */

4
drivers/phy/qualcomm/phy-qcom-qusb2.c
View File

@ -1114,9 +1114,7 @@ static int qusb2_phy_probe(struct platform_device *pdev)
phy_set_drvdata(generic_phy, qphy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (!IS_ERR(phy_provider))
dev_info(dev, "Registered Qcom-QUSB2 phy\n");
else
if (IS_ERR(phy_provider))
pm_runtime_disable(dev);
return PTR_ERR_OR_ZERO(phy_provider);

15
drivers/phy/rockchip/phy-rockchip-pcie.c
View File

@ -30,9 +30,8 @@
#define PHY_CFG_ADDR_SHIFT 1
#define PHY_CFG_DATA_MASK 0xf
#define PHY_CFG_ADDR_MASK 0x3f
#define PHY_CFG_RD_MASK 0x3ff
#define PHY_CFG_WR_ENABLE 1
#define PHY_CFG_WR_DISABLE 1
#define PHY_CFG_WR_DISABLE 0
#define PHY_CFG_WR_SHIFT 0
#define PHY_CFG_WR_MASK 1
#define PHY_CFG_PLL_LOCK 0x10
@ -160,6 +159,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
guard(mutex)(&rk_phy->pcie_mutex);
regmap_write(rk_phy->reg_base,
rk_phy->phy_data->pcie_laneoff,
HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT + inst->index));
if (rk_phy->pwr_cnt++) {
return 0;
}
@ -176,12 +181,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy)
PHY_CFG_ADDR_MASK,
PHY_CFG_ADDR_SHIFT));
regmap_write(rk_phy->reg_base,
rk_phy->phy_data->pcie_laneoff,
HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
PHY_LANE_IDLE_MASK,
PHY_LANE_IDLE_A_SHIFT + inst->index));
/*
* No documented timeout value for phy operation below,
* so we make it large enough here. And we use loop-break

52
drivers/phy/samsung/phy-exynos-mipi-video.c
View File

@ -213,6 +213,55 @@ static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
},
};
static const struct mipi_phy_device_desc exynos7870_mipi_phy = {
.num_regmaps = 3,
.regmap_names = {
"samsung,pmu-syscon",
"samsung,disp-sysreg",
"samsung,cam0-sysreg"
},
.num_phys = 4,
.phys = {
{
/* EXYNOS_MIPI_PHY_ID_CSIS0 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
.enable_val = EXYNOS4_PHY_ENABLE,
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL0,
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = BIT(0),
.resetn_reg = 0,
.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
}, {
/* EXYNOS_MIPI_PHY_ID_DSIM0 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
.enable_val = EXYNOS4_PHY_ENABLE,
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL0,
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = BIT(0),
.resetn_reg = 0,
.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
}, {
/* EXYNOS_MIPI_PHY_ID_CSIS1 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
.enable_val = EXYNOS4_PHY_ENABLE,
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL1,
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = BIT(1),
.resetn_reg = 0,
.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
}, {
/* EXYNOS_MIPI_PHY_ID_CSIS2 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
.enable_val = EXYNOS4_PHY_ENABLE,
.enable_reg = EXYNOS7870_MIPI_PHY_CONTROL2,
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = BIT(2),
.resetn_reg = 0,
.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
},
},
};
struct exynos_mipi_video_phy {
struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
int num_phys;
@ -351,6 +400,9 @@ static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
}, {
.compatible = "samsung,exynos5433-mipi-video-phy",
.data = &exynos5433_mipi_phy,
}, {
.compatible = "samsung,exynos7870-mipi-video-phy",
.data = &exynos7870_mipi_phy,
},
{ /* sentinel */ },
};

32
drivers/phy/samsung/phy-exynos5-usbdrd.c
View File

@ -2025,6 +2025,35 @@ static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = {
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
};
static const struct exynos5_usbdrd_phy_tuning exynos990_tunes_utmi_postinit[] = {
PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON,
(HSPPARACON_TXVREF |
HSPPARACON_TXPREEMPAMP | HSPPARACON_SQRX |
HSPPARACON_COMPDIS),
(FIELD_PREP_CONST(HSPPARACON_TXVREF, 7) |
FIELD_PREP_CONST(HSPPARACON_TXPREEMPAMP, 3) |
FIELD_PREP_CONST(HSPPARACON_SQRX, 5) |
FIELD_PREP_CONST(HSPPARACON_COMPDIS, 7))),
PHY_TUNING_ENTRY_LAST
};
static const struct exynos5_usbdrd_phy_tuning *exynos990_tunes[PTS_MAX] = {
[PTS_UTMI_POSTINIT] = exynos990_tunes_utmi_postinit,
};
static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = {
.phy_cfg = phy_cfg_exynos850,
.phy_ops = &exynos850_usbdrd_phy_ops,
.phy_tunes = exynos990_tunes,
.pmu_offset_usbdrd0_phy = EXYNOS990_PHY_CTRL_USB20,
.clk_names = exynos5_clk_names,
.n_clks = ARRAY_SIZE(exynos5_clk_names),
.core_clk_names = exynos5_core_clk_names,
.n_core_clks = ARRAY_SIZE(exynos5_core_clk_names),
.regulator_names = exynos5_regulator_names,
.n_regulators = ARRAY_SIZE(exynos5_regulator_names),
};
static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = {
{
.id = EXYNOS5_DRDPHY_UTMI,
@ -2228,6 +2257,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
}, {
.compatible = "samsung,exynos850-usbdrd-phy",
.data = &exynos850_usbdrd_phy
}, {
.compatible = "samsung,exynos990-usbdrd-phy",
.data = &exynos990_usbdrd_phy
},
{ },
};

2
drivers/phy/st/phy-stih407-usb.c
View File

@ -139,8 +139,6 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
if (IS_ERR(phy_provider))
return PTR_ERR(phy_provider);
dev_info(dev, "STiH407 USB Generic picoPHY driver probed!");
return 0;
}

4
drivers/phy/st/phy-stm32-usbphyc.c
View File

@ -757,8 +757,8 @@ static int stm32_usbphyc_probe(struct platform_device *pdev)
}
version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
dev_info(dev, "registered rev:%lu.%lu\n",
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
dev_dbg(dev, "registered rev: %lu.%lu\n",
FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
return 0;

1
drivers/phy/ti/phy-twl4030-usb.c
View File

@ -784,7 +784,6 @@ static int twl4030_usb_probe(struct platform_device *pdev)
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(twl->dev);
dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
return 0;
}

66
drivers/ufs/host/ufs-qcom.c
View File

@ -532,6 +532,12 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
goto out_disable_phy;
}
ret = phy_calibrate(phy);
if (ret) {
dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret);
goto out_disable_phy;
}
ufs_qcom_select_unipro_mode(host);
return 0;
@ -726,53 +732,29 @@ static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
enum ufs_notify_change_status status)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct phy *phy = host->generic_phy;
if (status == PRE_CHANGE)
return 0;
if (ufs_qcom_is_link_off(hba)) {
/*
* Disable the tx/rx lane symbol clocks before PHY is
* powered down as the PLL source should be disabled
* after downstream clocks are disabled.
*/
if (!ufs_qcom_is_link_active(hba))
ufs_qcom_disable_lane_clks(host);
phy_power_off(phy);
/* reset the connected UFS device during power down */
/* reset the connected UFS device during power down */
if (ufs_qcom_is_link_off(hba) && host->device_reset)
ufs_qcom_device_reset_ctrl(hba, true);
} else if (!ufs_qcom_is_link_active(hba)) {
ufs_qcom_disable_lane_clks(host);
}
return ufs_qcom_ice_suspend(host);
}
static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct phy *phy = host->generic_phy;
int err;
if (ufs_qcom_is_link_off(hba)) {
err = phy_power_on(phy);
if (err) {
dev_err(hba->dev, "%s: failed PHY power on: %d\n",
__func__, err);
return err;
}
err = ufs_qcom_enable_lane_clks(host);
if (err)
return err;
} else if (!ufs_qcom_is_link_active(hba)) {
err = ufs_qcom_enable_lane_clks(host);
if (err)
return err;
}
err = ufs_qcom_enable_lane_clks(host);
if (err)
return err;
return ufs_qcom_ice_resume(host);
}
@ -1151,12 +1133,20 @@ static void ufs_qcom_set_caps(struct ufs_hba *hba)
* @on: If true, enable clocks else disable them.
* @status: PRE_CHANGE or POST_CHANGE notify
*
* There are certain clocks which comes from the PHY so it needs
* to be managed together along with controller clocks which also
* provides a better power saving. Hence keep phy_power_off/on calls
* in ufs_qcom_setup_clocks, so that PHY's regulators & clks can be
* turned on/off along with UFS's clocks.
*
* Return: 0 on success, non-zero on failure.
*/
static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
enum ufs_notify_change_status status)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct phy *phy;
int err;
/*
* In case ufs_qcom_init() is not yet done, simply ignore.
@ -1166,6 +1156,8 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
if (!host)
return 0;
phy = host->generic_phy;
switch (status) {
case PRE_CHANGE:
if (on) {
@ -1175,10 +1167,22 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
/* disable device ref_clk */
ufs_qcom_dev_ref_clk_ctrl(host, false);
}
err = phy_power_off(phy);
if (err) {
dev_err(hba->dev, "phy power off failed, ret=%d\n", err);
return err;
}
}
break;
case POST_CHANGE:
if (on) {
err = phy_power_on(phy);
if (err) {
dev_err(hba->dev, "phy power on failed, ret = %d\n", err);
return err;
}
/* enable the device ref clock for HS mode*/
if (ufshcd_is_hs_mode(&hba->pwr_info))
ufs_qcom_dev_ref_clk_ctrl(host, true);

8
include/linux/soc/samsung/exynos-regs-pmu.h
View File

@ -662,6 +662,14 @@
#define EXYNOS5433_PAD_RETENTION_UFS_OPTION (0x3268)
#define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8)
/* For Exynos990 */
#define EXYNOS990_PHY_CTRL_USB20 (0x72C)
/* For Exynos7870 */
#define EXYNOS7870_MIPI_PHY_CONTROL0 (0x070c)
#define EXYNOS7870_MIPI_PHY_CONTROL1 (0x0714)
#define EXYNOS7870_MIPI_PHY_CONTROL2 (0x0734)
/* For Tensor GS101 */
/* PMU ALIVE */
#define GS101_SYSIP_DAT0 (0x810)