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Code

drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.

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Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2017-05-04 13:32:01 +08:00 committed by Alex Deucher
parent 5784d5cca6
commit 7b52db39a4
1 changed files with 34 additions and 33 deletions
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67
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
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@ -4189,55 +4189,56 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
switch (type) { switch (type) {
case PP_SCLK: case PP_SCLK:
if (data->registry_data.sclk_dpm_key_disabled)
break;
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
if (mask & (1 << i)) if (mask & (1 << i))
break; break;
} }
data->smc_state_table.gfx_boot_level = i;
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( for (i = 31; i >= 0; i--) {
hwmgr->smumgr, if (mask & (1 << i))
PPSMC_MSG_SetSoftMinGfxclkByIndex, break;
i), }
"Failed to set soft min sclk index!", data->smc_state_table.gfx_max_level = i;
return -1);
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
"Failed to upload boot level to lowest!",
return -EINVAL);
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
"Failed to upload dpm max level to highest!",
return -EINVAL);
break; break;
case PP_MCLK: case PP_MCLK:
if (data->registry_data.mclk_dpm_key_disabled)
break;
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
if (mask & (1 << i)) if (mask & (1 << i))
break; break;
} }
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter( for (i = 0; i < 32; i++) {
hwmgr->smumgr, if (mask & (1 << i))
PPSMC_MSG_SetSoftMinUclkByIndex, break;
i), }
"Failed to set soft min mclk index!", data->smc_state_table.mem_boot_level = i;
return -1);
for (i = 31; i >= 0; i--) {
if (mask & (1 << i))
break;
}
data->smc_state_table.mem_max_level = i;
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
"Failed to upload boot level to lowest!",
return -EINVAL);
PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
"Failed to upload dpm max level to highest!",
return -EINVAL);
break; break;
case PP_PCIE: case PP_PCIE:
if (data->registry_data.pcie_dpm_key_disabled)
break;
for (i = 0; i < 32; i++) {
if (mask & (1 << i))
break;
}
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
PPSMC_MSG_SetMinLinkDpmByIndex,
i),
"Failed to set min pcie index!",
return -1);
break;
default: default:
break; break;
} }