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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: imx: imx8mp: Add audiomix block control
Unlike the other block control IPs in i.MX8M, the audiomix is mostly a series of clock gates and muxes. Model it as a large static table of gates and muxes with one exception, which is the PLL14xx . The PLL14xx SAI PLL has to be registered separately. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230301163257.49005-2-marex@denx.de
This commit is contained in:
Marek Vasut
Abel Vesa
parent
27fc5ec673
commit
6cd95f7b15
@ -27,7 +27,7 @@ obj-$(CONFIG_MXC_CLK) += mxc-clk.o
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obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
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obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o
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obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
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obj-$(CONFIG_CLK_IMX8MN) += clk-imx8mn.o
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obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
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obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o clk-imx8mp-audiomix.o
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obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
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obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
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obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
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obj-$(CONFIG_CLK_IMX93) += clk-imx93.o
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277
drivers/clk/imx/clk-imx8mp-audiomix.c
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277
drivers/clk/imx/clk-imx8mp-audiomix.c
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@ -0,0 +1,277 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for i.MX8M Plus Audio BLK_CTRL
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*
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* Copyright (C) 2022 Marek Vasut <marex@denx.de>
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include "clk.h"
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#define CLKEN0 0x000
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#define CLKEN1 0x004
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#define SAI_MCLK_SEL(n) (0x300 + 4 * (n)) /* n in 0..5 */
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#define PDM_SEL 0x318
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#define SAI_PLL_GNRL_CTL 0x400
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#define SAIn_MCLK1_PARENT(n) \
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static const struct clk_parent_data \
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clk_imx8mp_audiomix_sai##n##_mclk1_parents[] = { \
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{ \
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.fw_name = "sai"__stringify(n), \
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.name = "sai"__stringify(n) \
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}, { \
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.fw_name = "sai"__stringify(n)"_mclk", \
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.name = "sai"__stringify(n)"_mclk" \
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}, \
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}
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SAIn_MCLK1_PARENT(1);
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SAIn_MCLK1_PARENT(2);
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SAIn_MCLK1_PARENT(3);
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SAIn_MCLK1_PARENT(5);
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SAIn_MCLK1_PARENT(6);
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SAIn_MCLK1_PARENT(7);
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static const struct clk_parent_data clk_imx8mp_audiomix_sai_mclk2_parents[] = {
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{ .fw_name = "sai1", .name = "sai1" },
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{ .fw_name = "sai2", .name = "sai2" },
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{ .fw_name = "sai3", .name = "sai3" },
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{ .name = "dummy" },
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{ .fw_name = "sai5", .name = "sai5" },
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{ .fw_name = "sai6", .name = "sai6" },
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{ .fw_name = "sai7", .name = "sai7" },
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{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
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{ .fw_name = "sai2_mclk", .name = "sai2_mclk" },
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{ .fw_name = "sai3_mclk", .name = "sai3_mclk" },
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{ .name = "dummy" },
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{ .fw_name = "sai5_mclk", .name = "sai5_mclk" },
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{ .fw_name = "sai6_mclk", .name = "sai6_mclk" },
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{ .fw_name = "sai7_mclk", .name = "sai7_mclk" },
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{ .fw_name = "spdif_extclk", .name = "spdif_extclk" },
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{ .name = "dummy" },
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};
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static const struct clk_parent_data clk_imx8mp_audiomix_pdm_parents[] = {
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{ .fw_name = "pdm", .name = "pdm" },
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{ .name = "sai_pll_out_div2" },
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{ .fw_name = "sai1_mclk", .name = "sai1_mclk" },
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{ .name = "dummy" },
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};
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static const struct clk_parent_data clk_imx8mp_audiomix_pll_parents[] = {
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{ .fw_name = "osc_24m", .name = "osc_24m" },
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{ .name = "dummy" },
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{ .name = "dummy" },
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{ .name = "dummy" },
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};
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static const struct clk_parent_data clk_imx8mp_audiomix_pll_bypass_sels[] = {
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{ .fw_name = "sai_pll", .name = "sai_pll" },
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{ .fw_name = "sai_pll_ref_sel", .name = "sai_pll_ref_sel" },
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};
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#define CLK_GATE(gname, cname) \
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{ \
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gname"_cg", \
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IMX8MP_CLK_AUDIOMIX_##cname, \
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{ .fw_name = "ahb", .name = "ahb" }, NULL, 1, \
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CLKEN0 + 4 * !!(IMX8MP_CLK_AUDIOMIX_##cname / 32), \
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1, IMX8MP_CLK_AUDIOMIX_##cname % 32 \
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}
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#define CLK_SAIn(n) \
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{ \
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"sai"__stringify(n)"_mclk1_sel", \
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IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1_SEL, {}, \
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clk_imx8mp_audiomix_sai##n##_mclk1_parents, \
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ARRAY_SIZE(clk_imx8mp_audiomix_sai##n##_mclk1_parents), \
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SAI_MCLK_SEL(n), 1, 0 \
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}, { \
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"sai"__stringify(n)"_mclk2_sel", \
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IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2_SEL, {}, \
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clk_imx8mp_audiomix_sai_mclk2_parents, \
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ARRAY_SIZE(clk_imx8mp_audiomix_sai_mclk2_parents), \
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SAI_MCLK_SEL(n), 4, 1 \
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}, { \
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"sai"__stringify(n)"_ipg_cg", \
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IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG, \
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{ .fw_name = "ahb", .name = "ahb" }, NULL, 1, \
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CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_IPG \
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}, { \
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"sai"__stringify(n)"_mclk1_cg", \
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IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1, \
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{ \
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.fw_name = "sai"__stringify(n)"_mclk1_sel", \
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.name = "sai"__stringify(n)"_mclk1_sel" \
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}, NULL, 1, \
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CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK1 \
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}, { \
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"sai"__stringify(n)"_mclk2_cg", \
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IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2, \
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{ \
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.fw_name = "sai"__stringify(n)"_mclk2_sel", \
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.name = "sai"__stringify(n)"_mclk2_sel" \
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}, NULL, 1, \
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CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK2 \
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}, { \
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"sai"__stringify(n)"_mclk3_cg", \
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IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3, \
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{ \
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.fw_name = "sai_pll_out_div2", \
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.name = "sai_pll_out_div2" \
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}, NULL, 1, \
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CLKEN0, 1, IMX8MP_CLK_AUDIOMIX_SAI##n##_MCLK3 \
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}
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#define CLK_PDM \
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{ \
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"pdm_sel", IMX8MP_CLK_AUDIOMIX_PDM_SEL, {}, \
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clk_imx8mp_audiomix_pdm_parents, \
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ARRAY_SIZE(clk_imx8mp_audiomix_pdm_parents), \
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PDM_SEL, 2, 0 \
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}
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struct clk_imx8mp_audiomix_sel {
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const char *name;
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int clkid;
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const struct clk_parent_data parent; /* For gate */
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const struct clk_parent_data *parents; /* For mux */
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int num_parents;
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u16 reg;
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u8 width;
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u8 shift;
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};
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static struct clk_imx8mp_audiomix_sel sels[] = {
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CLK_GATE("asrc", ASRC_IPG),
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CLK_GATE("pdm", PDM_IPG),
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CLK_GATE("earc", EARC_IPG),
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CLK_GATE("ocrama", OCRAMA_IPG),
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CLK_GATE("aud2htx", AUD2HTX_IPG),
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CLK_GATE("earc_phy", EARC_PHY),
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CLK_GATE("sdma2", SDMA2_ROOT),
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CLK_GATE("sdma3", SDMA3_ROOT),
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CLK_GATE("spba2", SPBA2_ROOT),
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CLK_GATE("dsp", DSP_ROOT),
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CLK_GATE("dspdbg", DSPDBG_ROOT),
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CLK_GATE("edma", EDMA_ROOT),
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CLK_GATE("audpll", AUDPLL_ROOT),
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CLK_GATE("mu2", MU2_ROOT),
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CLK_GATE("mu3", MU3_ROOT),
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CLK_PDM,
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CLK_SAIn(1),
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CLK_SAIn(2),
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CLK_SAIn(3),
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CLK_SAIn(5),
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CLK_SAIn(6),
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CLK_SAIn(7)
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};
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static int clk_imx8mp_audiomix_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *priv;
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struct device *dev = &pdev->dev;
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void __iomem *base;
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struct clk_hw *hw;
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int i;
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priv = devm_kzalloc(dev,
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struct_size(priv, hws, IMX8MP_CLK_AUDIOMIX_END),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->num = IMX8MP_CLK_AUDIOMIX_END;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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for (i = 0; i < ARRAY_SIZE(sels); i++) {
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if (sels[i].num_parents == 1) {
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hw = devm_clk_hw_register_gate_parent_data(dev,
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sels[i].name, &sels[i].parent, 0,
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base + sels[i].reg, sels[i].shift, 0, NULL);
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} else {
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hw = devm_clk_hw_register_mux_parent_data_table(dev,
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sels[i].name, sels[i].parents,
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sels[i].num_parents, 0,
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base + sels[i].reg,
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sels[i].shift, sels[i].width,
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0, NULL, NULL);
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}
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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priv->hws[sels[i].clkid] = hw;
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}
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/* SAI PLL */
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hw = devm_clk_hw_register_mux_parent_data_table(dev,
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"sai_pll_ref_sel", clk_imx8mp_audiomix_pll_parents,
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ARRAY_SIZE(clk_imx8mp_audiomix_pll_parents),
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CLK_SET_RATE_NO_REPARENT, base + SAI_PLL_GNRL_CTL,
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0, 2, 0, NULL, NULL);
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priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw;
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hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel",
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base + 0x400, &imx_1443x_pll);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL] = hw;
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hw = devm_clk_hw_register_mux_parent_data_table(dev,
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"sai_pll_bypass", clk_imx8mp_audiomix_pll_bypass_sels,
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ARRAY_SIZE(clk_imx8mp_audiomix_pll_bypass_sels),
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CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
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base + SAI_PLL_GNRL_CTL, 16, 1, 0, NULL, NULL);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS] = hw;
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hw = devm_clk_hw_register_gate(dev, "sai_pll_out", "sai_pll_bypass",
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0, base + SAI_PLL_GNRL_CTL, 13,
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0, NULL);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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priv->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT] = hw;
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hw = devm_clk_hw_register_fixed_factor(dev, "sai_pll_out_div2",
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"sai_pll_out", 0, 1, 2);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
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priv);
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}
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static const struct of_device_id clk_imx8mp_audiomix_of_match[] = {
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{ .compatible = "fsl,imx8mp-audio-blk-ctrl" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, clk_imx8mp_audiomix_of_match);
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static struct platform_driver clk_imx8mp_audiomix_driver = {
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.probe = clk_imx8mp_audiomix_probe,
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.driver = {
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.name = "imx8mp-audio-blk-ctrl",
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.of_match_table = clk_imx8mp_audiomix_of_match,
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},
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};
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module_platform_driver(clk_imx8mp_audiomix_driver);
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MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
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MODULE_DESCRIPTION("Freescale i.MX8MP Audio Block Controller driver");
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MODULE_LICENSE("GPL");
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