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Code

drm/i915/display: Store compressed bpp in U6.4 format

Browse Source 
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.

v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
 with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)

v3:
-Add separate file for 6.4 fixed point helper(Jani, Nikula)
-Add comment for magic values(Suraj)

v4:
-Fix checkpatch warnings caused by renaming(Suraj)

v5:
-Rebase.
-Use existing helpers for conversion of bpp_int to bpp_x16
 and vice versa.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn>
Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-3-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal 2023-11-10 15:40:11 +05:30
parent 0c2287c965
commit 59a266f068
10 changed files with 33 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/i915/display/icl_dsi.c
View File

@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp; int bpp;
if (crtc_state->dsc.compression_enable) if (crtc_state->dsc.compression_enable)
bpp = crtc_state->dsc.compressed_bpp; bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
else else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* compressed and non-compressed bpp. * compressed and non-compressed bpp.
*/ */
if (crtc_state->dsc.compression_enable) { if (crtc_state->dsc.compression_enable) {
mul = crtc_state->dsc.compressed_bpp; mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
} }
@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
int bpp, line_time_us, byte_clk_period_ns; int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable) if (crtc_state->dsc.compression_enable)
bpp = crtc_state->dsc.compressed_bpp; bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
else else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
struct drm_display_mode *adjusted_mode = struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode; &pipe_config->hw.adjusted_mode;
if (pipe_config->dsc.compressed_bpp) { if (pipe_config->dsc.compressed_bpp_x16) {
int div = pipe_config->dsc.compressed_bpp; int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal =

2
drivers/gpu/drm/i915/display/intel_audio.c
View File

@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal; h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
vdsc_bpp = crtc_state->dsc.compressed_bpp; vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
cdclk = i915->display.cdclk.hw.cdclk; cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */ /* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261; fec_coeff = 972261;

4
drivers/gpu/drm/i915/display/intel_bios.c
View File

@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->pipe_bpp = bpc * 3; crtc_state->pipe_bpp = bpc * 3;
crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,
VBT_DSC_MAX_BPP(dsc->max_bpp)); VBT_DSC_MAX_BPP(dsc->max_bpp)));
/* /*
* FIXME: This is ugly, and slice count should take DSC engine * FIXME: This is ugly, and slice count should take DSC engine

5
drivers/gpu/drm/i915/display/intel_cdclk.c
View File

@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
*/ */
int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24; int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) / int min_cdclk_bj =
(2 * bigjoiner_interface_bits); (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
pixel_clock) / (2 * bigjoiner_interface_bits);
min_cdclk = max(min_cdclk, min_cdclk_bj); min_cdclk = max(min_cdclk, min_cdclk_bj);
} }

2
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(dsc.compression_enable); PIPE_CONF_CHECK_I(dsc.compression_enable);
PIPE_CONF_CHECK_I(dsc.dsc_split); PIPE_CONF_CHECK_I(dsc.dsc_split);
PIPE_CONF_CHECK_I(dsc.compressed_bpp); PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
PIPE_CONF_CHECK_BOOL(splitter.enable); PIPE_CONF_CHECK_BOOL(splitter.enable);
PIPE_CONF_CHECK_I(splitter.link_count); PIPE_CONF_CHECK_I(splitter.link_count);

3
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1363,7 +1363,8 @@ struct intel_crtc_state {
struct { struct {
bool compression_enable; bool compression_enable;
bool dsc_split; bool dsc_split;
u16 compressed_bpp; /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
u16 compressed_bpp_x16;
u8 slice_count; u8 slice_count;
struct drm_dsc_config config; struct drm_dsc_config config;
} dsc; } dsc;

27
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -1885,7 +1885,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
valid_dsc_bpp[i], valid_dsc_bpp[i],
timeslots); timeslots);
if (ret == 0) { if (ret == 0) {
pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i]; pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(valid_dsc_bpp[i]);
return 0; return 0;
} }
} }
@ -1923,7 +1924,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
compressed_bpp, compressed_bpp,
timeslots); timeslots);
if (ret == 0) { if (ret == 0) {
pipe_config->dsc.compressed_bpp = compressed_bpp; pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(compressed_bpp);
return 0; return 0;
} }
} }
@ -2120,7 +2122,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
/* Compressed BPP should be less than the Input DSC bpp */ /* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp); pipe_config->dsc.compressed_bpp_x16 =
to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
pipe_config->pipe_bpp = pipe_bpp; pipe_config->pipe_bpp = pipe_bpp;
@ -2209,18 +2212,18 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
ret = intel_dp_dsc_compute_params(connector, pipe_config); ret = intel_dp_dsc_compute_params(connector, pipe_config);
if (ret < 0) { if (ret < 0) {
drm_dbg_kms(&dev_priv->drm, drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp = %d " "Cannot compute valid DSC parameters for Input Bpp = %d"
"Compressed BPP = %d\n", "Compressed BPP = " BPP_X16_FMT "\n",
pipe_config->pipe_bpp, pipe_config->pipe_bpp,
pipe_config->dsc.compressed_bpp); BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
return ret; return ret;
} }
pipe_config->dsc.compression_enable = true; pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
"Compressed Bpp = %d Slice Count = %d\n", "Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
pipe_config->pipe_bpp, pipe_config->pipe_bpp,
pipe_config->dsc.compressed_bpp, BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count); pipe_config->dsc.slice_count);
return 0; return 0;
@ -2393,15 +2396,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable) { if (pipe_config->dsc.compression_enable) {
drm_dbg_kms(&i915->drm, drm_dbg_kms(&i915->drm,
"DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", "DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
pipe_config->lane_count, pipe_config->port_clock, pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp, pipe_config->pipe_bpp,
pipe_config->dsc.compressed_bpp); BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
drm_dbg_kms(&i915->drm, drm_dbg_kms(&i915->drm,
"DP link rate required %i available %i\n", "DP link rate required %i available %i\n",
intel_dp_link_required(adjusted_mode->crtc_clock, intel_dp_link_required(adjusted_mode->crtc_clock,
pipe_config->dsc.compressed_bpp), to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
intel_dp_max_data_rate(pipe_config->port_clock, intel_dp_max_data_rate(pipe_config->port_clock,
pipe_config->lane_count)); pipe_config->lane_count));
} else { } else {
@ -2863,7 +2866,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
drm_dp_enhanced_frame_cap(intel_dp->dpcd); drm_dp_enhanced_frame_cap(intel_dp->dpcd);
if (pipe_config->dsc.compression_enable) if (pipe_config->dsc.compression_enable)
link_bpp = pipe_config->dsc.compressed_bpp; link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
else else
link_bpp = intel_dp_output_bpp(pipe_config->output_format, link_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp); pipe_config->pipe_bpp);

2
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -228,7 +228,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (!dsc) if (!dsc)
crtc_state->pipe_bpp = bpp; crtc_state->pipe_bpp = bpp;
else else
crtc_state->dsc.compressed_bpp = bpp; crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc); drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
} }

2
drivers/gpu/drm/i915/display/intel_link_bw.c
View File

@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
return PTR_ERR(crtc_state); return PTR_ERR(crtc_state);
if (crtc_state->dsc.compression_enable) if (crtc_state->dsc.compression_enable)
link_bpp = crtc_state->dsc.compressed_bpp; link_bpp = crtc_state->dsc.compressed_bpp_x16;
else else
/* /*
* TODO: for YUV420 the actual link bpp is only half * TODO: for YUV420 the actual link bpp is only half

4
drivers/gpu/drm/i915/display/intel_vdsc.c
View File

@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp; u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
int err; int err;
int ret; int ret;
@ -874,7 +874,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
if (vdsc_cfg->native_420) if (vdsc_cfg->native_420)
vdsc_cfg->bits_per_pixel >>= 1; vdsc_cfg->bits_per_pixel >>= 1;
crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
/* PPS 2 */ /* PPS 2 */
pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2); pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);