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net/mlx5: HWS, added actions handling
When a packet matches a flow, the actions specified for the flow are applied. The supported actions include (but not limited to) the following: - drop: packet processing is stopped - go to vport: packet is forwarded to a specified vport - go to flow table: packet is forwarded to a specified table and processing continues there - push/pop vlan: add/remove vlan header respectively to/from the packet - insert/remove header: add/remove a user-defined header to/from the packet - counter: count the packet bytes in the specified counter - tag: tag the matching flow with a provided tag value - reformat: change the packet format by adding or removing some of its headers - modify header: modify the value of the packet headers with set/add/copy ops - range: match packet on range of values Reviewed-by: Erez Shitrit <erezsh@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik
Saeed Mahameed
parent
00b9f0daef
commit
504e536d90
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/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
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#ifndef MLX5HWS_ACTION_H_
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#define MLX5HWS_ACTION_H_
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/* Max number of STEs needed for a rule (including match) */
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#define MLX5HWS_ACTION_MAX_STE 20
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/* Max number of internal subactions of ipv6_ext */
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#define MLX5HWS_ACTION_IPV6_EXT_MAX_SA 4
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enum mlx5hws_action_stc_idx {
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MLX5HWS_ACTION_STC_IDX_CTRL = 0,
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MLX5HWS_ACTION_STC_IDX_HIT = 1,
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MLX5HWS_ACTION_STC_IDX_DW5 = 2,
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MLX5HWS_ACTION_STC_IDX_DW6 = 3,
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MLX5HWS_ACTION_STC_IDX_DW7 = 4,
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MLX5HWS_ACTION_STC_IDX_MAX = 5,
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/* STC Jumvo STE combo: CTR, Hit */
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MLX5HWS_ACTION_STC_IDX_LAST_JUMBO_STE = 1,
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/* STC combo1: CTR, SINGLE, DOUBLE, Hit */
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MLX5HWS_ACTION_STC_IDX_LAST_COMBO1 = 3,
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/* STC combo2: CTR, 3 x SINGLE, Hit */
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MLX5HWS_ACTION_STC_IDX_LAST_COMBO2 = 4,
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/* STC combo2: CTR, TRIPLE, Hit */
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MLX5HWS_ACTION_STC_IDX_LAST_COMBO3 = 2,
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};
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enum mlx5hws_action_offset {
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MLX5HWS_ACTION_OFFSET_DW0 = 0,
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MLX5HWS_ACTION_OFFSET_DW5 = 5,
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MLX5HWS_ACTION_OFFSET_DW6 = 6,
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MLX5HWS_ACTION_OFFSET_DW7 = 7,
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MLX5HWS_ACTION_OFFSET_HIT = 3,
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MLX5HWS_ACTION_OFFSET_HIT_LSB = 4,
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};
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enum {
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MLX5HWS_ACTION_DOUBLE_SIZE = 8,
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MLX5HWS_ACTION_INLINE_DATA_SIZE = 4,
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MLX5HWS_ACTION_HDR_LEN_L2_MACS = 12,
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MLX5HWS_ACTION_HDR_LEN_L2_VLAN = 4,
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MLX5HWS_ACTION_HDR_LEN_L2_ETHER = 2,
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MLX5HWS_ACTION_HDR_LEN_L2 = (MLX5HWS_ACTION_HDR_LEN_L2_MACS +
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MLX5HWS_ACTION_HDR_LEN_L2_ETHER),
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MLX5HWS_ACTION_HDR_LEN_L2_W_VLAN = (MLX5HWS_ACTION_HDR_LEN_L2 +
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MLX5HWS_ACTION_HDR_LEN_L2_VLAN),
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MLX5HWS_ACTION_REFORMAT_DATA_SIZE = 64,
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DECAP_L3_NUM_ACTIONS_W_NO_VLAN = 6,
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DECAP_L3_NUM_ACTIONS_W_VLAN = 7,
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};
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enum mlx5hws_action_setter_flag {
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ASF_SINGLE1 = 1 << 0,
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ASF_SINGLE2 = 1 << 1,
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ASF_SINGLE3 = 1 << 2,
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ASF_DOUBLE = ASF_SINGLE2 | ASF_SINGLE3,
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ASF_TRIPLE = ASF_SINGLE1 | ASF_DOUBLE,
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ASF_INSERT = 1 << 3,
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ASF_REMOVE = 1 << 4,
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ASF_MODIFY = 1 << 5,
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ASF_CTR = 1 << 6,
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ASF_HIT = 1 << 7,
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};
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struct mlx5hws_action_default_stc {
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struct mlx5hws_pool_chunk nop_ctr;
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struct mlx5hws_pool_chunk nop_dw5;
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struct mlx5hws_pool_chunk nop_dw6;
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struct mlx5hws_pool_chunk nop_dw7;
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struct mlx5hws_pool_chunk default_hit;
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u32 refcount;
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};
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struct mlx5hws_action_shared_stc {
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struct mlx5hws_pool_chunk stc_chunk;
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u32 refcount;
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};
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struct mlx5hws_actions_apply_data {
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struct mlx5hws_send_engine *queue;
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struct mlx5hws_rule_action *rule_action;
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__be32 *wqe_data;
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struct mlx5hws_wqe_gta_ctrl_seg *wqe_ctrl;
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u32 jump_to_action_stc;
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struct mlx5hws_context_common_res *common_res;
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enum mlx5hws_table_type tbl_type;
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u32 next_direct_idx;
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u8 require_dep;
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};
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struct mlx5hws_actions_wqe_setter;
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typedef void (*mlx5hws_action_setter_fp)(struct mlx5hws_actions_apply_data *apply,
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struct mlx5hws_actions_wqe_setter *setter);
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struct mlx5hws_actions_wqe_setter {
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mlx5hws_action_setter_fp set_single;
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mlx5hws_action_setter_fp set_double;
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mlx5hws_action_setter_fp set_triple;
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mlx5hws_action_setter_fp set_hit;
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mlx5hws_action_setter_fp set_ctr;
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u8 idx_single;
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u8 idx_double;
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u8 idx_triple;
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u8 idx_ctr;
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u8 idx_hit;
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u8 stage_idx;
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u8 flags;
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};
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struct mlx5hws_action_template {
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struct mlx5hws_actions_wqe_setter setters[MLX5HWS_ACTION_MAX_STE];
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enum mlx5hws_action_type *action_type_arr;
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u8 num_of_action_stes;
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u8 num_actions;
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u8 only_term;
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};
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struct mlx5hws_action {
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u8 type;
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u8 flags;
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struct mlx5hws_context *ctx;
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union {
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struct {
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struct mlx5hws_pool_chunk stc[MLX5HWS_TABLE_TYPE_MAX];
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union {
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struct {
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u32 pat_id;
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u32 arg_id;
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__be64 single_action;
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u32 nope_locations;
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u8 num_of_patterns;
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u8 single_action_type;
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u8 num_of_actions;
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u8 max_num_of_actions;
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u8 require_reparse;
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} modify_header;
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struct {
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u32 arg_id;
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u32 header_size;
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u16 max_hdr_sz;
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u8 num_of_hdrs;
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u8 anchor;
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u8 e_anchor;
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u8 offset;
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bool encap;
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u8 require_reparse;
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} reformat;
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struct {
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u32 obj_id;
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u8 return_reg_id;
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} aso;
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struct {
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u16 vport_num;
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u16 esw_owner_vhca_id;
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bool esw_owner_vhca_id_valid;
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} vport;
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struct {
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u32 obj_id;
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} dest_obj;
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struct {
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struct mlx5hws_cmd_forward_tbl *fw_island;
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size_t num_dest;
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struct mlx5hws_cmd_set_fte_dest *dest_list;
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} dest_array;
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struct {
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u8 type;
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u8 start_anchor;
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u8 end_anchor;
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u8 num_of_words;
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bool decap;
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} insert_hdr;
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struct {
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/* PRM start anchor from which header will be removed */
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u8 anchor;
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/* Header remove offset in bytes, from the start
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* anchor to the location where remove header starts.
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*/
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u8 offset;
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/* Indicates the removed header size in bytes */
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size_t size;
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} remove_header;
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struct {
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struct mlx5hws_matcher_action_ste *table_ste;
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struct mlx5hws_action *hit_ft_action;
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struct mlx5hws_definer *definer;
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} range;
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};
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};
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struct ibv_flow_action *flow_action;
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u32 obj_id;
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struct ibv_qp *qp;
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};
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};
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const char *mlx5hws_action_type_to_str(enum mlx5hws_action_type action_type);
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int mlx5hws_action_get_default_stc(struct mlx5hws_context *ctx,
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u8 tbl_type);
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void mlx5hws_action_put_default_stc(struct mlx5hws_context *ctx,
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u8 tbl_type);
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void mlx5hws_action_prepare_decap_l3_data(u8 *src, u8 *dst,
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u16 num_of_actions);
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int mlx5hws_action_template_process(struct mlx5hws_action_template *at);
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bool mlx5hws_action_check_combo(struct mlx5hws_context *ctx,
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enum mlx5hws_action_type *user_actions,
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enum mlx5hws_table_type table_type);
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int mlx5hws_action_alloc_single_stc(struct mlx5hws_context *ctx,
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struct mlx5hws_cmd_stc_modify_attr *stc_attr,
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u32 table_type,
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struct mlx5hws_pool_chunk *stc);
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void mlx5hws_action_free_single_stc(struct mlx5hws_context *ctx,
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u32 table_type,
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struct mlx5hws_pool_chunk *stc);
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static inline void
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mlx5hws_action_setter_default_single(struct mlx5hws_actions_apply_data *apply,
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struct mlx5hws_actions_wqe_setter *setter)
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{
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW5] = 0;
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW5] =
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htonl(apply->common_res->default_stc->nop_dw5.offset);
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}
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static inline void
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mlx5hws_action_setter_default_double(struct mlx5hws_actions_apply_data *apply,
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struct mlx5hws_actions_wqe_setter *setter)
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{
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW6] = 0;
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] = 0;
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW6] =
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htonl(apply->common_res->default_stc->nop_dw6.offset);
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW7] =
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htonl(apply->common_res->default_stc->nop_dw7.offset);
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}
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static inline void
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mlx5hws_action_setter_default_ctr(struct mlx5hws_actions_apply_data *apply,
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struct mlx5hws_actions_wqe_setter *setter)
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{
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW0] = 0;
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_CTRL] =
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htonl(apply->common_res->default_stc->nop_ctr.offset);
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}
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static inline void
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mlx5hws_action_apply_setter(struct mlx5hws_actions_apply_data *apply,
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struct mlx5hws_actions_wqe_setter *setter,
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bool is_jumbo)
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{
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u8 num_of_actions;
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/* Set control counter */
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if (setter->set_ctr)
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setter->set_ctr(apply, setter);
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else
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mlx5hws_action_setter_default_ctr(apply, setter);
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if (!is_jumbo) {
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if (unlikely(setter->set_triple)) {
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/* Set triple on match */
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setter->set_triple(apply, setter);
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num_of_actions = MLX5HWS_ACTION_STC_IDX_LAST_COMBO3;
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} else {
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/* Set single and double on match */
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if (setter->set_single)
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setter->set_single(apply, setter);
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else
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mlx5hws_action_setter_default_single(apply, setter);
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if (setter->set_double)
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setter->set_double(apply, setter);
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else
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mlx5hws_action_setter_default_double(apply, setter);
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num_of_actions = setter->set_double ?
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MLX5HWS_ACTION_STC_IDX_LAST_COMBO1 :
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MLX5HWS_ACTION_STC_IDX_LAST_COMBO2;
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}
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} else {
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW5] = 0;
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW6] = 0;
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apply->wqe_data[MLX5HWS_ACTION_OFFSET_DW7] = 0;
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW5] = 0;
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW6] = 0;
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_DW7] = 0;
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num_of_actions = MLX5HWS_ACTION_STC_IDX_LAST_JUMBO_STE;
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}
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/* Set next/final hit action */
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setter->set_hit(apply, setter);
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/* Set number of actions */
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apply->wqe_ctrl->stc_ix[MLX5HWS_ACTION_STC_IDX_CTRL] |=
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htonl(num_of_actions << 29);
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}
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#endif /* MLX5HWS_ACTION_H_ */
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