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openrisc: Add cacheinfo support

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Add cacheinfo support for OpenRISC.

Currently, a few CPU cache attributes pertaining to OpenRISC processors
are exposed along with other unrelated CPU attributes in the procfs file
system (/proc/cpuinfo). However, a few cache attributes remain unexposed.

Provide a mechanism that the generic cacheinfo infrastructure can employ
to expose these attributes via the sysfs file system. These attributes
can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move
the implementation to pull cache attributes from the processor's
registers from arch/openrisc/kernel/setup.c with a few modifications.

This implementation is based on similar work done for MIPS and LoongArch.

Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf
Signed-off-by: Sahil Siddiq <sahilcdq0@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Sahil Siddiq 2025-04-19 21:18:19 +05:30 committed by Stafford Horne
parent 0c4a6e79ef
commit 4e6d24a309
3 changed files with 108 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/openrisc/kernel/Makefile
View File

@ -7,7 +7,7 @@ extra-y := vmlinux.lds
obj-y := head.o setup.o or32_ksyms.o process.o dma.o \
traps.o time.o irq.o entry.o ptrace.o signal.o \
sys_call_table.o unwinder.o
sys_call_table.o unwinder.o cacheinfo.o
obj-$(CONFIG_SMP) += smp.o sync-timer.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o

104
arch/openrisc/kernel/cacheinfo.c Normal file
View File

@ -0,0 +1,104 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* OpenRISC cacheinfo support
*
* Based on work done for MIPS and LoongArch. All original copyrights
* apply as per the original source declaration.
*
* OpenRISC implementation:
* Copyright (C) 2025 Sahil Siddiq <sahilcdq@proton.me>
*/
#include <linux/cacheinfo.h>
#include <asm/cpuinfo.h>
#include <asm/spr.h>
#include <asm/spr_defs.h>
static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type,
unsigned int level, struct cache_desc *cache, int cpu)
{
this_leaf->type = type;
this_leaf->level = level;
this_leaf->coherency_line_size = cache->block_size;
this_leaf->number_of_sets = cache->sets;
this_leaf->ways_of_associativity = cache->ways;
this_leaf->size = cache->size;
cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map);
}
int init_cache_level(unsigned int cpu)
{
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
int leaves = 0, levels = 0;
unsigned long upr = mfspr(SPR_UPR);
unsigned long iccfgr, dccfgr;
if (!(upr & SPR_UPR_UP)) {
printk(KERN_INFO
"-- no UPR register... unable to detect configuration\n");
return -ENOENT;
}
if (cpu_cache_is_present(SPR_UPR_DCP)) {
dccfgr = mfspr(SPR_DCCFGR);
cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
cpuinfo->dcache.size =
cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
leaves += 1;
printk(KERN_INFO
"-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
cpuinfo->dcache.size, cpuinfo->dcache.block_size,
cpuinfo->dcache.sets, cpuinfo->dcache.ways);
} else
printk(KERN_INFO "-- dcache disabled\n");
if (cpu_cache_is_present(SPR_UPR_ICP)) {
iccfgr = mfspr(SPR_ICCFGR);
cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
cpuinfo->icache.size =
cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
leaves += 1;
printk(KERN_INFO
"-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n",
cpuinfo->icache.size, cpuinfo->icache.block_size,
cpuinfo->icache.sets, cpuinfo->icache.ways);
} else
printk(KERN_INFO "-- icache disabled\n");
if (!leaves)
return -ENOENT;
levels = 1;
this_cpu_ci->num_leaves = leaves;
this_cpu_ci->num_levels = levels;
return 0;
}
int populate_cache_leaves(unsigned int cpu)
{
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
int level = 1;
if (cpu_cache_is_present(SPR_UPR_DCP)) {
ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu);
this_leaf->attributes = ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ?
CACHE_WRITE_BACK : CACHE_WRITE_THROUGH;
this_leaf++;
}
if (cpu_cache_is_present(SPR_UPR_ICP))
ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu);
this_cpu_ci->cpu_map_populated = true;
return 0;
}

44
arch/openrisc/kernel/setup.c
View File

@ -113,21 +113,6 @@ static void print_cpuinfo(void)
return;
}
if (upr & SPR_UPR_DCP)
printk(KERN_INFO
"-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
cpuinfo->dcache.size, cpuinfo->dcache.block_size,
cpuinfo->dcache.sets, cpuinfo->dcache.ways);
else
printk(KERN_INFO "-- dcache disabled\n");
if (upr & SPR_UPR_ICP)
printk(KERN_INFO
"-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)\n",
cpuinfo->icache.size, cpuinfo->icache.block_size,
cpuinfo->icache.sets, cpuinfo->icache.ways);
else
printk(KERN_INFO "-- icache disabled\n");
if (upr & SPR_UPR_DMP)
printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
@ -155,7 +140,6 @@ static void print_cpuinfo(void)
void __init setup_cpuinfo(void)
{
struct device_node *cpu;
unsigned long iccfgr, dccfgr;
int cpu_id = smp_processor_id();
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
@ -163,20 +147,6 @@ void __init setup_cpuinfo(void)
if (!cpu)
panic("Couldn't find CPU%d in device tree...\n", cpu_id);
iccfgr = mfspr(SPR_ICCFGR);
cpuinfo->icache.ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
cpuinfo->icache.sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
cpuinfo->icache.block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
cpuinfo->icache.size =
cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_size;
dccfgr = mfspr(SPR_DCCFGR);
cpuinfo->dcache.ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
cpuinfo->dcache.sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
cpuinfo->dcache.block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
cpuinfo->dcache.size =
cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_size;
if (of_property_read_u32(cpu, "clock-frequency",
&cpuinfo->clock_frequency)) {
printk(KERN_WARNING
@ -293,14 +263,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
unsigned int vr, cpucfgr;
unsigned int avr;
unsigned int version;
#ifdef CONFIG_SMP
struct cpuinfo_or1k *cpuinfo = v;
seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
#endif
vr = mfspr(SPR_VR);
cpucfgr = mfspr(SPR_CPUCFGR);
#ifdef CONFIG_SMP
seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid);
#endif
if (vr & SPR_VR_UVRP) {
vr = mfspr(SPR_VR2);
version = vr & SPR_VR2_VER;
@ -319,14 +289,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
}
seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size);
seq_printf(m, "dcache block size\t: %d bytes\n",
cpuinfo->dcache.block_size);
seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways);
seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size);
seq_printf(m, "icache block size\t: %d bytes\n",
cpuinfo->icache.block_size);
seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways);
seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));