From 4713dc185fa4cc21dcc69e7d35e347adc735126a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:08 -0500 Subject: [PATCH 01/13] ARM: dts: lpc32xx: remove usb bus and elevate all children nodes Remove usb bus and elevate all children nodes because usb bus is not existed and only group usb devices logically. Update register address and related full node name. Fix below CHECK_DTBS warnings: arm/boot/dts/nxp/lpc/lpc3250-ea3250.dtb: usb (simple-bus): $nodename:0: 'usb' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 79 ++++++++++++-------------- 1 file changed, 36 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 2236901a0031..e780451fd335 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -86,51 +86,44 @@ #dma-cells = <2>; }; - usb { + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: usb@31020000 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x31020000 0x300>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; + status = "disabled"; + }; + + usbd: usbd@31020000 { + compatible = "nxp,lpc3220-udc"; + reg = <0x31020000 0x300>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; + status = "disabled"; + }; + + i2cusb: i2c@31020300 { + compatible = "nxp,pnx-i2c"; + reg = <0x31020300 0x100>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; + #size-cells = <0>; + }; - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: usb@0 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_HOST>; - status = "disabled"; - }; - - usbd: usbd@0 { - compatible = "nxp,lpc3220-udc"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, - <30 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_LOW>; - clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; - status = "disabled"; - }; - - i2cusb: i2c@300 { - compatible = "nxp,pnx-i2c"; - reg = <0x300 0x100>; - interrupt-parent = <&sic1>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_I2C>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; + usbclk: clock-controller@31020f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0x31020f00 0x100>; + #clock-cells = <1>; }; clcd: clcd@31040000 { From 8f1dae6cf85a823ed065255ad8960890d3d4dc3b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:09 -0500 Subject: [PATCH 02/13] ARM: dts: lpc3250-ea3250: add key- prefix for gpio-keys Add key- prefix to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dtb: gpio-keys (gpio-keys): 'joy0', ... do not match any of the regexes: '^(button|...)$', 'pinctrl-[0-9]+ Reviewed-by: Vladimir Zapolskiy Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts index 63c6f17bb7c9..837a3cfa8e7c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts @@ -27,55 +27,55 @@ gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; - key1 { + key-1 { label = "KEY1"; linux,code = <1>; gpios = <&pca9532 0 0>; }; - key2 { + key-2 { label = "KEY2"; linux,code = <2>; gpios = <&pca9532 1 0>; }; - key3 { + key-3 { label = "KEY3"; linux,code = <3>; gpios = <&pca9532 2 0>; }; - key4 { + key-4 { label = "KEY4"; linux,code = <4>; gpios = <&pca9532 3 0>; }; - joy0 { + key-joy0 { label = "Joystick Key 0"; linux,code = <10>; gpios = <&gpio 2 0 0>; /* P2.0 */ }; - joy1 { + key-joy1 { label = "Joystick Key 1"; linux,code = <11>; gpios = <&gpio 2 1 0>; /* P2.1 */ }; - joy2 { + key-joy2 { label = "Joystick Key 2"; linux,code = <12>; gpios = <&gpio 2 2 0>; /* P2.2 */ }; - joy3 { + key-joy3 { label = "Joystick Key 3"; linux,code = <13>; gpios = <&gpio 2 3 0>; /* P2.3 */ }; - joy4 { + key-joy4 { label = "Joystick Key 4"; linux,code = <14>; gpios = <&gpio 2 4 0>; /* P2.4 */ From dd76e20b4c985a170c5b7a9ca781aa72be02e22d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:11 -0500 Subject: [PATCH 03/13] ARM: dts: lpc3250-phy3250: rename nodename at@0 to eeprom@0 Rename nodename at@0 to eeprom@0 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: at25@0 (atmel,at25): $nodename: 'anyOf' conditional failed, one must be fixed: 'at25@0' does not match '^eeprom@[0-9a-f]{1,2}$' 'at25@0' does not match '^fram@[0-9a-f]{1,2}$' Signed-off-by: Frank Li Reviewed-by: Vladimir Zapolskiy Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts index 21a6d0bca1e8..147ce360c4ea 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts @@ -200,7 +200,7 @@ cs-gpios = <&gpio 3 5 0>; status = "okay"; - eeprom: at25@0 { + eeprom: eeprom@0 { compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; From 867589d82f1a0e9f534dfe7bb3bcd08a5306c22e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:10 -0500 Subject: [PATCH 04/13] ARM: dts: lpc3250-phy3250: replace deprecated at25 properties with new ones Replace deprecated at25 properties with the required properties (size, address-width and pagesize), which duplicate the removed properties. Fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: at25@0 (atmel,at25): 'pagesize' is a required property arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: at25@0 (atmel,at25): $nodename: 'anyOf' conditional failed, one must be fixed: Signed-off-by: Frank Li [vzapolskiy: squashed two changes from the series and updated commit message] Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts index 147ce360c4ea..0f96ea0337a1 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts @@ -213,9 +213,9 @@ pl022,wait-state = <0>; pl022,duplex = <0>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; + size = <0x8000>; + address-width = <16>; + pagesize = <64>; }; }; From d2bfa3f72d4762f5e531bfe29781d9a62fea5847 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 24 Dec 2025 06:52:05 +0200 Subject: [PATCH 05/13] ARM: dts: lpc32xx: Update spi clock properties PL022 binding require two clocks to be defined but NXP LPC32xx platform doesn't comply with the bindings and define only one clock i.e apb_pclk. Update SPI clocks and clocks-names property by adding appropriate clock reference to make it compliant with the bindings. Noteworthy, strictly speaking the change tackles DT ABI by changing the order in the list of clock-names property values, however this level of impact is considered as acceptable. Cc: Vladimir Zapolskiy Signed-off-by: Kuldeep Singh [vzapolskiy: rebased and minor update to the commit message] Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index e780451fd335..206c66bdfe41 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -172,8 +172,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP0>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -196,8 +196,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP1>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 1594e575924c614bb376b4f0b749cef8e3fa4e29 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 24 Dec 2025 18:58:44 +0200 Subject: [PATCH 06/13] ARM: dts: lpc32xx: change NAND controllers node names The device tree node name of NAND controllers shall be 'nand-controller', while 'flash' name is the name of NAND chip device tree nodes. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 206c66bdfe41..3d5a59b2886c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -62,14 +62,14 @@ /* * Enable either SLC or MLC */ - slc: flash@20020000 { + slc: nand-controller@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; clocks = <&clk LPC32XX_CLK_SLC>; status = "disabled"; }; - mlc: flash@200a8000 { + mlc: nand-controller@200a8000 { compatible = "nxp,lpc3220-mlc"; reg = <0x200a8000 0x11000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; From d8bb9ef26e9c223c2113d08d89c2f912b22d518a Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 24 Dec 2025 18:58:45 +0200 Subject: [PATCH 07/13] ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controller SLC and MLC NAND flash controllers fire the muxed interrupt FLASH_INT to the SoC, add the interrupt property to the SLC device tree node. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 3d5a59b2886c..5ddaea8c481a 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -65,6 +65,7 @@ slc: nand-controller@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SLC>; status = "disabled"; }; From 8754c6e19b902416816057bcf38af8af52a91103 Mon Sep 17 00:00:00 2001 From: Piotr Wojtaszczyk Date: Wed, 31 Dec 2025 23:57:51 +0200 Subject: [PATCH 08/13] ARM: dts: lpc32xx: Use syscon for system control block The clock controller is a part of NXP LPC32xx system control block (SCB), and SCB provides a number of controllers apart of the clock controller. [vzapolskiy]: 1. kept a simple comment, 2. renamed SoC specific compatible to 'nxp,lpc3220-scb' due to the SoC UM, 3. changed size in 'ranges', since it should cover more SCB functions, 4. updated the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-5-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 5ddaea8c481a..e44917324aed 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -308,17 +308,17 @@ ranges = <0x20000000 0x20000000 0x30000000>; /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x40004000 0x00001000>; + syscon@40004000 { + compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd"; + reg = <0x40004000 0x1000>; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x40004000 0x1000>; clk: clock-controller@0 { compatible = "nxp,lpc3220-clk"; reg = <0x00 0x114>; #clock-cells = <1>; - clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; }; From 6b7e0f1c2a3eb66f561fdc5643752b190692e5cd Mon Sep 17 00:00:00 2001 From: Piotr Wojtaszczyk Date: Wed, 31 Dec 2025 23:57:52 +0200 Subject: [PATCH 09/13] ARM: dts: lpc32xx: Add missing DMA properties Add properties declared in the new DT binding nxp,lpc3220-dmamux.yaml and corresponding phandles. [vzapolskiy]: 1. rebased the change, 2. dmamux unit address shall be 0x78 instead of 0x7c, 3. removed unsupported 'dmas' properties from sd, ssp0, ssp1 and HS UARTs, 4. more non-functional updates by reordering properies, 5. minor updates to the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-6-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index e44917324aed..58d21f42ea4c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -67,6 +67,8 @@ reg = <0x20020000 0x1000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SLC>; + dmas = <&dma 1 1>; + dma-names = "rx-tx"; status = "disabled"; }; @@ -75,6 +77,8 @@ reg = <0x200a8000 0x11000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MLC>; + dmas = <&dma 12 1>; + dma-names = "rx-tx"; status = "disabled"; }; @@ -84,6 +88,12 @@ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_DMA>; clock-names = "apb_pclk"; + dma-channels = <8>; + dma-requests = <16>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; #dma-cells = <2>; }; @@ -184,6 +194,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + dmas = <&dmamux 11 1 0>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -208,6 +220,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + dmas = <&dmamux 3 1 0>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -216,6 +230,8 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + dmas = <&dma 0 1>, <&dma 13 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -232,6 +248,8 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + dmas = <&dma 2 1>, <&dmamux 10 1 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -322,6 +340,13 @@ clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; }; + + dmamux: dma-router@78 { + compatible = "nxp,lpc3220-dmamux"; + reg = <0x78 0x8>; + dma-masters = <&dma>; + #dma-cells = <3>; + }; }; mic: interrupt-controller@40008000 { From 14c877ddffe9d69da2c92eec390d2d0eadc8c1c6 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 31 Dec 2025 23:57:53 +0200 Subject: [PATCH 10/13] ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controller Add 'lli-bus-interface-ahb2' and 'mem-bus-interface-ahb2' properties to the PL080 DMA controller device tree node, tested with dmatest utility. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 58d21f42ea4c..b9a0d7dae4ed 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -91,7 +91,9 @@ dma-channels = <8>; dma-requests = <16>; lli-bus-interface-ahb1; + lli-bus-interface-ahb2; mem-bus-interface-ahb1; + mem-bus-interface-ahb2; memcpy-burst-size = <256>; memcpy-bus-width = <32>; #dma-cells = <2>; From c23ac0f9325ee5b3755ff9b7c3143fed7bbaebd8 Mon Sep 17 00:00:00 2001 From: Piotr Wojtaszczyk Date: Wed, 31 Dec 2025 23:57:54 +0200 Subject: [PATCH 11/13] ARM: dts: lpc32xx: Add missing properties to I2S device tree nodes Add NXP LPC32xx I2S controller device tree properties in accordance to nxp,lpc3220-i2s.yaml. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-7-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk [vzapolskiy: changes to the commit message] Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index b9a0d7dae4ed..e89ef62f9fbb 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -232,8 +232,11 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_I2S0>; dmas = <&dma 0 1>, <&dma 13 1>; dma-names = "rx", "tx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -250,8 +253,11 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_I2S1>; dmas = <&dma 2 1>, <&dmamux 10 1 1>; dma-names = "rx", "tx"; + #sound-dai-cells = <0>; status = "disabled"; }; From 71630e581a0e34c03757f5c1706f57c853b92555 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 29 Dec 2025 00:49:07 +0200 Subject: [PATCH 12/13] arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree node Motor Control PWM depends on its own supply clock, the clock gate control is present in TIMCLK_CTRL1 register. Fixes: b7d41c937ed7 ("ARM: LPC32xx: Add the motor PWM to base dts file") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index e89ef62f9fbb..7fa91d1ac9ea 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled"; }; From 2940a49ab7e31e9fc4f43637dc9ef75b5e8951d4 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 10 Jan 2026 03:45:24 +0200 Subject: [PATCH 13/13] arm: dts: lpc32xx: add interrupts property to Motor Control PWM Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt controller, the interrupt serves as period (timer limit), pulse-width (match) and capture event interrupt. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 7fa91d1ac9ea..e94df78def18 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled";