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dt-bindings: display/msm: convert MDP5 schema to YAML format
Convert the mdp5.txt into the yaml format. Changes to the existing (txt) schema: - MSM8996 has additional "iommu" clock, define it separately - Add new properties used on some of platforms: - interconnects, interconnect-names - iommus - power-domains - operating-points-v2, opp-table Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/518815/ Link: https://lore.kernel.org/r/20230118041243.1720520-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Qualcomm adreno/snapdragon MDP5 display controller
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Description:
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This is the bindings documentation for the MDP5 display
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controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
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MDP5:
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Required properties:
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- compatible:
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* "qcom,mdp5" - MDP5
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- reg: Physical base address and length of the controller's registers.
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- reg-names: The names of register regions. The following regions are required:
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* "mdp_phys"
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- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
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- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required.
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- * "bus"
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- * "iface"
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- * "core"
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- * "vsync"
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- ports: contains the list of output ports from MDP. These connect to interfaces
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that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
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special case since it is a part of the MDP block itself).
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Each output port contains an endpoint that describes how it is connected to an
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external interface. These are described by the standard properties documented
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here:
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Documentation/devicetree/bindings/graph.txt
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Documentation/devicetree/bindings/media/video-interfaces.txt
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The availability of output ports can vary across SoC revisions:
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For MSM8974 and APQ8084:
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Port 0 -> MDP_INTF0 (eDP)
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Port 1 -> MDP_INTF1 (DSI1)
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Port 2 -> MDP_INTF2 (DSI2)
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Port 3 -> MDP_INTF3 (HDMI)
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For MSM8916:
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Port 0 -> MDP_INTF1 (DSI1)
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For MSM8994 and MSM8996:
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Port 0 -> MDP_INTF1 (DSI1)
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Port 1 -> MDP_INTF2 (DSI2)
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Port 2 -> MDP_INTF3 (HDMI)
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Optional properties:
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- clock-names: the following clocks are optional:
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* "lut"
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* "tbu"
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* "tbu_rt"
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Example:
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/ {
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...
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mdss: mdss@1a00000 {
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compatible = "qcom,mdss";
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reg = <0x1a00000 0x1000>,
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<0x1ac8000 0x3000>;
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reg-names = "mdss_phys", "vbif_phys";
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power-domains = <&gcc MDSS_GDSC>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"vsync"
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interrupts = <0 72 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mdp: mdp@1a01000 {
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compatible = "qcom,mdp5";
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reg = <0x1a01000 0x90000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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interrupts = <0 0>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_MDP_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"core",
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"vsync";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdp5_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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dsi0: dsi@1a98000 {
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...
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ports {
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...
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&mdp5_intf1_out>;
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};
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};
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...
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};
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...
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};
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dsi_phy0: dsi-phy@1a98300 {
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...
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};
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};
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};
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138
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
Normal file
138
Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml
Normal file
@ -0,0 +1,138 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5)
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description:
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MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994
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and MSM8996.
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- Rob Clark <robdclark@gmail.com>
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properties:
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compatible:
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const: qcom,mdp5
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reg:
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maxItems: 1
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reg-names:
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items:
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- const: mdp_phys
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interrupts:
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maxItems: 1
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clocks:
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minItems: 4
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maxItems: 7
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clock-names:
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oneOf:
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- minItems: 4
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items:
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- const: iface
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- const: bus
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- const: core
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- const: vsync
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- const: lut
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- const: tbu
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- const: tbu_rt
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#MSM8996 has additional iommu clock
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- items:
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- const: iface
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- const: bus
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- const: core
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- const: iommu
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- const: vsync
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interconnects:
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minItems: 1
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items:
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- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
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- description: Interconnect path from mdp1 port to the data bus
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- description: Interconnect path from rotator port to the data bus
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interconnect-names:
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minItems: 1
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items:
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- const: mdp0-mem
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- const: mdp1-mem
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- const: rotator-mem
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iommus:
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items:
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- description: apps SMMU with the Stream-ID mask for Hard-Fail port0
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power-domains:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: >
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Contains the list of output ports from DPU device. These ports
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connect to interfaces that are external to the DPU hardware,
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such as DSI, DP etc. MDP5 devices support up to 4 ports:
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one or two DSI ports, HDMI and eDP.
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patternProperties:
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"^port@[0-3]+$":
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$ref: /schemas/graph.yaml#/properties/port
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# at least one port is required
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required:
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- port@0
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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display-controller@1a01000 {
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compatible = "qcom,mdp5";
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reg = <0x1a01000 0x90000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_MDP_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"core",
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"vsync";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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...
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