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KVM: arm64: Remove __vcpu_{read,write}_sys_reg_{from,to}_cpu()
There is no point having __vcpu_{read,write}_sys_reg_{from,to}_cpu() exposed to the rest of the kernel, as the only callers are in sys_regs.c. Move them where they below, which is another opportunity to simplify things a bit. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250817121926.217900-5-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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3328d17e70
@ -1161,113 +1161,6 @@ u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
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u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
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void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg);
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static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
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{
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/*
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* *** VHE ONLY ***
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*
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* System registers listed in the switch are not saved on every
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* exit from the guest but are only saved on vcpu_put.
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*
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* SYSREGS_ON_CPU *MUST* be checked before using this helper.
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*
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* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
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* should never be listed below, because the guest cannot modify its
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* own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
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* thread when emulating cross-VCPU communication.
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*/
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if (!has_vhe())
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return false;
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switch (reg) {
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case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
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case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
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case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
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case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
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case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
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case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break;
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case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break;
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case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break;
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case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break;
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case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
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case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
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case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
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case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
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case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
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case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
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case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
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case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
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case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
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case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
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case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
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case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
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case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
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case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break;
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case PAR_EL1: *val = read_sysreg_par(); break;
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case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
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case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
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case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
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case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break;
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case SCTLR2_EL1: *val = read_sysreg_s(SYS_SCTLR2_EL12); break;
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default: return false;
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}
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return true;
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}
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static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
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{
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/*
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* *** VHE ONLY ***
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*
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* System registers listed in the switch are not restored on every
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* entry to the guest but are only restored on vcpu_load.
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*
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* SYSREGS_ON_CPU *MUST* be checked before using this helper.
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*
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* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
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* should never be listed below, because the MPIDR should only be set
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* once, before running the VCPU, and never changed later.
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*/
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if (!has_vhe())
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return false;
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switch (reg) {
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case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
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case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
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case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
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case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
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case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
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case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
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case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
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case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
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case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
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case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
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case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
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case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
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case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
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case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
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case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
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case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
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case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
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case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
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case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
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case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
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case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
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case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
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case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
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case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
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case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
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case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
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case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
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case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
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case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
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default: return false;
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}
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return true;
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}
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struct kvm_vm_stat {
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struct kvm_vm_stat_generic generic;
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};
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@ -216,6 +216,82 @@ static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg,
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}
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}
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static u64 read_sr_from_cpu(enum vcpu_sysreg reg)
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{
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u64 val = 0x8badf00d8badf00d;
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switch (reg) {
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case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break;
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case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break;
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case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break;
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case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break;
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case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break;
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case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break;
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case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break;
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case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break;
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case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break;
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case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break;
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case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break;
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case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break;
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case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break;
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case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break;
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case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break;
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case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
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case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break;
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case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
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case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break;
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case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break;
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case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break;
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case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break;
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case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break;
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case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
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case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break;
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case PAR_EL1: val = read_sysreg_par(); break;
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case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break;
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case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break;
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case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
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default: WARN_ON_ONCE(1);
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}
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return val;
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}
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static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val)
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{
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switch (reg) {
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case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
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case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
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case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
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case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
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case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
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case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
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case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
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case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
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case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
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case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
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case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
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case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
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case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
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case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
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case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
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case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
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case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
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case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
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case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
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case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
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case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
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case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
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case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
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case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
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case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
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case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
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case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
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case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
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case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
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default: WARN_ON_ONCE(1);
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}
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}
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u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
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{
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struct sr_loc loc = {};
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@ -246,13 +322,13 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
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if (loc.loc & SR_LOC_LOADED) {
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enum vcpu_sysreg map_reg = reg;
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u64 val = 0x8badf00d8badf00d;
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if (loc.loc & SR_LOC_MAPPED)
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map_reg = loc.map_reg;
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if (!(loc.loc & SR_LOC_XLATED) &&
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__vcpu_read_sys_reg_from_cpu(map_reg, &val)) {
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if (!(loc.loc & SR_LOC_XLATED)) {
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u64 val = read_sr_from_cpu(map_reg);
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if (reg >= __SANITISED_REG_START__)
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val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
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@ -304,7 +380,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg)
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else
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xlated_val = val;
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__vcpu_write_sys_reg_to_cpu(xlated_val, map_reg);
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write_sr_to_cpu(map_reg, xlated_val);
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/*
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* Fall through to write the backing store anyway, which
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