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This is the usual collection of primarily clk driver updates. The big part of

Browse Source 
the diff is all the new Qualcomm clk drivers added for a few SoCs they're
 working on. The other two vendors with significant work this cycle are Renesas
 and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some
 new SoCs while Amlogic is starting a significant refactoring to simplify their
 code.
 
 The core framework gained a pair of helpers to get the 'struct device' or
 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit
 tests were added for these simple helpers as well. Beyond that core change
 there are lots of little fixes throughout the clk drivers for the stuff we see
 every day, wrong clk driver data that affects tree topology or supported
 frequencies, etc. They're not found until the clks are actually used by some
 consumer device driver.
 
 New Drivers:
  - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the
    Qualcomm Milos SoC
  - Camera, display, GPU, and video clock controllers for Qualcomm QCS615
  - Video clock controller driver for Qualcomm SM6350
  - Camera clock controller driver for Qualcomm SC8180X
  - I3C clocks and resets on Renesas RZ/G3E
  - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
    Renesas RZ/V2H(P) and RZ/V2N
  - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
  - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
  - Ethernet clocks and resets on Renesas RZ/G3E
  - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
    (R9A09G087) SoCs
  - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
  - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
    RZ/V2N
 
 Updates:
  - Support atomic PWMs in the PWM clk driver
  - clk_hw_get_dev() and clk_hw_get_of_node() helpers
  - Replace round_rate() with determine_rate() in various clk drivers
  - Convert clk DT bindings to DT schema format for DT validation
  - Various clk driver cleanups and refactorings from static analysis tools and
    possibly real humans
  - A lot of little fixes here and there to things like clk tree topology,
    missing frequencies, flagging clks as critical, etc. The full details are in
    the commits and sub-tree merge logs
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This is the usual collection of primarily clk driver updates.

  The big part of the diff is all the new Qualcomm clk drivers added for
  a few SoCs they're working on. The other two vendors with significant
  work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
  to existing drivers and supports some new SoCs while Amlogic is
  starting a significant refactoring to simplify their code.

  The core framework gained a pair of helpers to get the 'struct device'
  or 'struct device_node' associated with a 'struct clk_hw'. Some
  associated KUnit tests were added for these simple helpers as well.

  Beyond that core change there are lots of little fixes throughout the
  clk drivers for the stuff we see every day, wrong clk driver data that
  affects tree topology or supported frequencies, etc. They're not found
  until the clks are actually used by some consumer device driver.

  New Drivers:
   - Global, display, gpu, video, camera, tcsr, and rpmh clock
     controller for the Qualcomm Milos SoC
   - Camera, display, GPU, and video clock controllers for Qualcomm
     QCS615
   - Video clock controller driver for Qualcomm SM6350
   - Camera clock controller driver for Qualcomm SC8180X
   - I3C clocks and resets on Renesas RZ/G3E
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/V2H(P) and RZ/V2N
   - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
   - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
   - Ethernet clocks and resets on Renesas RZ/G3E
   - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
     (R9A09G087) SoCs
   - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
   - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
     RZ/V2N

  Updates:
   - Support atomic PWMs in the PWM clk driver
   - clk_hw_get_dev() and clk_hw_get_of_node() helpers
   - Replace round_rate() with determine_rate() in various clk drivers
   - Convert clk DT bindings to DT schema format for DT validation
   - Various clk driver cleanups and refactorings from static analysis
     tools and possibly real humans
   - A lot of little fixes here and there to things like clk tree
     topology, missing frequencies, flagging clks as critical, etc"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
  clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
  ...
This commit is contained in:
Linus Torvalds 2025-07-31 13:36:27 -07:00
commit 2d945dde7f
377 changed files with 21971 additions and 6929 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
Documentation/devicetree/bindings/clock/alphascale,acc.txt
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Alphascale Clock Controller
The ACC (Alphascale Clock Controller) is responsible for choosing proper
clock source, setting dividers and clock gates.
Required properties for the ACC node:
- compatible: must be "alphascale,asm9260-clock-controller"
- reg: must contain the ACC register base and size
- #clock-cells : shall be set to 1.
Simple one-cell clock specifier format is used, where the only cell is used
as an index of the clock inside the provider.
It is encouraged to use dt-binding for clock index definitions. SoC specific
dt-binding should be included to the device tree descriptor. For example
Alphascale ASM9260:
#include <dt-bindings/clock/alphascale,asm9260.h>
This binding contains two types of clock providers:
_AHB_ - AHB gate;
_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
All clock specific details can be found in the SoC documentation.
CLKID_AHB_ROM 0
CLKID_AHB_RAM 1
CLKID_AHB_GPIO 2
CLKID_AHB_MAC 3
CLKID_AHB_EMI 4
CLKID_AHB_USB0 5
CLKID_AHB_USB1 6
CLKID_AHB_DMA0 7
CLKID_AHB_DMA1 8
CLKID_AHB_UART0 9
CLKID_AHB_UART1 10
CLKID_AHB_UART2 11
CLKID_AHB_UART3 12
CLKID_AHB_UART4 13
CLKID_AHB_UART5 14
CLKID_AHB_UART6 15
CLKID_AHB_UART7 16
CLKID_AHB_UART8 17
CLKID_AHB_UART9 18
CLKID_AHB_I2S0 19
CLKID_AHB_I2C0 20
CLKID_AHB_I2C1 21
CLKID_AHB_SSP0 22
CLKID_AHB_IOCONFIG 23
CLKID_AHB_WDT 24
CLKID_AHB_CAN0 25
CLKID_AHB_CAN1 26
CLKID_AHB_MPWM 27
CLKID_AHB_SPI0 28
CLKID_AHB_SPI1 29
CLKID_AHB_QEI 30
CLKID_AHB_QUADSPI0 31
CLKID_AHB_CAMIF 32
CLKID_AHB_LCDIF 33
CLKID_AHB_TIMER0 34
CLKID_AHB_TIMER1 35
CLKID_AHB_TIMER2 36
CLKID_AHB_TIMER3 37
CLKID_AHB_IRQ 38
CLKID_AHB_RTC 39
CLKID_AHB_NAND 40
CLKID_AHB_ADC0 41
CLKID_AHB_LED 42
CLKID_AHB_DAC0 43
CLKID_AHB_LCD 44
CLKID_AHB_I2S1 45
CLKID_AHB_MAC1 46
CLKID_SYS_CPU 47
CLKID_SYS_AHB 48
CLKID_SYS_I2S0M 49
CLKID_SYS_I2S0S 50
CLKID_SYS_I2S1M 51
CLKID_SYS_I2S1S 52
CLKID_SYS_UART0 53
CLKID_SYS_UART1 54
CLKID_SYS_UART2 55
CLKID_SYS_UART3 56
CLKID_SYS_UART4 56
CLKID_SYS_UART5 57
CLKID_SYS_UART6 58
CLKID_SYS_UART7 59
CLKID_SYS_UART8 60
CLKID_SYS_UART9 61
CLKID_SYS_SPI0 62
CLKID_SYS_SPI1 63
CLKID_SYS_QUADSPI 64
CLKID_SYS_SSP0 65
CLKID_SYS_NAND 66
CLKID_SYS_TRACE 67
CLKID_SYS_CAMM 68
CLKID_SYS_WDT 69
CLKID_SYS_CLKOUT 70
CLKID_SYS_MAC 71
CLKID_SYS_LCD 72
CLKID_SYS_ADCANA 73
Example of clock consumer with _SYS_ and _AHB_ sinks.
uart4: serial@80010000 {
compatible = "alphascale,asm9260-uart";
reg = <0x80010000 0x4000>;
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
interrupts = <19>;
};
Clock consumer with only one, _AHB_ sink.
timer0: timer@80088000 {
compatible = "alphascale,asm9260-timer";
reg = <0x80088000 0x4000>;
clocks = <&acc CLKID_AHB_TIMER0>;
interrupts = <29>;
};

49
Documentation/devicetree/bindings/clock/alphascale,asm9260-clock-controller.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Alphascale Clock Controller
maintainers:
- Oleksij Rempel <linux@rempel-privat.de>
description: |
The ACC (Alphascale Clock Controller) is responsible for choosing proper
clock source, setting dividers and clock gates.
Simple one-cell clock specifier format is used, where the only cell is used
as an index of the clock inside the provider.
It is encouraged to use dt-binding for clock index definitions. SoC specific
dt-binding should be included to the device tree descriptor. For example
Alphascale ASM9260:
#include <dt-bindings/clock/alphascale,asm9260.h>
This binding contains two types of clock providers:
_AHB_ - AHB gate;
_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
All clock specific details can be found in the SoC documentation.
properties:
compatible:
const: alphascale,asm9260-clock-controller
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false

80
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC device clocks
maintainers:
- Khuong Dinh <khuong@os.amperecomputing.com>
properties:
compatible:
const: apm,xgene-device-clock
reg:
minItems: 1
maxItems: 2
reg-names:
items:
- enum: [ csr-reg, div-reg ]
- const: div-reg
minItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
clock-output-names:
maxItems: 1
clock-names:
maxItems: 1
csr-offset:
description: Offset to the CSR reset register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
csr-mask:
description: CSR reset mask bit
$ref: /schemas/types.yaml#/definitions/uint32
default: 0xf
enable-offset:
description: Offset to the enable register
$ref: /schemas/types.yaml#/definitions/uint32
default: 8
enable-mask:
description: CSR enable mask bit
$ref: /schemas/types.yaml#/definitions/uint32
default: 0xf
divider-offset:
description: Offset to the divider register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
divider-width:
description: Width of the divider register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
divider-shift:
description: Bit shift of the divider register
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
required:
- compatible
- reg
- clocks
- '#clock-cells'
- clock-output-names
additionalProperties: false

50
Documentation/devicetree/bindings/clock/apm,xgene-socpll-clock.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks
maintainers:
- Khuong Dinh <khuong@os.amperecomputing.com>
properties:
compatible:
items:
- enum:
- apm,xgene-pcppll-clock
- apm,xgene-pcppll-v2-clock
- apm,xgene-pmd-clock
- apm,xgene-socpll-clock
- apm,xgene-socpll-v2-clock
reg:
maxItems: 1
reg-names:
items:
- enum: [ csr-reg, div-reg ]
- const: div-reg
minItems: 1
clocks:
maxItems: 1
clock-names:
enum: [ pcppll, socpll ]
"#clock-cells":
const: 1
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- clock-output-names
additionalProperties: false

71
Documentation/devicetree/bindings/clock/armada3700-periph-clock.txt
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* Peripheral Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provide peripheral clocks which are
used as clock source for the peripheral of the SoC.
There are two different blocks associated to north bridge and south
bridge.
The peripheral clock consumer should specify the desired clock by
having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs for Armada 3700 North bridge clocks:
ID Clock name Description
-----------------------------------
0 mmc MMC controller
1 sata_host Sata Host
2 sec_at Security AT
3 sac_dap Security DAP
4 tsecm Security Engine
5 setm_tmx Serial Embedded Trace Module
6 avs Adaptive Voltage Scaling
7 sqf SPI
8 pwm PWM
9 i2c_2 I2C 2
10 i2c_1 I2C 1
11 ddr_phy DDR PHY
12 ddr_fclk DDR F clock
13 trace Trace
14 counter Counter
15 eip97 EIP 97
16 cpu CPU
The following is a list of provided IDs for Armada 3700 South bridge clocks:
ID Clock name Description
-----------------------------------
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
1 gbe-core parent clock for Gigabit Ethernet core
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
7 gbe1-core Gigabit Ethernet core port 1
8 gbe0-core Gigabit Ethernet core port 0
9 gbe-bm Gigabit Ethernet Buffer Manager
10 sdio SDIO
11 usb32-sub2-sys USB 2 clock
12 usb32-ss-sys USB 3 clock
13 pcie PCIe controller
Required properties:
- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
north bridge block, or
"marvell,armada-3700-periph-clock-sb" for the south bridge block
- reg : must be the register address of North/South Bridge Clock register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : list of the parent clock phandle in the following order:
TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
Example:
nb_perih_clk: nb-periph-clk@13000{
compatible = "marvell,armada-3700-periph-clock-nb";
reg = <0x13000 0x1000>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
<&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};

27
Documentation/devicetree/bindings/clock/armada3700-tbg-clock.txt
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* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
used as parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the
clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 3700:
0 = TBG A P
1 = TBG B P
2 = TBG A S
3 = TBG B S
Required properties:
- compatible : shall be "marvell,armada-3700-tbg-clock"
- reg : must be the register address of North Bridge PLL register
- #clock-cells : from common clock binding; shall be set to 1
Example:
tbg: tbg@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x1000>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};

41
Documentation/devicetree/bindings/clock/artpec6.txt
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* Clock bindings for Axis ARTPEC-6 chip
The bindings are based on the clock provider binding in
Documentation/devicetree/bindings/clock/clock-bindings.txt
External clocks:
----------------
There are two external inputs to the main clock controller which should be
provided using the common clock bindings.
- "sys_refclk": External 50 Mhz oscillator (required)
- "i2s_refclk": Alternate audio reference clock (optional).
Main clock controller
---------------------
Required properties:
- #clock-cells: Should be <1>
See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
- compatible: Should be "axis,artpec6-clkctrl"
- reg: Must contain the base address and length of the system controller
- clocks: Must contain a phandle entry for each clock in clock-names
- clock-names: Must include the external oscillator ("sys_refclk"). Optional
ones are the audio reference clock ("i2s_refclk") and the audio fractional
dividers ("frac_clk0" and "frac_clk1").
Examples:
ext_clk: ext_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clkctrl: clkctrl@f8000000 {
#clock-cells = <1>;
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
clocks = <&ext_clk>;
clock-names = "sys_refclk";
};

55
Documentation/devicetree/bindings/clock/axis,artpec6-clkctrl.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/axis,artpec6-clkctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC-6 clock controller
maintainers:
- Lars Persson <lars.persson@axis.com>
properties:
compatible:
const: axis,artpec6-clkctrl
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
minItems: 1
items:
- description: external 50 MHz oscillator.
- description: optional audio reference clock.
- description: fractional audio clock divider 0.
- description: fractional audio clock divider 1.
clock-names:
minItems: 1
items:
- const: sys_refclk
- const: i2s_refclk
- const: frac_clk0
- const: frac_clk1
required:
- compatible
- reg
- "#clock-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller@f8000000 {
compatible = "axis,artpec6-clkctrl";
reg = <0xf8000000 0x48>;
#clock-cells = <1>;
clocks = <&ext_clk>;
clock-names = "sys_refclk";
};

60
Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt
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@ -1,60 +0,0 @@
Broadcom BCM2835 CPRMAN clocks
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
The CPRMAN clock controller generates clocks in the audio power domain
of the BCM2835. There is a level of PLLs deriving from an external
oscillator, a level of PLL dividers that produce channels off of the
few PLLs, and a level of mostly-generic clock generators sourcing from
the PLL channels. Most other hardware components source from the
clock generators, but a few (like the ARM or HDMI) will source from
the PLL dividers directly.
Required properties:
- compatible: should be one of the following,
"brcm,bcm2711-cprman"
"brcm,bcm2835-cprman"
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835.h
- reg: Specifies base physical address and size of the registers
- clocks: phandles to the parent clocks used as input to the module, in
the following order:
- External oscillator
- DSI0 byte clock
- DSI0 DDR2 clock
- DSI0 DDR clock
- DSI1 byte clock
- DSI1 DDR2 clock
- DSI1 DDR clock
Only external oscillator is required. The DSI clocks may
not be present, in which case their children will be
unusable.
Example:
clk_osc: clock@3 {
compatible = "fixed-clock";
reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
clocks = <&clk_osc>;
};
i2c0: i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm2835-cprman.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM2835 CPRMAN clocks
maintainers:
- Stefan Wahren <wahrenst@gmx.net>
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
description:
The CPRMAN clock controller generates clocks in the audio power domain of the
BCM2835. There is a level of PLLs deriving from an external oscillator, a
level of PLL dividers that produce channels off of the few PLLs, and a level
of mostly-generic clock generators sourcing from the PLL channels. Most other
hardware components source from the clock generators, but a few (like the ARM
or HDMI) will source from the PLL dividers directly.
properties:
compatible:
enum:
- brcm,bcm2711-cprman
- brcm,bcm2835-cprman
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
items:
- description: External oscillator clock.
- description: DSI0 byte clock.
- description: DSI0 DDR2 clock.
- description: DSI0 DDR clock.
- description: DSI1 byte clock.
- description: DSI1 DDR2 clock.
- description: DSI1 DDR clock.
additionalProperties: false
required:
- compatible
- '#clock-cells'
- reg
- clocks
examples:
- |
clock-controller@7e101000 {
compatible = "brcm,bcm2835-cprman";
reg = <0x7e101000 0x2000>;
#clock-cells = <1>;
clocks = <&clk_osc>;
};

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Broadcom BCM53573 ILP clock
===========================
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
This binding is used for ILP clock (sometimes referred as "slow clock")
on Broadcom BCM53573 devices using Cortex-A7 CPU.
ILP's rate has to be calculated on runtime and it depends on ALP clock
which has to be referenced.
This clock is part of PMU (Power Management Unit), a Broadcom's device
handing power-related aspects. Its node must be sub-node of the PMU
device.
Required properties:
- compatible: "brcm,bcm53573-ilp"
- clocks: has to reference an ALP clock
- #clock-cells: should be <0>
- clock-output-names: from common clock bindings, should contain clock
name
Example:
pmu@18012000 {
compatible = "simple-mfd", "syscon";
reg = <0x18012000 0x00001000>;
ilp {
compatible = "brcm,bcm53573-ilp";
clocks = <&alp>;
#clock-cells = <0>;
clock-output-names = "ilp";
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm53573-ilp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53573 ILP clock
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
description: >
ILP clock (sometimes referred as "slow clock") on Broadcom BCM53573 devices
using Cortex-A7 CPU.
ILP's rate has to be calculated on runtime and it depends on ALP clock which
has to be referenced.
This clock is part of PMU (Power Management Unit), a Broadcom device handling
power-related aspects. Its node must be sub-node of the PMU device.
properties:
compatible:
items:
- const: brcm,bcm53573-ilp
clocks:
maxItems: 1
'#clock-cells':
const: 0
clock-output-names:
items:
- const: ilp
additionalProperties: false
examples:
- |
ilp {
compatible = "brcm,bcm53573-ilp";
clocks = <&alp>;
#clock-cells = <0>;
clock-output-names = "ilp";
};

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Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
Required properties:
- compatible: must be one of:
"brcm,bcm3368-clocks"
"brcm,bcm6318-clocks"
"brcm,bcm6318-ubus-clocks"
"brcm,bcm6328-clocks"
"brcm,bcm6358-clocks"
"brcm,bcm6362-clocks"
"brcm,bcm6368-clocks"
"brcm,bcm63268-clocks"
- reg: Address and length of the register set
- #clock-cells: must be <1>
Example:
clkctl: clock-controller@10000004 {
compatible = "brcm,bcm6328-clocks";
reg = <0x10000004 0x4>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm63xx-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS based BCM63XX SoCs Gated Clock Controller
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
- Jonas Gorski <jonas.gorski@gmail.com>
properties:
compatible:
enum:
- brcm,bcm3368-clocks
- brcm,bcm6318-clocks
- brcm,bcm6318-ubus-clocks
- brcm,bcm6328-clocks
- brcm,bcm6358-clocks
- brcm,bcm6362-clocks
- brcm,bcm6368-clocks
- brcm,bcm63268-clocks
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@10000004 {
compatible = "brcm,bcm6328-clocks";
reg = <0x10000004 0x4>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/cirrus,ep7209-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cirrus Logic CLPS711X Clock Controller
maintainers:
- Alexander Shiyan <shc_work@mail.ru>
description:
See include/dt-bindings/clock/clps711x-clock.h for the full list of CLPS711X
clock IDs.
properties:
compatible:
items:
- const: cirrus,ep7312-clk
- const: cirrus,ep7209-clk
reg:
maxItems: 1
startup-frequency:
description: Factory set CPU startup frequency in HZ.
$ref: /schemas/types.yaml#/definitions/uint32
"#clock-cells":
const: 1
required:
- compatible
- reg
- startup-frequency
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@80000000 {
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
reg = <0x80000000 0xc000>;
#clock-cells = <1>;
startup-frequency = <73728000>;
};

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* Clock bindings for the Cirrus Logic CLPS711X CPUs
Required properties:
- compatible : Shall contain "cirrus,ep7209-clk".
- reg : Address of the internal register set.
- startup-frequency: Factory set CPU startup frequency in HZ.
- #clock-cells : Should be <1>.
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
for the full list of CLPS711X clock IDs.
Example:
clks: clks@80000000 {
#clock-cells = <1>;
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
reg = <0x80000000 0xc000>;
startup-frequency = <73728000>;
};

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PLL divider based Dove clocks
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
high speed clocks for a number of peripherals. These dividers are part of
the PMU, and thus this node should be a child of the PMU node.
The following clocks are provided:
ID Clock
-------------
0 AXI bus clock
1 GPU clock
2 VMeta clock
3 LCD clock
Required properties:
- compatible : shall be "marvell,dove-divider-clock"
- reg : shall be the register address of the Core PLL and Clock Divider
Control 0 register. This will cover that register, as well as the
Core PLL and Clock Divider Control 1 register. Thus, it will have
a size of 8.
- #clock-cells : from common clock binding; shall be set to 1
divider_clk: core-clock@64 {
compatible = "marvell,dove-divider-clock";
reg = <0x0064 0x8>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Imagination Technologies Pistachio SoC clock controllers
maintainers:
- Andrew Bresticker <abrestic@chromium.org>
description: |
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
general control, and top general control) which are instantiated individually
from the device-tree.
Core clock controller:
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
co-processor), audio, and several peripherals.
Peripheral clock controller:
The peripheral clock controller generates clocks for the DDR, ROM, and other
peripherals. The peripheral system clock ("periph_sys") generated by the core
clock controller is the input clock to the peripheral clock controller.
Peripheral general control:
The peripheral general control block generates system interface clocks and
resets for various peripherals. It also contains miscellaneous peripheral
control registers.
Top-level general control:
The top-level general control block contains miscellaneous control registers
and gates for the external clocks "audio_clk_in" and "enet_clk_in".
properties:
compatible:
items:
- enum:
- img,pistachio-clk
- img,pistachio-clk-periph
- img,pistachio-cr-periph
- img,pistachio-cr-top
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: img,pistachio-clk
then:
properties:
clocks:
items:
- description: External 52Mhz oscillator
- description: Alternate audio reference clock
- description: Alternate ethernet PHY clock
clock-names:
items:
- const: xtal
- const: audio_refclk_ext_gate
- const: ext_enet_in_gate
- if:
properties:
compatible:
contains:
const: img,pistachio-clk-periph
then:
properties:
clocks:
items:
- description: Peripheral system clock
clock-names:
items:
- const: periph_sys_core
- if:
properties:
compatible:
contains:
const: img,pistachio-cr-periph
then:
properties:
clocks:
items:
- description: System interface clock
clock-names:
items:
- const: sys
- if:
properties:
compatible:
contains:
const: img,pistachio-cr-top
then:
properties:
clocks:
items:
- description: External audio reference clock
- description: External ethernet PHY clock
clock-names:
items:
- const: audio_clk_in
- const: enet_clk_in
additionalProperties: false

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* NXP LPC1850 Clock Control Unit (CCU)
Each CGU base clock has several clock branches which can be turned on
or off independently by the Clock Control Units CCU1 or CCU2. The
branch clocks are distributed between CCU1 and CCU2.
- Above text taken from NXP LPC1850 User Manual.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible:
Should be "nxp,lpc1850-ccu"
- reg:
Shall define the base and range of the address space
containing clock control registers
- #clock-cells:
Shall have value <1>. The permitted clock-specifier values
are the branch clock names defined in table below.
- clocks:
Shall contain a list of phandles for the base clocks routed
from the CGU to the specific CCU. See mapping of base clocks
and CCU in table below.
- clock-names:
Shall contain a list of names for the base clock routed
from the CGU to the specific CCU. Valid CCU clock names:
"base_usb0_clk", "base_periph_clk", "base_usb1_clk",
"base_cpu_clk", "base_spifi_clk", "base_spi_clk",
"base_apb1_clk", "base_apb3_clk", "base_adchs_clk",
"base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk",
"base_uart0_clk", "base_uart1_clk", "base_uart2_clk",
"base_uart3_clk", "base_audio_clk"
Which branch clocks that are available on the CCU depends on the
specific LPC part. Check the user manual for your specific part.
A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
Example board file:
soc {
ccu1: clock-controller@40051000 {
compatible = "nxp,lpc1850-ccu";
reg = <0x40051000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
clock-names = "base_apb3_clk", "base_apb1_clk",
"base_spifi_clk", "base_cpu_clk",
"base_periph_clk", "base_usb0_clk",
"base_usb1_clk", "base_spi_clk";
};
ccu2: clock-controller@40052000 {
compatible = "nxp,lpc1850-ccu";
reg = <0x40052000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
clock-names = "base_audio_clk", "base_uart3_clk",
"base_uart2_clk", "base_uart1_clk",
"base_uart0_clk", "base_ssp1_clk",
"base_ssp0_clk", "base_sdio_clk";
};
/* A user of CCU branch clocks */
uart1: serial@40082000 {
...
clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
...
};
};

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* NXP LPC1850 Clock Generation Unit (CGU)
The CGU generates multiple independent clocks for the core and the
peripheral blocks of the LPC18xx. Each independent clock is called
a base clock and itself is one of the inputs to the two Clock
Control Units (CCUs) which control the branch clocks to the
individual peripherals.
The CGU selects the inputs to the clock generators from multiple
clock sources, controls the clock generation, and routes the outputs
of the clock generators through the clock source bus to the output
stages. Each output stage provides an independent clock source and
corresponds to one of the base clocks for the LPC18xx.
- Above text taken from NXP LPC1850 User Manual.
This binding uses the common clock binding:
Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible:
Should be "nxp,lpc1850-cgu"
- reg:
Shall define the base and range of the address space
containing clock control registers
- #clock-cells:
Shall have value <1>. The permitted clock-specifier values
are the base clock numbers defined below.
- clocks:
Shall contain a list of phandles for the external input
sources to the CGU. The list shall be in the following
order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
- clock-indices:
Shall be an ordered list of numbers defining the base clock
number provided by the CGU.
- clock-output-names:
Shall be an ordered list of strings defining the names of
the clocks provided by the CGU.
Which base clocks that are available on the CGU depends on the
specific LPC part. Base clocks are numbered from 0 to 27.
Number: Name: Description:
0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
1 BASE_USB0_CLK Base clock for USB0
2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
SPI, and SGPIO
3 BASE_USB1_CLK Base clock for USB1
4 BASE_CPU_CLK System base clock for ARM Cortex-M core
and APB peripheral blocks #0 and #2
5 BASE_SPIFI_CLK Base clock for SPIFI
6 BASE_SPI_CLK Base clock for SPI
7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
9 BASE_APB1_CLK Base clock for APB peripheral block # 1
10 BASE_APB3_CLK Base clock for APB peripheral block # 3
11 BASE_LCD_CLK Base clock for LCD
12 BASE_ADCHS_CLK Base clock for ADCHS
13 BASE_SDIO_CLK Base clock for SD/MMC
14 BASE_SSP0_CLK Base clock for SSP0
15 BASE_SSP1_CLK Base clock for SSP1
16 BASE_UART0_CLK Base clock for UART0
17 BASE_UART1_CLK Base clock for UART1
18 BASE_UART2_CLK Base clock for UART2
19 BASE_UART3_CLK Base clock for UART3
20 BASE_OUT_CLK Base clock for CLKOUT pin
24-21 - Reserved
25 BASE_AUDIO_CLK Base clock for audio system (I2S)
26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
BASE_ADCHS_CLK is only available on LPC4370.
Example board file:
/ {
clocks {
xtal: xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
xtal32: xtal32 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
enet_rx_clk: enet_rx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "enet_rx_clk";
};
enet_tx_clk: enet_tx_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "enet_tx_clk";
};
gp_clkin: gp_clkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
clock-output-names = "gp_clkin";
};
};
soc {
cgu: clock-controller@40050000 {
compatible = "nxp,lpc1850-cgu";
reg = <0x40050000 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
};
/* A CGU and CCU clock consumer */
lcdc: lcdc@40008000 {
...
clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
clock-names = "clcdclk", "apb_pclk";
...
};
};
};

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AXM5516 clock driver bindings
-----------------------------
Required properties :
- compatible : shall contain "lsi,axm5516-clks"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
The consumer specifies the desired clock by having the clock ID in its "clocks"
phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
supported clock IDs.
Example:
clks: clock-controller@2010020000 {
compatible = "lsi,axm5516-clks";
#clock-cells = <1>;
reg = <0x20 0x10020000 0 0x20000>;
};
serial0: uart@2010080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20 0x10080000 0 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks AXXIA_CLK_PER>;
clock-names = "apb_pclk";
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2025 LSI
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/lsi,axm5516-clks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LSI AXM5516 Clock Controller
maintainers:
- Anders Berg <anders.berg@lsi.com>
description:
See <dt-bindings/clock/lsi,axxia-clock.h> for the list of supported clock IDs.
properties:
compatible:
const: lsi,axm5516-clks
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <1>;
clock-controller@2010020000 {
compatible = "lsi,axm5516-clks";
#clock-cells = <1>;
reg = <0x20 0x10020000 0x20000>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/lsi,nspire-cx-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI-NSPIRE Clocks
maintainers:
- Daniel Tang <dt.tangr@gmail.com>
properties:
compatible:
enum:
- lsi,nspire-cx-ahb-divider
- lsi,nspire-classic-ahb-divider
- lsi,nspire-cx-clock
- lsi,nspire-classic-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 0
additionalProperties: false
required:
- compatible
- reg

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/marvell,armada-370-corediv-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU Core Divider Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
oneOf:
- enum:
- marvell,armada-370-corediv-clock
- marvell,armada-375-corediv-clock
- marvell,armada-380-corediv-clock
- marvell,mv98dx3236-corediv-clock
- items:
- const: marvell,armada-390-corediv-clock
- const: marvell,armada-380-corediv-clock
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
- clocks
additionalProperties: false
examples:
- |
clock-controller@18740 {
compatible = "marvell,armada-370-corediv-clock";
reg = <0x18740 0xc>;
#clock-cells = <1>;
clocks = <&pll>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 37xx SoCs Peripheral Clocks
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Armada 37xx SoCs provide peripheral clocks which are used as clock
source for the peripheral of the SoC.
There are two different blocks associated to north bridge and south bridge.
The following is a list of provided IDs for Armada 3700 North bridge clocks:
ID Clock name Description
-----------------------------------
0 mmc MMC controller
1 sata_host Sata Host
2 sec_at Security AT
3 sac_dap Security DAP
4 tsecm Security Engine
5 setm_tmx Serial Embedded Trace Module
6 avs Adaptive Voltage Scaling
7 sqf SPI
8 pwm PWM
9 i2c_2 I2C 2
10 i2c_1 I2C 1
11 ddr_phy DDR PHY
12 ddr_fclk DDR F clock
13 trace Trace
14 counter Counter
15 eip97 EIP 97
16 cpu CPU
The following is a list of provided IDs for Armada 3700 South bridge clocks:
ID Clock name Description
-----------------------------------
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
1 gbe-core parent clock for Gigabit Ethernet core
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
7 gbe1-core Gigabit Ethernet core port 1
8 gbe0-core Gigabit Ethernet core port 0
9 gbe-bm Gigabit Ethernet Buffer Manager
10 sdio SDIO
11 usb32-sub2-sys USB 2 clock
12 usb32-ss-sys USB 3 clock
13 pcie PCIe controller
properties:
compatible:
oneOf:
- const: marvell,armada-3700-periph-clock-sb
- items:
- const: marvell,armada-3700-periph-clock-nb
- const: syscon
reg:
maxItems: 1
clocks:
items:
- description: TBG-A P clock and specifier
- description: TBG-B P clock and specifier
- description: TBG-A S clock and specifier
- description: TBG-B S clock and specifier
- description: Xtal clock and specifier
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@13000{
compatible = "marvell,armada-3700-periph-clock-sb";
reg = <0x13000 0x1000>;
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,armada-3700-tbg-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada 3700 Time Base Generator Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Armada 37xx SoCs provide Time Base Generator clocks which are used as
parent clocks for the peripheral clocks.
The TBG clock consumer should specify the desired clock by having the clock ID
in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 3700:
0 = TBG A P
1 = TBG B P
2 = TBG A S
3 = TBG B S
properties:
compatible:
const: marvell,armada-3700-tbg-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@13200 {
compatible = "marvell,armada-3700-tbg-clock";
reg = <0x13200 0x1000>;
clocks = <&xtalclk>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$schema: http://devicetree.org/meta-schemas/core.yaml#
$id: http://devicetree.org/schemas/clock/marvell,armada-xp-cpu-clock.yaml#
title: Marvell EBU CPU Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
properties:
compatible:
enum:
- marvell,armada-xp-cpu-clock
- marvell,mv98dx3236-cpu-clock
reg:
items:
- description: Clock complex registers
- description: PMU DFS registers
'#clock-cells':
const: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
clock-controller@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xa0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
};

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Device Tree Clock bindings for Marvell Berlin
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Clock related registers are spread among the chip control registers. Berlin
clock node should be a sub-node of the chip controller node. Marvell Berlin2
(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
minor differences in features and register layout.
Required properties:
- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
- #clock-cells: must be 1
- clocks: must be the input parent clock phandle
- clock-names: name of the input parent clock
Allowed clock-names for the reference clocks are
"refclk" for the SoCs oscillator input on all SoCs,
and SoC-specific input clocks for
BG2/BG2CD: "video_ext0" for the external video clock input
Example:
chip_clk: clock {
compatible = "marvell,berlin2q-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,berlin2-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Berlin Clock Controller
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
description:
Clock related registers are spread among the chip control registers. Berlin
clock node should be a sub-node of the chip controller node. Marvell Berlin2
(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some minor
differences in features and register layout.
properties:
compatible:
enum:
- marvell,berlin2-clk
- marvell,berlin2q-clk
'#clock-cells':
const: 1
clocks:
maxItems: 1
clock-names:
items:
- enum:
- refclk
- video_ext0
required:
- compatible
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller {
compatible = "marvell,berlin2q-clk";
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/marvell,dove-divider-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Dove PLL Divider Clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
high speed clocks for a number of peripherals. These dividers are part of the
PMU, and thus this node should be a child of the PMU node.
The following clocks are provided:
ID Clock
-------------
0 AXI bus clock
1 GPU clock
2 VMeta clock
3 LCD clock
properties:
compatible:
const: marvell,dove-divider-clock
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@64 {
compatible = "marvell,dove-divider-clock";
reg = <0x0064 0x8>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,mvebu-core-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MVEBU SoC core clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell MVEBU SoCs usually allow to determine core clock frequencies by
reading the Sample-At-Reset (SAR) register. The core clock consumer should
specify the desired clock by having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 370/XP:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (L2 Cache clock)
3 = hclk (DRAM control clock)
4 = dramclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 375:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 380/385:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 39x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (Coherent Fabric clock)
3 = hclk (SDRAM Controller Internal Clock)
4 = dclk (SDRAM Interface Clock)
5 = refclk (Reference Clock)
The following is a list of provided IDs and clock names on 98dx3236:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = ddrclk (DDR clock)
3 = mpll (MPLL Clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = l2clk (L2 Cache clock derived from CPU0 clock)
3 = ddrclk (DDR controller clock derived from CPU0 clock)
The following is a list of provided IDs and clock names on Orion5x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = ddrclk (DDR controller clock derived from CPU0 clock)
properties:
compatible:
enum:
- marvell,armada-370-core-clock
- marvell,armada-375-core-clock
- marvell,armada-380-core-clock
- marvell,armada-390-core-clock
- marvell,armada-xp-core-clock
- marvell,dove-core-clock
- marvell,kirkwood-core-clock
- marvell,mv88f5181-core-clock
- marvell,mv88f5182-core-clock
- marvell,mv88f5281-core-clock
- marvell,mv88f6180-core-clock
- marvell,mv88f6183-core-clock
- marvell,mv98dx1135-core-clock
- marvell,mv98dx3236-core-clock
reg:
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
description: Overwrite default clock output names.
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
---
$id: http://devicetree.org/schemas/clock/marvell-armada-370-gating-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell EBU SoC gating-clock
maintainers:
- Andrew Lunn <andrew@lunn.ch>
- Gregory Clement <gregory.clement@bootlin.com>
description: >
Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some peripheral
clocks to be gated to save some power. The clock ID is directly mapped to the
corresponding clock gating control bit in HW to ease manual clock lookup in
datasheet.
The following is a list of provided IDs for Armada 370:
ID Clock Peripheral
-----------------------------------
0 Audio AC97 Cntrl
1 pex0_en PCIe 0 Clock out
2 pex1_en PCIe 1 Clock out
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
9 pex1 PCIe Cntrl 1
15 sata0 SATA Host 0
17 sdio SDHCI Host
23 crypto CESA (crypto engine)
25 tdm Time Division Mplx
28 ddr DDR Cntrl
30 sata1 SATA Host 0
The following is a list of provided IDs for Armada 375:
ID Clock Peripheral
-----------------------------------
2 mu Management Unit
3 pp Packet Processor
4 ptp PTP
5 pex0 PCIe 0 Clock out
6 pex1 PCIe 1 Clock out
8 audio Audio Cntrl
11 nd_clk Nand Flash Cntrl
14 sata0_link SATA 0 Link
15 sata0_core SATA 0 Core
16 usb3 USB3 Host
17 sdio SDHCI Host
18 usb USB Host
19 gop Gigabit Ethernet MAC
20 sata1_link SATA 1 Link
21 sata1_core SATA 1 Core
22 xor0 XOR DMA 0
23 xor1 XOR DMA 0
24 copro Coprocessor
25 tdm Time Division Mplx
28 crypto0_enc Cryptographic Unit Port 0 Encryption
29 crypto0_core Cryptographic Unit Port 0 Core
30 crypto1_enc Cryptographic Unit Port 1 Encryption
31 crypto1_core Cryptographic Unit Port 1 Core
The following is a list of provided IDs for Armada 380/385:
ID Clock Peripheral
-----------------------------------
0 audio Audio
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
11 usb3d USB3 Device
13 bm Buffer Management
14 crypto0z Cryptographic 0 Z
15 sata0 SATA 0
16 crypto1z Cryptographic 1 Z
17 sdio SDIO
18 usb2 USB 2
21 crypto1 Cryptographic 1
22 xor0 XOR 0
23 crypto0 Cryptographic 0
25 tdm Time Division Multiplexing
28 xor1 XOR 1
30 sata1 SATA 1
The following is a list of provided IDs for Armada 39x:
ID Clock Peripheral
-----------------------------------
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
15 sata0 SATA 0
17 sdio SDIO
22 xor0 XOR 0
28 xor1 XOR 1
The following is a list of provided IDs for Armada XP:
ID Clock Peripheral
-----------------------------------
0 audio Audio Cntrl
1 ge3 Gigabit Ethernet 3
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
6 pex1 PCIe Cntrl 1
7 pex2 PCIe Cntrl 2
8 pex3 PCIe Cntrl 3
13 bp
14 sata0lnk
15 sata0 SATA Host 0
16 lcd LCD Cntrl
17 sdio SDHCI Host
18 usb0 USB Host 0
19 usb1 USB Host 1
20 usb2 USB Host 2
22 xor0 XOR DMA 0
23 crypto CESA engine
25 tdm Time Division Mplx
28 xor1 XOR DMA 1
29 sata1lnk
30 sata1 SATA Host 1
The following is a list of provided IDs for 98dx3236:
ID Clock Peripheral
-----------------------------------
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
17 sdio SDHCI Host
18 usb0 USB Host 0
22 xor0 XOR DMA 0
The following is a list of provided IDs for Dove:
ID Clock Peripheral
-----------------------------------
0 usb0 USB Host 0
1 usb1 USB Host 1
2 ge Gigabit Ethernet
3 sata SATA Host
4 pex0 PCIe Cntrl 0
5 pex1 PCIe Cntrl 1
8 sdio0 SDHCI Host 0
9 sdio1 SDHCI Host 1
10 nand NAND Cntrl
11 camera Camera Cntrl
12 i2s0 I2S Cntrl 0
13 i2s1 I2S Cntrl 1
15 crypto CESA engine
21 ac97 AC97 Cntrl
22 pdma Peripheral DMA
23 xor0 XOR DMA 0
24 xor1 XOR DMA 1
30 gephy Gigabit Ethernet PHY
Note: gephy(30) is implemented as a parent clock of ge(2)
The following is a list of provided IDs for Kirkwood:
ID Clock Peripheral
-----------------------------------
0 ge0 Gigabit Ethernet 0
2 pex0 PCIe Cntrl 0
3 usb0 USB Host 0
4 sdio SDIO Cntrl
5 tsu Transp. Stream Unit
6 dunit SDRAM Cntrl
7 runit Runit
8 xor0 XOR DMA 0
9 audio I2S Cntrl 0
14 sata0 SATA Host 0
15 sata1 SATA Host 1
16 xor1 XOR DMA 1
17 crypto CESA engine
18 pex1 PCIe Cntrl 1
19 ge1 Gigabit Ethernet 1
20 tdm Time Division Mplx
properties:
compatible:
enum:
- marvell,armada-370-gating-clock
- marvell,armada-375-gating-clock
- marvell,armada-380-gating-clock
- marvell,armada-390-gating-clock
- marvell,armada-xp-gating-clock
- marvell,mv98dx3236-gating-clock
- marvell,dove-gating-clock
- marvell,kirkwood-gating-clock
reg:
maxItems: 1
clocks:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@d0038 {
compatible = "marvell,dove-gating-clock";
reg = <0xd0038 0x4>;
/* default parent clock is tclk */
clocks = <&core_clk 0>;
#clock-cells = <1>;
};

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Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
This device exposes 4 clocks in total:
- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
frequencies
- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
requests.
Required properties:
- compatible: "maxim,max9485"
- clocks: Input clock, must provide 27.000 MHz
- clock-names: Must be set to "xclk"
- #clock-cells: From common clock binding; shall be set to 1
Optional properties:
- reset-gpios: GPIO descriptor connected to the #RESET input pin
- vdd-supply: A regulator node for Vdd
- clock-output-names: Name of output clocks, as defined in common clock
bindings
If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
and "clkout2".
Clocks are defined as preprocessor macros in the dt-binding header.
Example:
#include <dt-bindings/clock/maxim,max9485.h>
xo-27mhz: xo-27mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
&i2c0 {
max9485: audio-clock@63 {
reg = <0x63>;
compatible = "maxim,max9485";
clock-names = "xclk";
clocks = <&xo-27mhz>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
vdd-supply = <&3v3-reg>;
#clock-cells = <1>;
};
};
// Clock consumer node
foo@0 {
compatible = "bar,foo";
/* ... */
clock-names = "foo-input-clk";
clocks = <&max9485 MAX9485_CLKOUT1>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/maxim,max9485.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim MAX9485 Programmable Audio Clock Generator
maintainers:
- Daniel Mack <daniel@zonque.org>
description: >
Maxim MAX9485 Programmable Audio Clock Generator exposes 4 clocks in total:
- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete
frequencies
- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
requests.
properties:
compatible:
const: maxim,max9485
reg:
maxItems: 1
clocks:
description: Input clock. Must provide 27 MHz
maxItems: 1
clock-names:
items:
- const: xclk
'#clock-cells':
const: 1
reset-gpios:
description: >
GPIO descriptor connected to the #RESET input pin
vdd-supply:
description: A regulator node for Vdd
clock-output-names:
description: Name of output clocks, as defined in common clock bindings
items:
- const: mclkout
- const: clkout
- const: clkout1
- const: clkout2
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-controller@63 {
compatible = "maxim,max9485";
reg = <0x63>;
#clock-cells = <1>;
clock-names = "xclk";
clocks = <&xo_27mhz>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
vdd-supply = <&reg_3v3>;
};
};

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Microchip PIC32 Clock Controller Binding
----------------------------------------
Microchip clock controller is consists of few oscillators, PLL, multiplexer
and few divider modules.
This binding uses common clock bindings.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible: shall be "microchip,pic32mzda-clk".
- reg: shall contain base address and length of clock registers.
- #clock-cells: shall be 1.
Optional properties:
- microchip,pic32mzda-sosc: shall be added only if platform has
secondary oscillator connected.
Example:
rootclk: clock-controller@1f801200 {
compatible = "microchip,pic32mzda-clk";
reg = <0x1f801200 0x200>;
#clock-cells = <1>;
/* optional */
microchip,pic32mzda-sosc;
};
The clock consumer shall specify the desired clock-output of the clock
controller (as defined in [2]) by specifying output-id in its "clock"
phandle cell.
[2] include/dt-bindings/clock/microchip,pic32-clock.h
For example for UART2:
uart2: serial@2 {
compatible = "microchip,pic32mzda-uart";
reg = <>;
interrupts = <>;
clocks = <&rootclk PB2CLK>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/microchip,pic32mzda-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIC32MZDA Clock Controller
maintainers:
- Purna Chandra Mandal <purna.mandal@microchip.com>
description:
Microchip clock controller consists of a few oscillators, PLL, multiplexer
and divider modules.
properties:
compatible:
const: microchip,pic32mzda-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
microchip,pic32mzda-sosc:
description: Presence of secondary oscillator.
type: boolean
required:
- compatible
- reg
- "#clock-cells"
additionalProperties: false
examples:
- |
clock-controller@1f801200 {
compatible = "microchip,pic32mzda-clk";
reg = <0x1f801200 0x200>;
#clock-cells = <1>;
/* optional */
microchip,pic32mzda-sosc;
};

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Device Tree Clock bindings for arch-moxart
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
MOXA ART SoCs allow to determine PLL output and APB frequencies
by reading registers holding multiplier and divisor information.
PLL:
Required properties:
- compatible : Must be "moxa,moxart-pll-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock
Optional properties:
- clock-output-names : Should contain clock name
APB:
Required properties:
- compatible : Must be "moxa,moxart-apb-clock"
- #clock-cells : Should be 0
- reg : Should contain registers location and length
- clocks : Should contain phandle + clock-specifier for the parent clock
Optional properties:
- clock-output-names : Should contain clock name
For example:
clk_pll: clk_pll@98100000 {
compatible = "moxa,moxart-pll-clock";
#clock-cells = <0>;
reg = <0x98100000 0x34>;
};
clk_apb: clk_apb@98100000 {
compatible = "moxa,moxart-apb-clock";
#clock-cells = <0>;
reg = <0x98100000 0x34>;
clocks = <&clk_pll>;
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/moxa,moxart-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MOXA ART Clock Controllers
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description:
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading
registers holding multiplier and divisor information.
properties:
compatible:
enum:
- moxa,moxart-apb-clock
- moxa,moxart-pll-clock
"#clock-cells":
const: 0
reg:
maxItems: 1
clocks:
maxItems: 1
clock-output-names: true
additionalProperties: false
required:
- compatible
- "#clock-cells"
- reg

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* Core Clock bindings for Marvell MVEBU SoCs
Marvell MVEBU SoCs usually allow to determine core clock frequencies by
reading the Sample-At-Reset (SAR) register. The core clock consumer should
specify the desired clock by having the clock ID in its "clocks" phandle cell.
The following is a list of provided IDs and clock names on Armada 370/XP:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (L2 Cache clock)
3 = hclk (DRAM control clock)
4 = dramclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 375:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 380/385:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = l2clk (L2 Cache clock)
3 = ddrclk (DDR clock)
The following is a list of provided IDs and clock names on Armada 39x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = nbclk (Coherent Fabric clock)
3 = hclk (SDRAM Controller Internal Clock)
4 = dclk (SDRAM Interface Clock)
5 = refclk (Reference Clock)
The following is a list of provided IDs and clock names on 98dx3236:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU clock)
2 = ddrclk (DDR clock)
3 = mpll (MPLL Clock)
The following is a list of provided IDs and clock names on Kirkwood and Dove:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = l2clk (L2 Cache clock derived from CPU0 clock)
3 = ddrclk (DDR controller clock derived from CPU0 clock)
The following is a list of provided IDs and clock names on Orion5x:
0 = tclk (Internal Bus clock)
1 = cpuclk (CPU0 clock)
2 = ddrclk (DDR controller clock derived from CPU0 clock)
Required properties:
- compatible : shall be one of the following:
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
"marvell,dove-core-clock" - for Dove SoC core clocks
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
"marvell,mv98dx1135-core-clock" - for Kirkwood 98dx1135 SoC
"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
- reg : shall be the register address of the Sample-At-Reset (SAR) register
- #clock-cells : from common clock binding; shall be set to 1
Optional properties:
- clock-output-names : from common clock binding; allows overwrite default clock
output names ("tclk", "cpuclk", "l2clk", "ddrclk")
Example:
core_clk: core-clocks@d0214 {
compatible = "marvell,dove-core-clock";
reg = <0xd0214 0x4>;
#clock-cells = <1>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
/* ... */
/* get tclk from core clock provider */
clocks = <&core_clk 0>;
};

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* Core Divider Clock bindings for Marvell MVEBU SoCs
The following is a list of provided IDs and clock names on Armada 370/XP:
0 = nand (NAND clock)
Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
"marvell,mv98dx3236-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
- clocks : must be set to the parent's phandle
Example:
corediv_clk: corediv-clocks@18740 {
compatible = "marvell,armada-370-corediv-clock";
reg = <0x18740 0xc>;
#clock-cells = <1>;
clocks = <&pll>;
};

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Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
"marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.
cpuclk: clock-complex@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
}
cpu@0 {
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};

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* Gated Clock bindings for Marvell EBU SoCs
Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
peripheral clocks to be gated to save some power. The clock consumer
should specify the desired clock by having the clock ID in its
"clocks" phandle cell. The clock ID is directly mapped to the
corresponding clock gating control bit in HW to ease manual clock
lookup in datasheet.
The following is a list of provided IDs for Armada 370:
ID Clock Peripheral
-----------------------------------
0 Audio AC97 Cntrl
1 pex0_en PCIe 0 Clock out
2 pex1_en PCIe 1 Clock out
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
9 pex1 PCIe Cntrl 1
15 sata0 SATA Host 0
17 sdio SDHCI Host
23 crypto CESA (crypto engine)
25 tdm Time Division Mplx
28 ddr DDR Cntrl
30 sata1 SATA Host 0
The following is a list of provided IDs for Armada 375:
ID Clock Peripheral
-----------------------------------
2 mu Management Unit
3 pp Packet Processor
4 ptp PTP
5 pex0 PCIe 0 Clock out
6 pex1 PCIe 1 Clock out
8 audio Audio Cntrl
11 nd_clk Nand Flash Cntrl
14 sata0_link SATA 0 Link
15 sata0_core SATA 0 Core
16 usb3 USB3 Host
17 sdio SDHCI Host
18 usb USB Host
19 gop Gigabit Ethernet MAC
20 sata1_link SATA 1 Link
21 sata1_core SATA 1 Core
22 xor0 XOR DMA 0
23 xor1 XOR DMA 0
24 copro Coprocessor
25 tdm Time Division Mplx
28 crypto0_enc Cryptographic Unit Port 0 Encryption
29 crypto0_core Cryptographic Unit Port 0 Core
30 crypto1_enc Cryptographic Unit Port 1 Encryption
31 crypto1_core Cryptographic Unit Port 1 Core
The following is a list of provided IDs for Armada 380/385:
ID Clock Peripheral
-----------------------------------
0 audio Audio
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
11 usb3d USB3 Device
13 bm Buffer Management
14 crypto0z Cryptographic 0 Z
15 sata0 SATA 0
16 crypto1z Cryptographic 1 Z
17 sdio SDIO
18 usb2 USB 2
21 crypto1 Cryptographic 1
22 xor0 XOR 0
23 crypto0 Cryptographic 0
25 tdm Time Division Multiplexing
28 xor1 XOR 1
30 sata1 SATA 1
The following is a list of provided IDs for Armada 39x:
ID Clock Peripheral
-----------------------------------
5 pex1 PCIe 1
6 pex2 PCIe 2
7 pex3 PCIe 3
8 pex0 PCIe 0
9 usb3h0 USB3 Host 0
10 usb3h1 USB3 Host 1
15 sata0 SATA 0
17 sdio SDIO
22 xor0 XOR 0
28 xor1 XOR 1
The following is a list of provided IDs for Armada XP:
ID Clock Peripheral
-----------------------------------
0 audio Audio Cntrl
1 ge3 Gigabit Ethernet 3
2 ge2 Gigabit Ethernet 2
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
6 pex1 PCIe Cntrl 1
7 pex2 PCIe Cntrl 2
8 pex3 PCIe Cntrl 3
13 bp
14 sata0lnk
15 sata0 SATA Host 0
16 lcd LCD Cntrl
17 sdio SDHCI Host
18 usb0 USB Host 0
19 usb1 USB Host 1
20 usb2 USB Host 2
22 xor0 XOR DMA 0
23 crypto CESA engine
25 tdm Time Division Mplx
28 xor1 XOR DMA 1
29 sata1lnk
30 sata1 SATA Host 1
The following is a list of provided IDs for 98dx3236:
ID Clock Peripheral
-----------------------------------
3 ge1 Gigabit Ethernet 1
4 ge0 Gigabit Ethernet 0
5 pex0 PCIe Cntrl 0
17 sdio SDHCI Host
18 usb0 USB Host 0
22 xor0 XOR DMA 0
The following is a list of provided IDs for Dove:
ID Clock Peripheral
-----------------------------------
0 usb0 USB Host 0
1 usb1 USB Host 1
2 ge Gigabit Ethernet
3 sata SATA Host
4 pex0 PCIe Cntrl 0
5 pex1 PCIe Cntrl 1
8 sdio0 SDHCI Host 0
9 sdio1 SDHCI Host 1
10 nand NAND Cntrl
11 camera Camera Cntrl
12 i2s0 I2S Cntrl 0
13 i2s1 I2S Cntrl 1
15 crypto CESA engine
21 ac97 AC97 Cntrl
22 pdma Peripheral DMA
23 xor0 XOR DMA 0
24 xor1 XOR DMA 1
30 gephy Gigabit Ethernel PHY
Note: gephy(30) is implemented as a parent clock of ge(2)
The following is a list of provided IDs for Kirkwood:
ID Clock Peripheral
-----------------------------------
0 ge0 Gigabit Ethernet 0
2 pex0 PCIe Cntrl 0
3 usb0 USB Host 0
4 sdio SDIO Cntrl
5 tsu Transp. Stream Unit
6 dunit SDRAM Cntrl
7 runit Runit
8 xor0 XOR DMA 0
9 audio I2S Cntrl 0
14 sata0 SATA Host 0
15 sata1 SATA Host 1
16 xor1 XOR DMA 1
17 crypto CESA engine
18 pex1 PCIe Cntrl 1
19 ge1 Gigabit Ethernet 1
20 tdm Time Division Mplx
Required properties:
- compatible : shall be one of the following:
"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
"marvell,dove-gating-clock" - for Dove SoC clock gating
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
- reg : shall be the register address of the Clock Gating Control register
- #clock-cells : from common clock binding; shall be set to 1
Optional properties:
- clocks : default parent clock phandle (e.g. tclk)
Example:
gate_clk: clock-gating-control@d0038 {
compatible = "marvell,dove-gating-clock";
reg = <0xd0038 0x4>;
/* default parent clock is tclk */
clocks = <&core_clk 0>;
#clock-cells = <1>;
};
sdio0: sdio@92000 {
compatible = "marvell,dove-sdhci";
/* get clk gate bit 8 (sdio0) */
clocks = <&gate_clk 8>;
};

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TI-NSPIRE Clocks
Required properties:
- compatible: Valid compatible properties include:
"lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
"lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
"lsi,nspire-cx-clock" for the base clock in the CX model
"lsi,nspire-classic-clock" for the base clock in the older model
- reg: Physical base address of the controller and length of memory mapped
region.
Optional:
- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
clock where it divides the rate from.
Example:
ahb_clk {
#clock-cells = <0>;
compatible = "lsi,nspire-cx-clock";
reg = <0x900B0000 0x4>;
clocks = <&base_clk>;
};

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* Nuvoton NPCM7XX Clock Controller
Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.
External clocks:
There are six fixed clocks that are generated outside the BMC. All clocks are of
a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
clk_sysbypck are inputs to the clock controller.
clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
network. They are set on the device tree, but not used by the clock module. The
network devices use them directly.
Example can be found below.
All available clocks are defined as preprocessor macros in:
dt-bindings/clock/nuvoton,npcm7xx-clock.h
and can be reused as DT sources.
Required Properties of clock controller:
- compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
Poleg BMC NPCM750
- reg: physical base address of the clock controller and length of
memory mapped region.
- #clock-cells: should be 1.
Example: Clock controller node:
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk";
#clock-cells = <1>;
reg = <0xf0801000 0x1000>;
clock-names = "refclk", "sysbypck", "mcbypck";
clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
};
Example: Required external clocks for network:
/* external reference clock */
clk_refclk: clk-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "refclk";
};
/* external reference clock for cpu. float in normal operation */
clk_sysbypck: clk-sysbypck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <800000000>;
clock-output-names = "sysbypck";
};
/* external reference clock for MC. float in normal operation */
clk_mcbypck: clk-mcbypck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <800000000>;
clock-output-names = "mcbypck";
};
/* external clock signal rg1refck, supplied by the phy */
clk_rg1refck: clk-rg1refck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "clk_rg1refck";
};
/* external clock signal rg2refck, supplied by the phy */
clk_rg2refck: clk-rg2refck {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "clk_rg2refck";
};
clk_xin: clk-xin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "clk_xin";
};
Example: GMAC controller node that consumes two clocks: a generated clk by the
clock controller and a fixed clock from DT (clk_rg1refck).
ethernet0: ethernet@f0802000 {
compatible = "snps,dwmac";
reg = <0xf0802000 0x2000>;
interrupts = <0 14 4>;
interrupt-names = "macirq";
clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
clock-names = "stmmaceth", "clk_gmac";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,npcm750-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton NPCM7XX Clock Controller
maintainers:
- Tali Perry <tali.perry1@gmail.com>
description: >
Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
generates and supplies clocks to all modules within the BMC.
External clocks:
There are six fixed clocks that are generated outside the BMC. All clocks are of
a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
clk_sysbypck are inputs to the clock controller.
clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the
network. They are set on the device tree, but not used by the clock module. The
network devices use them directly.
All available clocks are defined as preprocessor macros in:
dt-bindings/clock/nuvoton,npcm7xx-clock.h
and can be reused as DT sources.
properties:
compatible:
const: nuvoton,npcm750-clk
reg:
maxItems: 1
'#clock-cells':
const: 1
clock-names:
items:
- const: refclk
- const: sysbypck
- const: mcbypck
clocks:
items:
- description: refclk
- description: sysbypck
- description: mcbypck
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@f0801000 {
compatible = "nuvoton,npcm750-clk";
#clock-cells = <1>;
reg = <0xf0801000 0x1000>;
clock-names = "refclk", "sysbypck", "mcbypck";
clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
};

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compatible:
items:
- enum:
- nxp,imx94-display-csr
- nxp,imx94-lvds-csr
- nxp,imx95-camera-csr
- nxp,imx95-display-csr
- nxp,imx95-hsio-blk-ctl

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,lpc1850-ccu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC1850 Clock Control Unit (CCU)
description:
Each CGU base clock has several clock branches which can be turned on
or off independently by the Clock Control Units CCU1 or CCU2. The
branch clocks are distributed between CCU1 and CCU2.
Above text taken from NXP LPC1850 User Manual
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc1850-ccu
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 8
clock-names:
minItems: 1
maxItems: 8
items:
enum:
- base_usb0_clk
- base_periph_clk
- base_usb1_clk
- base_cpu_clk
- base_spifi_clk
- base_spi_clk
- base_apb1_clk
- base_apb3_clk
- base_adchs_clk
- base_sdio_clk
- base_ssp0_clk
- base_ssp1_clk
- base_uart0_clk
- base_uart1_clk
- base_uart2_clk
- base_uart3_clk
- base_audio_clk
description:
Which branch clocks that are available on the CCU depends on the
specific LPC part. Check the user manual for your specific part.
A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-cgu.h>
clock-controller@40051000 {
compatible = "nxp,lpc1850-ccu";
reg = <0x40051000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
clock-names = "base_apb3_clk", "base_apb1_clk",
"base_spifi_clk", "base_cpu_clk",
"base_periph_clk", "base_usb0_clk",
"base_usb1_clk", "base_spi_clk";
};
- |
#include <dt-bindings/clock/lpc18xx-cgu.h>
clock-controller@40052000 {
compatible = "nxp,lpc1850-ccu";
reg = <0x40052000 0x1000>;
#clock-cells = <1>;
clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
clock-names = "base_audio_clk", "base_uart3_clk",
"base_uart2_clk", "base_uart1_clk",
"base_uart0_clk", "base_ssp1_clk",
"base_ssp0_clk", "base_sdio_clk";
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nxp,lpc1850-cgu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC1850 Clock Generation Unit (CGU)
description: >
The CGU generates multiple independent clocks for the core and the
peripheral blocks of the LPC18xx. Each independent clock is called
a base clock and itself is one of the inputs to the two Clock
Control Units (CCUs) which control the branch clocks to the
individual peripherals.
The CGU selects the inputs to the clock generators from multiple
clock sources, controls the clock generation, and routes the outputs
of the clock generators through the clock source bus to the output
stages. Each output stage provides an independent clock source and
corresponds to one of the base clocks for the LPC18xx.
Above text taken from NXP LPC1850 User Manual.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: nxp,lpc1850-cgu
reg:
maxItems: 1
'#clock-cells':
const: 1
description: |
Which base clocks that are available on the CGU depends on the
specific LPC part. Base clocks are numbered from 0 to 27.
Number: Name: Description:
0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
1 BASE_USB0_CLK Base clock for USB0
2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
SPI, and SGPIO
3 BASE_USB1_CLK Base clock for USB1
4 BASE_CPU_CLK System base clock for ARM Cortex-M core
and APB peripheral blocks #0 and #2
5 BASE_SPIFI_CLK Base clock for SPIFI
6 BASE_SPI_CLK Base clock for SPI
7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
9 BASE_APB1_CLK Base clock for APB peripheral block # 1
10 BASE_APB3_CLK Base clock for APB peripheral block # 3
11 BASE_LCD_CLK Base clock for LCD
12 BASE_ADCHS_CLK Base clock for ADCHS
13 BASE_SDIO_CLK Base clock for SD/MMC
14 BASE_SSP0_CLK Base clock for SSP0
15 BASE_SSP1_CLK Base clock for SSP1
16 BASE_UART0_CLK Base clock for UART0
17 BASE_UART1_CLK Base clock for UART1
18 BASE_UART2_CLK Base clock for UART2
19 BASE_UART3_CLK Base clock for UART3
20 BASE_OUT_CLK Base clock for CLKOUT pin
24-21 - Reserved
25 BASE_AUDIO_CLK Base clock for audio system (I2S)
26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
BASE_ADCHS_CLK is only available on LPC4370.
clocks:
maxItems: 5
clock-indices:
minItems: 1
maxItems: 28
clock-output-names:
minItems: 1
maxItems: 28
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@40050000 {
compatible = "nxp,lpc1850-cgu";
reg = <0x40050000 0x1000>;
#clock-cells = <1>;
clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
};

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@ -1,123 +0,0 @@
Imagination Technologies Pistachio SoC clock controllers
========================================================
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
general control, and top general control) which are instantiated individually
from the device-tree.
External clocks:
----------------
There are three external inputs to the clock controllers which should be
defined with the following clock-output-names:
- "xtal": External 52Mhz oscillator (required)
- "audio_clk_in": Alternate audio reference clock (optional)
- "enet_clk_in": Alternate ethernet PHY clock (optional)
Core clock controller:
----------------------
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
co-processor), audio, and several peripherals.
Required properties:
- compatible: Must be "img,pistachio-clk".
- reg: Must contain the base address and length of the core clock controller.
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "xtal" (see "External clocks") and
"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
top-level general control.
Example:
clk_core: clock-controller@18144000 {
compatible = "img,pistachio-clk";
reg = <0x18144000 0x800>;
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
<&cr_top EXT_CLK_ENET_IN>;
clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
#clock-cells = <1>;
};
Peripheral clock controller:
----------------------------
The peripheral clock controller generates clocks for the DDR, ROM, and other
peripherals. The peripheral system clock ("periph_sys") generated by the core
clock controller is the input clock to the peripheral clock controller.
Required properties:
- compatible: Must be "img,pistachio-periph-clk".
- reg: Must contain the base address and length of the peripheral clock
controller.
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "periph_sys", the peripheral system clock generated
by the core clock controller.
Example:
clk_periph: clock-controller@18144800 {
compatible = "img,pistachio-clk-periph";
reg = <0x18144800 0x800>;
clocks = <&clk_core CLK_PERIPH_SYS>;
clock-names = "periph_sys";
#clock-cells = <1>;
};
Peripheral general control:
---------------------------
The peripheral general control block generates system interface clocks and
resets for various peripherals. It also contains miscellaneous peripheral
control registers. The system clock ("sys") generated by the peripheral clock
controller is the input clock to the system clock controller.
Required properties:
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
- reg: Must contain the base address and length of the peripheral general
control registers.
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Must include "sys", the system clock generated by the peripheral
clock controller.
Example:
cr_periph: syscon@18144800 {
compatible = "img,pistachio-cr-periph", "syscon";
reg = <0x18148000 0x1000>;
clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
clock-names = "sys";
#clock-cells = <1>;
};
Top-level general control:
--------------------------
The top-level general control block contains miscellaneous control registers and
gates for the external clocks "audio_clk_in" and "enet_clk_in".
Required properties:
- compatible: Must include "img,pistachio-cr-top" and "syscon".
- reg: Must contain the base address and length of the top-level
control registers.
- clocks: Must contain an entry for each clock in clock-names.
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
"External clocks").
- #clock-cells: Must be 1. The single cell is the clock identifier.
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
Example:
cr_top: syscon@18144800 {
compatible = "img,pistachio-cr-top", "syscon";
reg = <0x18149000 0x200>;
clocks = <&audio_refclk>, <&ext_enet_in>;
clock-names = "audio_clk_in", "enet_clk_in";
#clock-cells = <1>;
};

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@ -1,33 +0,0 @@
Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
Required Properties:
- compatible: has to be "qca,<soctype>-pll" and one of the following
fallbacks:
- "qca,ar7100-pll"
- "qca,ar7240-pll"
- "qca,ar9130-pll"
- "qca,ar9330-pll"
- "qca,ar9340-pll"
- "qca,qca9550-pll"
- reg: Base address and size of the controllers memory area
- clock-names: Name of the input clock, has to be "ref"
- clocks: phandle of the external reference clock
- #clock-cells: has to be one
Optional properties:
- clock-output-names: should be "cpu", "ddr", "ahb"
Example:
pll-controller@18050000 {
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>;
clock-names = "ref";
clocks = <&extosc>;
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
};

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@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Atheros ATH79 PLL controller
maintainers:
- Alban Bedel <albeu@free.fr>
- Antony Pavlov <antonynpavlov@gmail.com>
description: >
The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
properties:
compatible:
oneOf:
- items:
- const: qca,ar9132-pll
- const: qca,ar9130-pll
- items:
- enum:
- qca,ar7100-pll
- qca,ar7240-pll
- qca,ar9130-pll
- qca,ar9330-pll
- qca,ar9340-pll
- qca,qca9530-pll
- qca,qca9550-pll
- qca,qca9560-pll
reg:
maxItems: 1
clock-names:
items:
- const: ref
clocks:
maxItems: 1
'#clock-cells':
const: 1
clock-output-names:
items:
- const: cpu
- const: ddr
- const: ahb
required:
- compatible
- reg
- clock-names
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@18050000 {
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>;
clock-names = "ref";
clocks = <&extosc>;
#clock-cells = <1>;
clock-output-names = "cpu", "ddr", "ahb";
};

2
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@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8250.
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
See also: include/dt-bindings/clock/qcom,camcc-sm8250.h
allOf:
- $ref: qcom,gcc.yaml#

2
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@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks and power domains
on SM6125.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
See also: include/dt-bindings/clock/qcom,dispcc-sm6125.h
properties:
compatible:

2
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@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6350.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
See also: include/dt-bindings/clock/qcom,dispcc-sm6350.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml
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@ -15,7 +15,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ4019.
See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
See also: include/dt-bindings/clock/qcom,gcc-ipq4019.h
allOf:
- $ref: qcom,gcc.yaml#

2
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8074.
See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
See also: include/dt-bindings/clock/qcom,gcc-ipq8074.h
allOf:
- $ref: qcom,gcc.yaml#

2
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8976.
See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
See also: include/dt-bindings/clock/qcom,gcc-msm8976.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8994 and MSM8992.
See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h
See also: include/dt-bindings/clock/qcom,gcc-msm8994.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module which provides the clocks, resets and
power domains on MSM8996.
See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
See also: include/dt-bindings/clock/qcom,gcc-msm8996.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8998.
See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
See also: include/dt-bindings/clock/qcom,gcc-msm8998.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on QCM2290.
See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h
See also: include/dt-bindings/clock/qcom,gcc-qcm2290.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on QCS404.
See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
See also: include/dt-bindings/clock/qcom,gcc-qcs404.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h
See also: include/dt-bindings/clock/qcom,gcc-sc7180.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7280.
See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
See also: include/dt-bindings/clock/qcom,gcc-sc7280.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SC8180x.
See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h
See also: include/dt-bindings/clock/qcom,gcc-sc8180x.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and
power domains on SC8280xp.
See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
See also: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM670 and SDM845
See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
See also: include/dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and
power domains on SDX55
See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h
See also: include/dt-bindings/clock/qcom,gcc-sdx55.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDX65
See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
See also: include/dt-bindings/clock/qcom,gcc-sdx65.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM4250/6115.
See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h
See also: include/dt-bindings/clock/qcom,gcc-sm6115.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6125.
See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
See also: include/dt-bindings/clock/qcom,gcc-sm6125.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6350.
See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h
See also: include/dt-bindings/clock/qcom,gcc-sm6350.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8150.
See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h
See also: include/dt-bindings/clock/qcom,gcc-sm8150.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
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@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8250.
See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h
See also: include/dt-bindings/clock/qcom,gcc-sm8250.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8350.
See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
See also: include/dt-bindings/clock/qcom,gcc-sm8350.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
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@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8450
See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
See also: include/dt-bindings/clock/qcom,gcc-sm8450.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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@ -24,6 +24,8 @@ description:
properties:
compatible:
enum:
- qcom,ipq5018-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq9574-cmn-pll
reg:

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@ -1,34 +0,0 @@
Krait Clock Controller
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,krait-cc-v1"
"qcom,krait-cc-v2"
- #clock-cells:
Usage: required
Value type: <u32>
Definition: must be 1
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the clock parents of hfpll, secondary muxes.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb".
Example:
kraitcc: clock-controller {
compatible = "qcom,krait-cc-v1";
clocks = <&hfpll0>, <&hfpll1>, <&acpu0_aux>, <&acpu1_aux>, <qsb>;
clock-names = "hfpll0", "hfpll1", "acpu0_aux", "acpu1_aux", "qsb";
#clock-cells = <1>;
};

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@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,krait-cc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Clock Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
properties:
compatible:
enum:
- qcom,krait-cc-v1
- qcom,krait-cc-v2
'#clock-cells':
const: 1
clocks:
items:
- description: Parent clock phandle for hfpll0
- description: Parent clock phandle for hfpll1
- description: Parent clock phandle for acpu0_aux
- description: Parent clock phandle for acpu1_aux
- description: Parent clock phandle for qsb
clock-names:
items:
- const: hfpll0
- const: hfpll1
- const: acpu0_aux
- const: acpu1_aux
- const: qsb
required:
- compatible
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false

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@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-camcc.h
properties:
compatible:
const: qcom,milos-camcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Camera AHB clock from GCC
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
clock-controller@adb0000 {
compatible = "qcom,milos-camcc";
reg = <0x0adb0000 0x40000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&gcc GCC_CAMERA_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-dispcc.h
properties:
compatible:
const: qcom,milos-dispcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Display's AHB clock
- description: GPLL0 source from GCC
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
clock-controller@af00000 {
compatible = "qcom,milos-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

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@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-gcc.h
properties:
compatible:
const: qcom,milos-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,milos-gcc";
reg = <0x00100000 0x1f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

53
Documentation/devicetree/bindings/clock/qcom,milos-videocc.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-videocc.h
properties:
compatible:
const: qcom,milos-videocc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: Video AHB clock from GCC
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,milos-gcc.h>
clock-controller@aaf0000 {
compatible = "qcom,milos-videocc";
reg = <0x0aaf0000 0x10000>;
clocks = <&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&sleep_clk>,
<&gcc GCC_VIDEO_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

24
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
View File

@ -38,36 +38,16 @@ properties:
minItems: 7
maxItems: 13
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
protected-clocks:
description:
Protected clock specifier list as per common clock binding
vdd-gfx-supply:
description:
Regulator supply for the GPU_GX GDSC
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
@ -351,6 +331,8 @@ allOf:
- const: dp_link_2x_clk_divsel_five
- const: dp_vco_divided_clk_src_mux
unevaluatedProperties: false
examples:
# Example for MMCC for MSM8960:
- |

2
Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on MSM8998.
See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h
See also: include/dt-bindings/clock/qcom,gpucc-msm8998.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on qcm2290.
See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
See also: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
properties:
compatible:

55
Documentation/devicetree/bindings/clock/qcom,qcs615-dispcc.yaml Normal file
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@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on QCS615.
See also: include/dt-bindings/clock/qcom,qcs615-dispcc.h
properties:
compatible:
const: qcom,qcs615-dispcc
clocks:
items:
- description: Board XO source
- description: GPLL0 clock source from GCC
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Pixel clock from DSI PHY1
- description: Display port PLL link clock
- description: Display port PLL VCO DIV clock
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
clock-controller@af00000 {
compatible = "qcom,qcs615-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dp_phy 0>,
<&mdss_dp_vco 0>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

49
Documentation/devicetree/bindings/clock/qcom,qcs615-gpucc.yaml Normal file
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@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
domains on QCS615 Qualcomm SoCs.
See also: include/dt-bindings/clock/qcom,qcs615-gpucc.h
properties:
compatible:
const: qcom,qcs615-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 GPUCC div branch source
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0x5090000 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GPLL0>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

47
Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml Normal file
View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides clocks, resets and power
domains on QCS615 Qualcomm SoCs.
See also: include/dt-bindings/clock/qcom,qcs615-videocc.h
properties:
compatible:
const: qcom,qcs615-videocc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
clock-controller@ab00000 {
compatible = "qcom,qcs615-videocc";
reg = <0xab00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

2
Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml
View File

@ -14,7 +14,7 @@ description: |
Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control
module which supports the clocks, resets on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
See also: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
View File

@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on QDU1000 and QRU1000
See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h
See also: include/dt-bindings/clock/qcom,qdu1000-gcc.h
properties:
compatible:

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- qcom,milos-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk

15
Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml
View File

@ -17,12 +17,14 @@ description: |
See also:
include/dt-bindings/clock/qcom,qcs8300-camcc.h
include/dt-bindings/clock/qcom,sa8775p-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
properties:
compatible:
enum:
- qcom,qcs8300-camcc
- qcom,sa8775p-camcc
- qcom,sc8280xp-camcc
clocks:
items:
@ -35,6 +37,11 @@ properties:
maxItems: 1
description: MMCX power domain
required-opps:
description:
OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- clocks
@ -43,6 +50,14 @@ required:
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
const: qcom,sc8280xp-camcc
then:
required:
- required-opps
unevaluatedProperties: false

2
Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and
power domains on sa8775p.
See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
See also: include/dt-bindings/clock/qcom,sa8775p-gcc.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
See also: include/dt-bindings/clock/qcom,camcc-sc7180.h
allOf:
- $ref: qcom,gcc.yaml#

2
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h
See also: include/dt-bindings/clock/qcom,dispcc-sc7180.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7180.
See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
See also: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm camera clock control module provides the clocks, resets and
power domains on SC7280.
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
See also: include/dt-bindings/clock/qcom,camcc-sc7280.h
allOf:
- $ref: qcom,gcc.yaml#

2
Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7280.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
See also: include/dt-bindings/clock/qcom,dispcc-sc7280.h
properties:
compatible:

2
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
View File

@ -13,7 +13,7 @@ description: |
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7280.
See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h
See also: include/dt-bindings/clock/qcom,lpass-sc7280.h
properties:
compatible:

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