mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-09-04 20:19:47 +08:00
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
Add initial device tree support for the AX3000 SoC and its evaluation platform. The AX3000 is a multi-core SoC featuring 4 Cortex-A53 cores, Secure Vault, AI Engine and Firewall. It adds support for Cortex-A53 CPUs, timer, UARTs, and I3C controllers on the AX3000 evaluation board. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Harshit Shah <hshah@axiado.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Harshit Shah
Arnd Bergmann
parent
729b770bb4
commit
1f70557790
@ -9,6 +9,7 @@ subdir-y += amlogic
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subdir-y += apm
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subdir-y += apple
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subdir-y += arm
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subdir-y += axiado
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subdir-y += bitmain
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subdir-y += blaize
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subdir-y += broadcom
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2
arch/arm64/boot/dts/axiado/Makefile
Normal file
2
arch/arm64/boot/dts/axiado/Makefile
Normal file
@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
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79
arch/arm64/boot/dts/axiado/ax3000-evk.dts
Normal file
79
arch/arm64/boot/dts/axiado/ax3000-evk.dts
Normal file
@ -0,0 +1,79 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
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*/
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/dts-v1/;
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#include "ax3000.dtsi"
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/ {
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model = "Axiado AX3000 EVK";
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compatible = "axiado,ax3000-evk", "axiado,ax3000";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial3 = &uart3;
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};
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chosen {
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stdout-path = "serial3:115200";
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};
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memory@0 {
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device_type = "memory";
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/* Cortex-A53 will use following memory map */
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reg = <0x00000000 0x3d000000 0x00000000 0x23000000>,
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<0x00000004 0x00000000 0x00000000 0x80000000>;
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};
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};
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/* GPIO bank 0 - 7 */
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&gpio6 {
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status = "okay";
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};
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&gpio7 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&uart3 {
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status = "okay";
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};
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520
arch/arm64/boot/dts/axiado/ax3000.dtsi
Normal file
520
arch/arm64/boot/dts/axiado/ax3000.dtsi
Normal file
@ -0,0 +1,520 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */
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/ {
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model = "Axiado AX3000";
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interrupt-parent = <&gic500>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x3c0013a0>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x3c0013a0>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x3c0013a0>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x3c0013a0>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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cache-size = <0x100000>;
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cache-unified;
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cache-line-size = <64>;
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cache-sets = <1024>;
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cache-level = <2>;
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};
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};
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clocks {
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clk_xin: clock-200000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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clock-output-names = "clk_xin";
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};
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refclk: clock-125000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic500>;
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gic500: interrupt-controller@80300000 {
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compatible = "arm,gic-v3";
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reg = <0x00 0x80300000 0x00 0x10000>,
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<0x00 0x80380000 0x00 0x80000>;
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ranges;
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-controller;
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#redistributor-regions = <1>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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/* GPIO Controller banks 0 - 7 */
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gpio0: gpio-controller@80500000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80500000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio-controller@80580000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80580000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio2: gpio-controller@80600000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80600000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio3: gpio-controller@80680000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80680000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio4: gpio-controller@80700000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80700000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio5: gpio-controller@80780000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80780000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio6: gpio-controller@80800000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80800000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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gpio7: gpio-controller@80880000 {
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compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02";
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reg = <0x00 0x80880000 0x00 0x400>;
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clocks = <&refclk>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "disabled";
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};
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/* I3C Controller 0 - 16 */
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i3c0: i3c@80500400 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80500400 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c1: i3c@80500800 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80500800 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c2: i3c@80580400 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80580400 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c3: i3c@80580800 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80580800 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c4: i3c@80600400 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80600400 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c5: i3c@80600800 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80600800 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c6: i3c@80680400 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80680400 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c7: i3c@80680800 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80680800 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
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#address-cells = <3>;
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#size-cells = <0>;
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status = "disabled";
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};
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i3c8: i3c@80700400 {
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compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
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reg = <0x00 0x80700400 0x00 0x400>;
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clocks = <&refclk &clk_xin>;
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clock-names = "pclk", "sysclk";
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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i2c-scl-hz = <100000>;
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i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c9: i3c@80700800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80700800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c10: i3c@80780400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80780400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c11: i3c@80780800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80780800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c12: i3c@80800400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80800400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c13: i3c@80800800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80800800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c14: i3c@80880400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80880400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c15: i3c@80880800 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80880800 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i3c16: i3c@80620400 {
|
||||
compatible = "axiado,ax3000-i3c", "cdns,i3c-master";
|
||||
reg = <0x00 0x80620400 0x00 0x400>;
|
||||
clocks = <&refclk &clk_xin>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
i2c-scl-hz = <100000>;
|
||||
i3c-scl-hz = <400000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@80520000 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x80520000 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@805a0000 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x805A0000 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@80620000 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x80620000 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@80520800 {
|
||||
compatible = "axiado,ax3000-uart", "cdns,uart-r1p12";
|
||||
reg = <0x00 0x80520800 0x00 0x100>;
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "uart_clk", "pclk";
|
||||
clocks = <&refclk &refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic500>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user