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arm64: cpufeature: Rework ptr auth hwcaps using multi_entry_cap_matches
Open-coding the pointer-auth HWCAPs is a mess and can be avoided by reusing the multi-cap logic from the CPU errata framework. Move the multi_entry_cap_matches code to cpufeature.h and reuse it for the pointer auth HWCAPs. Reviewed-by: Suzuki Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
a56005d321
commit
1e013d0612
@ -321,19 +321,20 @@ struct arm64_cpu_capabilities {
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bool sign;
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unsigned long hwcap;
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};
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/*
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* A list of "matches/cpu_enable" pair for the same
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* "capability" of the same "type" as described by the parent.
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* Only matches(), cpu_enable() and fields relevant to these
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* methods are significant in the list. The cpu_enable is
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* invoked only if the corresponding entry "matches()".
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* However, if a cpu_enable() method is associated
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* with multiple matches(), care should be taken that either
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* the match criteria are mutually exclusive, or that the
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* method is robust against being called multiple times.
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*/
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const struct arm64_cpu_capabilities *match_list;
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};
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/*
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* An optional list of "matches/cpu_enable" pair for the same
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* "capability" of the same "type" as described by the parent.
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* Only matches(), cpu_enable() and fields relevant to these
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* methods are significant in the list. The cpu_enable is
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* invoked only if the corresponding entry "matches()".
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* However, if a cpu_enable() method is associated
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* with multiple matches(), care should be taken that either
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* the match criteria are mutually exclusive, or that the
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* method is robust against being called multiple times.
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*/
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const struct arm64_cpu_capabilities *match_list;
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};
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static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
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@ -353,6 +354,39 @@ cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
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return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
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}
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/*
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* Generic helper for handling capabilties with multiple (match,enable) pairs
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* of call backs, sharing the same capability bit.
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* Iterate over each entry to see if at least one matches.
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*/
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static inline bool
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cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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const struct arm64_cpu_capabilities *caps;
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for (caps = entry->match_list; caps->matches; caps++)
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if (caps->matches(caps, scope))
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return true;
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return false;
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}
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/*
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* Take appropriate action for all matching entries in the shared capability
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* entry.
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*/
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static inline void
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cpucap_multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
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{
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const struct arm64_cpu_capabilities *caps;
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for (caps = entry->match_list; caps->matches; caps++)
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if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
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caps->cpu_enable)
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caps->cpu_enable(caps);
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}
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extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
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extern struct static_key_false arm64_const_caps_ready;
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@ -476,7 +510,6 @@ static inline bool id_aa64pfr0_sve(u64 pfr0)
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void __init setup_cpu_features(void);
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void check_local_cpu_capabilities(void);
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u64 read_sanitised_ftr_reg(u32 id);
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static inline bool cpu_supports_mixed_endian_el0(void)
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@ -507,38 +507,6 @@ cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
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CAP_MIDR_RANGE_LIST(midr_list)
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/*
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* Generic helper for handling capabilties with multiple (match,enable) pairs
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* of call backs, sharing the same capability bit.
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* Iterate over each entry to see if at least one matches.
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*/
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static bool __maybe_unused
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multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
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{
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const struct arm64_cpu_capabilities *caps;
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for (caps = entry->match_list; caps->matches; caps++)
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if (caps->matches(caps, scope))
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return true;
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return false;
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}
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/*
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* Take appropriate action for all matching entries in the shared capability
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* entry.
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*/
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static void __maybe_unused
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multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
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{
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const struct arm64_cpu_capabilities *caps;
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for (caps = entry->match_list; caps->matches; caps++)
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if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
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caps->cpu_enable)
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caps->cpu_enable(caps);
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}
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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/*
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@ -700,7 +668,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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{
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.desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
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.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
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.matches = multi_entry_cap_matches,
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.matches = cpucap_multi_entry_cap_matches,
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.match_list = qcom_erratum_1003_list,
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},
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#endif
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@ -1196,34 +1196,6 @@ static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
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sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
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SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
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}
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static bool has_address_auth(const struct arm64_cpu_capabilities *entry,
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int __unused)
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{
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u64 isar1 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);
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bool api, apa;
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apa = cpuid_feature_extract_unsigned_field(isar1,
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ID_AA64ISAR1_APA_SHIFT) > 0;
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api = cpuid_feature_extract_unsigned_field(isar1,
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ID_AA64ISAR1_API_SHIFT) > 0;
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return apa || api;
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}
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static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
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int __unused)
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{
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u64 isar1 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1);
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bool gpi, gpa;
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gpa = cpuid_feature_extract_unsigned_field(isar1,
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ID_AA64ISAR1_GPA_SHIFT) > 0;
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gpi = cpuid_feature_extract_unsigned_field(isar1,
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ID_AA64ISAR1_GPI_SHIFT) > 0;
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return gpa || gpi;
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}
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#endif /* CONFIG_ARM64_PTR_AUTH */
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static const struct arm64_cpu_capabilities arm64_features[] = {
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@ -1506,19 +1478,58 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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{},
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};
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#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
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{ \
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.desc = #cap, \
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.type = ARM64_CPUCAP_SYSTEM_FEATURE, \
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.matches = has_cpuid_feature, \
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.sys_reg = reg, \
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.field_pos = field, \
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.sign = s, \
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.min_field_value = min_value, \
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.hwcap_type = cap_type, \
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.hwcap = cap, \
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#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
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.matches = has_cpuid_feature, \
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.sys_reg = reg, \
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.field_pos = field, \
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.sign = s, \
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.min_field_value = min_value,
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#define __HWCAP_CAP(name, cap_type, cap) \
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.desc = name, \
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.type = ARM64_CPUCAP_SYSTEM_FEATURE, \
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.hwcap_type = cap_type, \
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.hwcap = cap, \
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#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
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{ \
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__HWCAP_CAP(#cap, cap_type, cap) \
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HWCAP_CPUID_MATCH(reg, field, s, min_value) \
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}
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#define HWCAP_MULTI_CAP(list, cap_type, cap) \
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{ \
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__HWCAP_CAP(#cap, cap_type, cap) \
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.matches = cpucap_multi_entry_cap_matches, \
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.match_list = list, \
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}
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#ifdef CONFIG_ARM64_PTR_AUTH
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static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
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{
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HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
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FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
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},
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{
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HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
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FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
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},
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{},
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};
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static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
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{
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HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
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FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
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},
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{
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HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
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FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
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},
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{},
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};
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#endif
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static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
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@ -1551,10 +1562,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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#endif
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HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
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#ifdef CONFIG_ARM64_PTR_AUTH
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{ .desc = "HWCAP_PACA", .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_address_auth,
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.hwcap_type = CAP_HWCAP, .hwcap = HWCAP_PACA },
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{ .desc = "HWCAP_PACG", .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_generic_auth,
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.hwcap_type = CAP_HWCAP, .hwcap = HWCAP_PACG },
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HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, HWCAP_PACA),
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HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, HWCAP_PACG),
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#endif
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{},
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};
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