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Code

arm64: dts: imx95-19x19-evk: add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 and tpm3

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Add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 tpm3 netc_timer and related phys
regulators pinmux and related child nodes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frank Li 2025-06-06 15:00:41 -04:00 committed by Shawn Guo
parent 947771d00b
commit 02b7adb791
1 changed files with 160 additions and 0 deletions
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160
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
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@ -77,6 +77,29 @@
};
};
flexcan1_phy: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
max-bitrate = <1000000>;
enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>;
};
flexcan2_phy: can-phy1 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
max-bitrate = <1000000>;
enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>;
};
reg_vref_1v8: regulator-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SW";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
@ -204,6 +227,11 @@
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
@ -212,6 +240,20 @@
status = "okay";
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
phys = <&flexcan1_phy>;
status = "disabled";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
phys = <&flexcan2_phy>;
status = "okay";
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
@ -231,6 +273,37 @@
};
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
adp5585: io-expander@34 {
compatible = "adi,adp5585-00", "adi,adp5585";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
gpio-reserved-ranges = <5 1>;
#pwm-cells = <3>;
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
i2c3_gpio_expander_20: gpio@20 {
compatible = "nxp,pcal6408";
#gpio-cells = <2>;
gpio-controller;
reg = <0x20>;
vcc-supply = <&reg_3p3v>;
};
};
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -378,6 +451,24 @@
status = "okay";
};
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "disabled";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&lpspi7 {
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi7>;
cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
@ -418,6 +509,10 @@
};
};
&netc_timer {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
@ -484,6 +579,12 @@
status = "okay";
};
&tpm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm3>;
status = "okay";
};
&usb2 {
dr_mode = "host";
disable-over-current;
@ -588,6 +689,20 @@
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e
IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e
>;
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe
@ -628,6 +743,27 @@
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e
IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e
IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <
IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
@ -656,6 +792,15 @@
>;
};
pinctrl_lpspi7: lpspi7grp {
fsl,pins = <
IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe
IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe
IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe
IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
@ -716,6 +861,12 @@
>;
};
pinctrl_tpm3: tpm3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e
>;
};
pinctrl_tpm6: tpm6grp {
fsl,pins = <
IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e
@ -729,6 +880,15 @@
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e
IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e